imx8qm-cgtqmx8.dts 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2016 Freescale Semiconductor, Inc.
  4. * Copyright 2017 NXP
  5. * Copyright 2017 congatec AG
  6. * Copyright (C) 2019 Oliver Graute <oliver.graute@kococonnector.com>
  7. */
  8. /dts-v1/;
  9. /* First 128KB is for PSCI ATF. */
  10. /memreserve/ 0x80000000 0x00020000;
  11. #include "fsl-imx8qm.dtsi"
  12. / {
  13. model = "Congatec QMX8 Qseven series";
  14. compatible = "fsl,imx8qm-qmx8", "fsl,imx8qm";
  15. chosen {
  16. bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200";
  17. stdout-path = &lpuart0;
  18. };
  19. regulators {
  20. compatible = "simple-bus";
  21. #address-cells = <1>;
  22. #size-cells = <0>;
  23. reg_usdhc2_vmmc: usdhc2_vmmc {
  24. compatible = "regulator-fixed";
  25. regulator-name = "sw-3p3-sd1";
  26. regulator-min-microvolt = <3300000>;
  27. regulator-max-microvolt = <3300000>;
  28. gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>;
  29. enable-active-high;
  30. off-on-delay-us = <3000>;
  31. };
  32. reg_usdhc3_vmmc: usdhc3_vmmc {
  33. compatible = "regulator-fixed";
  34. regulator-name = "sw-3p3-sd2";
  35. regulator-min-microvolt = <3300000>;
  36. regulator-max-microvolt = <3300000>;
  37. gpio = <&gpio4 9 GPIO_ACTIVE_HIGH>;
  38. enable-active-high;
  39. off-on-delay-us = <3000>;
  40. };
  41. };
  42. };
  43. &fec1 {
  44. pinctrl-names = "default";
  45. pinctrl-0 = <&pinctrl_fec1>;
  46. phy-mode = "rgmii";
  47. phy-handle = <&ethphy0>;
  48. fsl,magic-packet;
  49. fsl,rgmii_txc_dly;
  50. fsl,rgmii_rxc_dly;
  51. status = "okay";
  52. mdio {
  53. #address-cells = <1>;
  54. #size-cells = <0>;
  55. ethphy0: ethernet-phy@6 {
  56. compatible = "ethernet-phy-ieee802.3-c22";
  57. reg = <6>;
  58. at803x,eee-disabled;
  59. at803x,vddio-1p8v;
  60. };
  61. };
  62. };
  63. &gpio2 {
  64. status = "okay";
  65. };
  66. &gpio5 {
  67. status = "okay";
  68. };
  69. &i2c0 {
  70. #address-cells = <1>;
  71. #size-cells = <0>;
  72. pinctrl-names = "default";
  73. pinctrl-0 = <&pinctrl_lpi2c0>;
  74. clock-frequency = <100000>;
  75. status = "okay";
  76. rtc_ext: m41t62@68 {
  77. compatible = "st,m41t62";
  78. reg = <0x68>;
  79. };
  80. };
  81. &i2c1 {
  82. #address-cells = <1>;
  83. #size-cells = <0>;
  84. clock-frequency = <100000>;
  85. pinctrl-names = "default";
  86. pinctrl-0 = <&pinctrl_lpi2c1>;
  87. status = "okay";
  88. wm8904: wm8904@1a {
  89. compatible = "wlf,wm8904";
  90. reg = <0x1a>;
  91. clocks = <&clk IMX8QM_AUD_MCLKOUT0>;
  92. clock-names = "mclk";
  93. wlf,shared-lrclk;
  94. /* power-domains = <&pd_mclk_out0>; */
  95. assigned-clocks = <&clk IMX8QM_AUD_PLL0_DIV>,
  96. <&clk IMX8QM_AUD_ACM_AUD_PLL_CLK0_DIV>,
  97. <&clk IMX8QM_AUD_ACM_AUD_REC_CLK0_DIV>,
  98. <&clk IMX8QM_AUD_MCLKOUT0>;
  99. assigned-clock-rates = <786432000>, <49152000>, <24576000>;
  100. };
  101. };
  102. &iomuxc {
  103. pinctrl-names = "default";
  104. pinctrl-0 = <&pinctrl_hog>;
  105. imx8qm-qmx8 {
  106. pinctrl_hog: hoggrp{
  107. fsl,pins = <
  108. SC_P_M40_GPIO0_01_LSIO_GPIO0_IO09 0x00000021
  109. SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x00000021
  110. SC_P_M40_GPIO0_00_LSIO_GPIO0_IO08 0x00000021
  111. SC_P_ESAI1_SCKT_LSIO_GPIO2_IO07 0x00000021
  112. SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021
  113. SC_P_FLEXCAN1_RX_LSIO_GPIO3_IO31 0x00000021
  114. SC_P_ESAI1_TX0_LSIO_GPIO2_IO08 0x00000021
  115. SC_P_FLEXCAN1_TX_LSIO_GPIO4_IO00 0x00000021
  116. SC_P_ESAI1_TX1_LSIO_GPIO2_IO09 0x00000021
  117. >;
  118. };
  119. pinctrl_fec1: fec1grp {
  120. fsl,pins = <
  121. SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000020
  122. SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000020
  123. SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x06000020
  124. SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x06000020
  125. SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x06000020
  126. SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x06000020
  127. SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x06000020
  128. SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x06000020
  129. SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x06000020
  130. SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x06000020
  131. SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x06000020
  132. SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x06000020
  133. SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x06000020
  134. SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x06000020
  135. >;
  136. };
  137. pinctrl_lpi2c0: lpi2c0grp {
  138. fsl,pins = <
  139. SC_P_HDMI_TX0_TS_SCL_DMA_I2C0_SCL 0xc600004c
  140. SC_P_HDMI_TX0_TS_SDA_DMA_I2C0_SDA 0xc600004c
  141. >;
  142. };
  143. pinctrl_lpi2c1: lpi2c1grp {
  144. fsl,pins = <
  145. SC_P_GPT0_CLK_DMA_I2C1_SCL 0xc600004c
  146. SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0xc600004c
  147. >;
  148. };
  149. pinctrl_lpuart0: lpuart0grp {
  150. fsl,pins = <
  151. SC_P_UART0_RX_DMA_UART0_RX 0x06000020
  152. SC_P_UART0_TX_DMA_UART0_TX 0x06000020
  153. >;
  154. };
  155. pinctrl_lpuart1: lpuart1grp {
  156. fsl,pins = <
  157. SC_P_UART1_RX_DMA_UART1_RX 0x06000020
  158. SC_P_UART1_TX_DMA_UART1_TX 0x06000020
  159. SC_P_UART1_CTS_B_DMA_UART1_CTS_B 0x06000020
  160. SC_P_UART1_RTS_B_DMA_UART1_RTS_B 0x06000020
  161. >;
  162. };
  163. pinctrl_lpuart3: lpuart3grp {
  164. fsl,pins = <
  165. SC_P_M41_GPIO0_00_DMA_UART3_RX 0x06000020
  166. SC_P_M41_GPIO0_01_DMA_UART3_TX 0x06000020
  167. >;
  168. };
  169. pinctrl_mlb: mlbgrp {
  170. fsl,pins = <
  171. SC_P_MLB_SIG_CONN_MLB_SIG 0x21
  172. SC_P_MLB_CLK_CONN_MLB_CLK 0x21
  173. SC_P_MLB_DATA_CONN_MLB_DATA 0x21
  174. >;
  175. };
  176. pinctrl_isl29023: isl29023grp {
  177. fsl,pins = <
  178. SC_P_ADC_IN2_LSIO_GPIO3_IO20 0x00000021
  179. >;
  180. };
  181. pinctrl_usdhc1: usdhc1grp {
  182. fsl,pins = <
  183. SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041
  184. SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021
  185. SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021
  186. SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021
  187. SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021
  188. SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021
  189. SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021
  190. SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021
  191. SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021
  192. SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021
  193. SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000041
  194. SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021
  195. >;
  196. };
  197. pinctrl_usdhc1_100mhz: usdhc1grp100mhz {
  198. fsl,pins = <
  199. SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
  200. SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
  201. SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
  202. SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
  203. SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
  204. SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
  205. SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
  206. SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
  207. SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
  208. SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
  209. SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
  210. SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
  211. >;
  212. };
  213. pinctrl_usdhc1_200mhz: usdhc1grp200mhz {
  214. fsl,pins = <
  215. SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040
  216. SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020
  217. SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020
  218. SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020
  219. SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020
  220. SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020
  221. SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020
  222. SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020
  223. SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020
  224. SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020
  225. SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x00000040
  226. SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020
  227. >;
  228. };
  229. pinctrl_usdhc2_gpio: usdhc2grpgpio {
  230. fsl,pins = <
  231. SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021
  232. SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021
  233. SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021
  234. >;
  235. };
  236. pinctrl_usdhc2: usdhc2grp {
  237. fsl,pins = <
  238. SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041
  239. SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021
  240. SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021
  241. SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021
  242. SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021
  243. SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021
  244. SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021
  245. >;
  246. };
  247. pinctrl_usdhc2_100mhz: usdhc2grp100mhz {
  248. fsl,pins = <
  249. SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
  250. SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
  251. SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
  252. SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
  253. SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
  254. SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
  255. SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
  256. >;
  257. };
  258. pinctrl_usdhc2_200mhz: usdhc2grp200mhz {
  259. fsl,pins = <
  260. SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040
  261. SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020
  262. SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020
  263. SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020
  264. SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020
  265. SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020
  266. SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020
  267. >;
  268. };
  269. pinctrl_usdhc3_gpio: usdhc3grpgpio {
  270. fsl,pins = <
  271. SC_P_USDHC2_RESET_B_LSIO_GPIO4_IO09 0x00000021
  272. SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021
  273. >;
  274. };
  275. pinctrl_usdhc3: usdhc3grp {
  276. fsl,pins = <
  277. SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041
  278. SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021
  279. SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021
  280. SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021
  281. SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021
  282. SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021
  283. SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000021
  284. >;
  285. };
  286. pinctrl_usdhc3_100mhz: usdhc3grp100mhz {
  287. fsl,pins = <
  288. SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
  289. SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
  290. SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
  291. SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
  292. SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
  293. SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
  294. SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
  295. >;
  296. };
  297. pinctrl_usdhc3_200mhz: usdhc3grp200mhz {
  298. fsl,pins = <
  299. SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000040
  300. SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000020
  301. SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000020
  302. SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000020
  303. SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000020
  304. SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000020
  305. SC_P_USDHC2_VSELECT_CONN_USDHC2_VSELECT 0x00000020
  306. >;
  307. };
  308. };
  309. };
  310. &lpuart0 { /* console */
  311. pinctrl-names = "default";
  312. pinctrl-0 = <&pinctrl_lpuart0>;
  313. status = "okay";
  314. };
  315. &lpuart1 { /* Q7 connector */
  316. pinctrl-names = "default";
  317. pinctrl-0 = <&pinctrl_lpuart1>;
  318. status = "okay";
  319. };
  320. &pd_dma_lpuart0 {
  321. debug_console;
  322. };
  323. &usdhc1 {
  324. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  325. pinctrl-0 = <&pinctrl_usdhc1>;
  326. pinctrl-1 = <&pinctrl_usdhc1_100mhz>;
  327. pinctrl-2 = <&pinctrl_usdhc1_200mhz>;
  328. bus-width = <8>;
  329. non-removable;
  330. status = "okay";
  331. };
  332. &usdhc2 {
  333. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  334. pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>;
  335. pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>;
  336. pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>;
  337. bus-width = <4>;
  338. cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>;
  339. wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>;
  340. vmmc-supply = <&reg_usdhc2_vmmc>;
  341. fsl,tuning-start-tap = <20>;
  342. fsl,tuning-step= <2>;
  343. status = "okay";
  344. };
  345. &usdhc3 {
  346. pinctrl-names = "default", "state_100mhz", "state_200mhz";
  347. pinctrl-0 = <&pinctrl_usdhc3>, <&pinctrl_usdhc3_gpio>;
  348. pinctrl-1 = <&pinctrl_usdhc3_100mhz>, <&pinctrl_usdhc3_gpio>;
  349. pinctrl-2 = <&pinctrl_usdhc3_200mhz>, <&pinctrl_usdhc3_gpio>;
  350. bus-width = <4>;
  351. cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>;
  352. vmmc-supply = <&reg_usdhc3_vmmc>;
  353. fsl,tuning-start-tap = <20>;
  354. fsl,tuning-step= <2>;
  355. status = "okay";
  356. };