jh7100.dtsi 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629
  1. // SPDX-License-Identifier: (GPL-2.0 OR MIT)
  2. /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
  3. /dts-v1/;
  4. #include <dt-bindings/clock/starfive-jh7100.h>
  5. #include <dt-bindings/starfive_fb.h>
  6. / {
  7. #address-cells = <2>;
  8. #size-cells = <2>;
  9. compatible = "starfive,jh7100";
  10. cpus {
  11. #address-cells = <1>;
  12. #size-cells = <0>;
  13. cpu@0 {
  14. compatible = "sifive,u74-mc", "riscv";
  15. d-cache-block-size = <64>;
  16. d-cache-sets = <64>;
  17. d-cache-size = <32768>;
  18. d-tlb-sets = <1>;
  19. d-tlb-size = <32>;
  20. device_type = "cpu";
  21. i-cache-block-size = <64>;
  22. i-cache-sets = <64>;
  23. i-cache-size = <32768>;
  24. i-tlb-sets = <1>;
  25. i-tlb-size = <32>;
  26. mmu-type = "riscv,sv39";
  27. next-level-cache = <&ccache>;
  28. reg = <0>;
  29. riscv,isa = "rv64imafdc";
  30. starfive,itim = <&itim0>;
  31. status = "okay";
  32. tlb-split;
  33. cpu0_intc: interrupt-controller {
  34. #interrupt-cells = <1>;
  35. compatible = "riscv,cpu-intc";
  36. interrupt-controller;
  37. };
  38. };
  39. cpu@1 {
  40. compatible = "sifive,u74-mc", "riscv";
  41. d-cache-block-size = <64>;
  42. d-cache-sets = <64>;
  43. d-cache-size = <32768>;
  44. d-tlb-sets = <1>;
  45. d-tlb-size = <32>;
  46. device_type = "cpu";
  47. i-cache-block-size = <64>;
  48. i-cache-sets = <64>;
  49. i-cache-size = <32768>;
  50. i-tlb-sets = <1>;
  51. i-tlb-size = <32>;
  52. mmu-type = "riscv,sv39";
  53. next-level-cache = <&ccache>;
  54. reg = <1>;
  55. riscv,isa = "rv64imafdc";
  56. starfive,itim = <&itim1>;
  57. status = "okay";
  58. tlb-split;
  59. cpu1_intc: interrupt-controller {
  60. #interrupt-cells = <1>;
  61. compatible = "riscv,cpu-intc";
  62. interrupt-controller;
  63. };
  64. };
  65. };
  66. osc_sys: osc_sys {
  67. compatible = "fixed-clock";
  68. #clock-cells = <0>;
  69. /* This value must be overridden by the board */
  70. clock-frequency = <0>;
  71. };
  72. osc_aud: osc_aud {
  73. compatible = "fixed-clock";
  74. #clock-cells = <0>;
  75. /* This value must be overridden by the board */
  76. clock-frequency = <0>;
  77. };
  78. soc {
  79. compatible = "simple-bus";
  80. interrupt-parent = <&plic>;
  81. #address-cells = <2>;
  82. #size-cells = <2>;
  83. ranges;
  84. ccache: cache-controller@2010000 {
  85. cache-block-size = <64>;
  86. cache-line-size = <64>;
  87. cache-level = <2>;
  88. cache-sets = <2048>;
  89. cache-size = <2097152>;
  90. cache-unified;
  91. #size-cells = <2>;
  92. compatible = "sifive,fu540-c000-ccache", "sifive,fu740-c000-ccache", "starfive,ccache0", "cache";
  93. interrupts = <128 131 129 130>;
  94. /*next-level-cache = <&L40 &L36>;*/
  95. reg = <0x0 0x2010000 0x0 0x1000>,
  96. <0x0 0x8000000 0x0 0x2000000>;
  97. reg-names = "control", "sideband";
  98. ranges = <0x0 0x0 0x0 0x80000000 0x8 0x0>;
  99. };
  100. dtim: dtim@1000000 {
  101. compatible = "starfive,dtim0";
  102. reg = <0x0 0x1000000 0x0 0x2000>;
  103. reg-names = "mem";
  104. };
  105. itim0: itim@1808000 {
  106. compatible = "starfive,itim0";
  107. reg = <0x0 0x1808000 0x0 0x8000>;
  108. reg-names = "mem";
  109. };
  110. itim1: itim@1820000 {
  111. compatible = "starfive,itim0";
  112. reg = <0x0 0x1820000 0x0 0x8000>;
  113. reg-names = "mem";
  114. };
  115. clint: clint@2000000 {
  116. #interrupt-cells = <1>;
  117. compatible = "riscv,clint0";
  118. interrupts-extended = <&cpu0_intc 3>,
  119. <&cpu0_intc 7>,
  120. <&cpu1_intc 3>,
  121. <&cpu1_intc 7>;
  122. reg = <0x0 0x2000000 0x0 0x10000>;
  123. reg-names = "control";
  124. };
  125. plic: interrupt-controller@c000000 {
  126. #interrupt-cells = <1>;
  127. compatible = "riscv,plic0";
  128. interrupt-controller;
  129. interrupts-extended = <&cpu0_intc 11>,
  130. <&cpu0_intc 9>,
  131. <&cpu1_intc 11>,
  132. <&cpu1_intc 9>;
  133. reg = <0x0 0xc000000 0x0 0x4000000>;
  134. reg-names = "control";
  135. riscv,max-priority = <7>;
  136. riscv,ndev = <127>;
  137. };
  138. clkgen: clock-controller@11800000 {
  139. compatible = "starfive,jh7100-clkgen";
  140. reg = <0x0 0x11800000 0x0 0x10000>;
  141. clocks = <&osc_sys>, <&osc_aud>;
  142. clock-names = "osc_sys", "osc_aud";
  143. #clock-cells = <1>;
  144. };
  145. uart0: serial@11870000 {
  146. compatible = "snps,dw-apb-uart";
  147. interrupts = <92>;
  148. reg = <0x0 0x11870000 0x0 0x10000>;
  149. reg-io-width = <4>;
  150. reg-shift = <2>;
  151. clocks = <&clkgen JH7100_CLK_UART0_CORE>,
  152. <&clkgen JH7100_CLK_UART0_APB>;
  153. clock-names = "baudclk", "apb_pclk";
  154. current-clock = <74250000>;
  155. current-speed = <115200>;
  156. status = "disabled";
  157. };
  158. uart1: serial@11880000 {
  159. compatible = "snps,dw-apb-uart";
  160. interrupts = <93>;
  161. reg = <0x0 0x11880000 0x0 0x10000>;
  162. reg-io-width = <4>;
  163. reg-shift = <2>;
  164. clocks = <&clkgen JH7100_CLK_UART1_CORE>,
  165. <&clkgen JH7100_CLK_UART1_APB>;
  166. clock-names = "baudclk", "apb_pclk";
  167. current-clock = <74250000>;
  168. current-speed = <115200>;
  169. status = "disabled";
  170. };
  171. uart2: serial@12430000 {
  172. compatible = "snps,dw-apb-uart";
  173. interrupts = <72>;
  174. reg = <0x0 0x12430000 0x0 0x10000>;
  175. reg-io-width = <4>;
  176. reg-shift = <2>;
  177. clocks = <&clkgen JH7100_CLK_UART2_CORE>,
  178. <&clkgen JH7100_CLK_UART2_APB>;
  179. clock-names = "baudclk", "apb_pclk";
  180. current-clock = <100000000>;
  181. current-speed = <115200>;
  182. status = "disabled";
  183. };
  184. uart3: serial@12440000 {
  185. compatible = "snps,dw-apb-uart", "starfive,uart0";
  186. interrupts = <73>;
  187. reg = <0x0 0x12440000 0x0 0x10000>;
  188. reg-io-width = <4>;
  189. reg-shift = <2>;
  190. clocks = <&clkgen JH7100_CLK_UART3_CORE>,
  191. <&clkgen JH7100_CLK_UART3_APB>;
  192. clock-names = "baudclk", "apb_pclk";
  193. current-clock = <100000000>;
  194. current-speed = <115200>;
  195. status = "disabled";
  196. };
  197. dma2p: dma-controller@100b0000 {
  198. compatible = "snps,axi-dma-1.01a";
  199. reg = <0x0 0x100b0000 0x0 0x10000>;
  200. clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
  201. <&clkgen JH7100_CLK_SGDMA2P_AHB>;
  202. clock-names = "core-clk", "cfgr-clk";
  203. interrupts = <2>;
  204. #dma-cells = <1>;
  205. dma-channels = <4>;
  206. snps,dma-masters = <1>;
  207. snps,data-width = <4>;
  208. snps,block-size = <4096 4096 4096 4096>;
  209. snps,priority = <0 1 2 3>;
  210. snps,axi-max-burst-len = <128>;
  211. status = "okay";
  212. };
  213. dma1p: dma-controller@10500000 {
  214. compatible = "snps,axi-dma-1.01a";
  215. reg = <0x0 0x10500000 0x0 0x10000>;
  216. clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
  217. <&clkgen JH7100_CLK_SGDMA1P_BUS>;
  218. clock-names = "core-clk", "cfgr-clk";
  219. interrupts = <1>;
  220. #dma-cells = <1>;
  221. dma-channels = <16>;
  222. snps,dma-masters = <1>;
  223. snps,data-width = <3>;
  224. snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
  225. snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
  226. snps,axi-max-burst-len = <64>;
  227. status = "okay";
  228. };
  229. usb3: usb@104c0000 {
  230. compatible = "cdns,usb3";
  231. reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
  232. <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
  233. <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
  234. reg-names = "otg", "xhci", "dev";
  235. interrupts = <44>, <52>, <43>;
  236. interrupt-names = "host", "peripheral", "otg";
  237. phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
  238. maximum-speed = "super-speed";
  239. status = "disabled";
  240. };
  241. gpio: gpio@11910000 {
  242. compatible = "starfive,jh7100-gpio";
  243. reg = <0x0 0x11910000 0x0 0x10000>;
  244. clocks = <&clkgen JH7100_CLK_GPIO_APB>;
  245. gpio-controller;
  246. #gpio-cells = <2>;
  247. interrupt-controller;
  248. #interrupt-cells = <2>;
  249. interrupts = <32>;
  250. };
  251. i2c0: i2c@118b0000 {
  252. #address-cells = <1>;
  253. #size-cells = <0>;
  254. compatible = "snps,designware-i2c";
  255. reg = <0x0 0x118b0000 0x0 0x10000>;
  256. interrupts = <96>;
  257. clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
  258. <&clkgen JH7100_CLK_I2C0_APB>;
  259. clock-names = "ref", "pclk";
  260. status = "disabled";
  261. };
  262. i2c1: i2c@118c0000 {
  263. #address-cells = <1>;
  264. #size-cells = <0>;
  265. compatible = "snps,designware-i2c";
  266. reg = <0x0 0x118c0000 0x0 0x10000>;
  267. interrupts = <97>;
  268. clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
  269. <&clkgen JH7100_CLK_I2C1_APB>;
  270. clock-names = "ref", "pclk";
  271. status = "disabled";
  272. };
  273. i2c2: i2c@12450000 {
  274. #address-cells = <1>;
  275. #size-cells = <0>;
  276. compatible = "snps,designware-i2c";
  277. reg = <0x0 0x12450000 0x0 0x10000>;
  278. interrupts = <74>;
  279. clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
  280. <&clkgen JH7100_CLK_I2C2_APB>;
  281. clock-names = "ref", "pclk";
  282. status = "disabled";
  283. };
  284. i2c3: i2c@12460000 {
  285. #address-cells = <1>;
  286. #size-cells = <0>;
  287. compatible = "snps,designware-i2c";
  288. reg = <0x0 0x12460000 0x0 0x10000>;
  289. interrupts = <75>;
  290. clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
  291. <&clkgen JH7100_CLK_I2C3_APB>;
  292. clock-names = "ref", "pclk";
  293. status = "disabled";
  294. };
  295. trng: trng@118d0000 {
  296. compatible = "starfive,vic-rng";
  297. reg = <0x0 0x118d0000 0x0 0x10000>;
  298. interrupts = <98>;
  299. clocks = <&clkgen JH7100_CLK_TRNG_APB>;
  300. };
  301. crypto: crypto@100d0000 {
  302. compatible = "starfive,vic-sec";
  303. reg = <0x0 0x100d0000 0x0 0x20000>,
  304. <0x0 0x11800234 0x0 0xc>;
  305. reg-names = "secmem", "secclk";
  306. interrupts = <31>;
  307. clocks = <&clkgen JH7100_CLK_SEC_AHB>;
  308. };
  309. /* gmac device configuration */
  310. stmmac_axi_setup: stmmac-axi-config {
  311. snps,wr_osr_lmt = <0xf>;
  312. snps,rd_osr_lmt = <0xf>;
  313. snps,blen = <256 128 64 32 0 0 0>;
  314. };
  315. gmac: ethernet@10020000 {
  316. compatible = "snps,dwmac";
  317. reg = <0x0 0x10020000 0x0 0x10000>;
  318. interrupts = <6 7>;
  319. interrupt-names = "macirq", "eth_wake_irq";
  320. max-frame-size = <9000>;
  321. phy-mode = "rgmii-txid";
  322. snps,multicast-filter-bins = <256>;
  323. snps,perfect-filter-entries = <128>;
  324. rx-fifo-depth = <32768>;
  325. tx-fifo-depth = <16384>;
  326. clocks = <&clkgen JH7100_CLK_GMAC_AHB>,
  327. <&clkgen JH7100_CLK_GMAC_AHB>,
  328. <&clkgen JH7100_CLK_GMAC_PTP_REF>;
  329. clock-names = "stmmaceth", "pclk", "ptp_ref";
  330. snps,fixed-burst;
  331. snps,no-pbl-x8 = <1>;
  332. /*snps,force_sf_dma_mode;*/
  333. snps,force_thresh_dma_mode;
  334. snps,axi-config = <&stmmac_axi_setup>;
  335. };
  336. nvdla@11940000 {
  337. compatible = "nvidia,nvdla_os_initial";
  338. interrupts = <22>;
  339. memory-region = <&nvdla_reserved>;
  340. reg = <0x0 0x11940000 0x0 0x40000>;
  341. status = "okay";
  342. };
  343. jpu: coadj12@11900000 {
  344. compatible = "cm,codaj12-jpu-1";
  345. reg = <0x0 0x11900000 0x0 0x300>;
  346. memory-region = <&jpu_reserved>;
  347. interrupts = <24>;
  348. clocks = <&clkgen JH7100_CLK_JPEG_APB>;
  349. clock-names = "jpege";
  350. reg-names = "control";
  351. status = "okay";
  352. };
  353. vpu_dec: vpu_dec@118f0000 {
  354. compatible = "c&m,cm511-vpu";
  355. reg = <0 0x118f0000 0 0x10000>;
  356. //memory-region = <&vpu_reserved>;
  357. interrupts = <23>;
  358. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  359. clock-names = "vcodec";
  360. status = "okay";
  361. };
  362. vpu_enc: vpu_enc@118e0000 {
  363. compatible = "cm,cm521-vpu";
  364. reg = <0x0 0x118e0000 0x0 0x4000>;
  365. interrupts = <26>;
  366. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  367. clock-names = "vcodec";
  368. reg-names = "control";
  369. };
  370. ptc: pwm@12490000 {
  371. compatible = "starfive,pwm0";
  372. reg = <0x0 0x12490000 0x0 0x10000>;
  373. reg-names = "control";
  374. sifive,approx-period = <100000000>;
  375. clocks = <&clkgen JH7100_CLK_PWM_APB>;
  376. #pwm-cells = <3>;
  377. sifive,npwm = <8>;
  378. };
  379. qspi: spi@11860000 {
  380. compatible = "cadence,qspi","cdns,qspi-nor";
  381. #address-cells = <1>;
  382. #size-cells = <0>;
  383. reg = <0x0 0x11860000 0x0 0x10000>,
  384. <0x0 0x20000000 0x0 0x20000000>;
  385. interrupts = <3>;
  386. clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
  387. cdns,fifo-depth = <256>;
  388. cdns,fifo-width = <4>;
  389. cdns,trigger-address = <0x0>;
  390. status = "okay";
  391. spi-max-frequency = <250000000>;
  392. };
  393. spi0: spi@11890000 {
  394. compatible = "snps,dw-apb-ssi";
  395. #address-cells = <1>;
  396. #size-cells = <0>;
  397. interrupts = <94>;
  398. reg = <0x0 0x11890000 0x0 0x10000>;
  399. clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
  400. <&clkgen JH7100_CLK_SPI0_APB>;
  401. clock-names = "ssi_clk", "pclk";
  402. status = "disabled";
  403. };
  404. spi1: spi@118a0000 {
  405. compatible = "snps,dw-apb-ssi";
  406. #address-cells = <1>;
  407. #size-cells = <0>;
  408. interrupts = <95>;
  409. reg = <0x0 0x118a0000 0x0 0x10000>;
  410. clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
  411. <&clkgen JH7100_CLK_SPI1_APB>;
  412. clock-names = "ssi_clk", "pclk";
  413. status = "disabled";
  414. };
  415. spi2: spi@12410000 {
  416. compatible = "snps,dw-apb-ssi";
  417. #address-cells = <1>;
  418. #size-cells = <0>;
  419. interrupts = <70>;
  420. reg = <0x0 0x12410000 0x0 0x10000>;
  421. clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
  422. <&clkgen JH7100_CLK_SPI2_APB>;
  423. clock-names = "ssi_clk", "pclk";
  424. status = "disabled";
  425. };
  426. spi3: spi@12420000 {
  427. compatible = "snps,dw-apb-ssi";
  428. #address-cells = <1>;
  429. #size-cells = <0>;
  430. interrupts = <71>;
  431. reg = <0x0 0x12420000 0x0 0x10000>;
  432. clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
  433. <&clkgen JH7100_CLK_SPI3_APB>;
  434. clock-names = "ssi_clk", "pclk";
  435. status = "disabled";
  436. };
  437. xrp@f0000000 {
  438. compatible = "cdns,xrp";
  439. reg = <0x0 0xf0000000 0x0 0x01ffffff>,
  440. <0x10 0x72000000 0x0 0x00001000>,
  441. <0x10 0x72001000 0x0 0x00fff000>,
  442. <0x0 0x124b0000 0x0 0x00010000>;
  443. clocks = <&clkgen JH7100_CLK_VP6_CORE>;
  444. firmware-name = "vp6_elf";
  445. dsp-irq = <19 20>;
  446. dsp-irq-src = <0x20 0x21>;
  447. intc-irq-mode = <1>;
  448. intc-irq = <0 1>;
  449. interrupts = <27 28>;
  450. #address-cells = <1>;
  451. #size-cells = <1>;
  452. ranges = <0x40000000 0x0 0x40000000 0x01000000>,
  453. <0xb0000000 0x10 0x70000000 0x3000000>;
  454. dsp@0 {
  455. };
  456. };
  457. sdio0: mmc@10000000 {
  458. compatible = "snps,dw-mshc";
  459. reg = <0x0 0x10000000 0x0 0x10000>;
  460. interrupts = <4>;
  461. clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
  462. <&clkgen JH7100_CLK_SDIO0_CCLKINT>;
  463. clock-names = "biu", "ciu";
  464. clock-frequency = <100000000>;
  465. data-addr = <0>;
  466. fifo-depth = <32>;
  467. fifo-watermark-aligned;
  468. bus-width = <4>;
  469. max-frequency = <10000000>;
  470. status = "disabled";
  471. };
  472. sdio1: mmc@10010000 {
  473. compatible = "snps,dw-mshc";
  474. reg = <0x0 0x10010000 0x0 0x10000>;
  475. interrupts = <5>;
  476. clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
  477. <&clkgen JH7100_CLK_SDIO1_CCLKINT>;
  478. clock-names = "biu", "ciu";
  479. clock-frequency = <100000000>;
  480. data-addr = <0>;
  481. fifo-depth = <32>;
  482. fifo-watermark-aligned;
  483. bus-width = <4>;
  484. max-frequency = <50000000>;
  485. status = "disabled";
  486. };
  487. sfivefb: sfivefb@12000000 {
  488. compatible = "starfive,vpp-lcdc";
  489. interrupts = <101>, <103>;
  490. interrupt-names = "lcdc_irq", "vpp1_irq";
  491. reg = <0x0 0x12000000 0x0 0x10000>,
  492. <0x0 0x12100000 0x0 0x10000>,
  493. <0x0 0x12040000 0x0 0x10000>,
  494. <0x0 0x12080000 0x0 0x10000>,
  495. <0x0 0x120c0000 0x0 0x10000>,
  496. <0x0 0x12240000 0x0 0x10000>,
  497. <0x0 0x12250000 0x0 0x10000>,
  498. <0x0 0x12260000 0x0 0x10000>;
  499. reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
  500. memory-region = <&sffb_reserved>;
  501. #if 0 // FIXME uart clocks can't be right for lcdc
  502. clocks = <&clkgen JH7100_CLK_UART>,
  503. <&clkgen JH7100_CLK_APB2>;
  504. #endif
  505. clock-names = "baudclk", "apb_pclk";
  506. ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
  507. status = "disabled";
  508. };
  509. vin_sysctl: vin_sysctl@19800000 {
  510. compatible = "starfive,stf-vin";
  511. reg = <0x0 0x19800000 0x0 0x10000>,
  512. <0x0 0x19810000 0x0 0x10000>,
  513. <0x0 0x19820000 0x0 0x10000>,
  514. <0x0 0x19830000 0x0 0x10000>,
  515. <0x0 0x19840000 0x0 0x10000>,
  516. <0x0 0x19870000 0x0 0x30000>,
  517. <0x0 0x198a0000 0x0 0x30000>,
  518. <0x0 0x11800000 0x0 0x10000>,
  519. <0x0 0x11840000 0x0 0x10000>,
  520. <0x0 0x11858000 0x0 0x10000>;
  521. reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
  522. "isp0", "isp1", "tclk", "trst", "iopad";
  523. interrupts = <119 109>;
  524. memory-region = <&vin_reserved>;
  525. /*defaule config for imx219 vin&isp*/
  526. format = <SRC_CSI2RX_VIN_ISP>;
  527. frame-width = <800>;
  528. frame-height =<480>;
  529. isp0_enable;
  530. csi-lane = <2>;
  531. csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
  532. csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
  533. csi-clane-swap = /bits/ 8 <0>;
  534. csi-clane-pn-swap = /bits/ 8 <0>;
  535. csi-mipiID = <0>;
  536. csi-width = <1920>;
  537. csi-height = <1080>;
  538. csi-dt = <0x2b>;
  539. };
  540. sfctemp: tmon@124a0000 {
  541. compatible = "starfive,jh7100-temp";
  542. reg = <0x0 0x124a0000 0x0 0x10000>;
  543. #thermal-sensor-cells = <0>;
  544. interrupts = <122>;
  545. };
  546. thermal-zones {
  547. cpu-thermal {
  548. polling-delay-passive = <250>;
  549. polling-delay = <15000>;
  550. thermal-sensors = <&sfctemp>;
  551. cooling-maps {
  552. };
  553. trips {
  554. cpu_alert0: cpu_alert0 {
  555. /* milliCelsius */
  556. temperature = <75000>;
  557. hysteresis = <2000>;
  558. type = "passive";
  559. };
  560. cpu_crit: cpu_crit {
  561. /* milliCelsius */
  562. temperature = <90000>;
  563. hysteresis = <2000>;
  564. type = "critical";
  565. };
  566. };
  567. };
  568. };
  569. otp: otp@11810000 {
  570. compatible = "starfive,fu740-otp";
  571. reg = <0x0 0x11810000 0x0 0x10000>;
  572. fuse-count = <0x200>;
  573. clocks = <&clkgen JH7100_CLK_OTP_APB>;
  574. };
  575. };
  576. };