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- // SPDX-License-Identifier: (GPL-2.0 OR MIT)
- /* Copyright (c) 2021 StarFive Technology Co., Ltd. */
- /dts-v1/;
- #include <dt-bindings/clock/starfive-jh7100.h>
- #include <dt-bindings/starfive_fb.h>
- / {
- #address-cells = <2>;
- #size-cells = <2>;
- compatible = "starfive,jh7100";
- cpus {
- #address-cells = <1>;
- #size-cells = <0>;
- cpu@0 {
- compatible = "sifive,u74-mc", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&ccache>;
- reg = <0>;
- riscv,isa = "rv64imafdc";
- starfive,itim = <&itim0>;
- status = "okay";
- tlb-split;
- cpu0_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- cpu@1 {
- compatible = "sifive,u74-mc", "riscv";
- d-cache-block-size = <64>;
- d-cache-sets = <64>;
- d-cache-size = <32768>;
- d-tlb-sets = <1>;
- d-tlb-size = <32>;
- device_type = "cpu";
- i-cache-block-size = <64>;
- i-cache-sets = <64>;
- i-cache-size = <32768>;
- i-tlb-sets = <1>;
- i-tlb-size = <32>;
- mmu-type = "riscv,sv39";
- next-level-cache = <&ccache>;
- reg = <1>;
- riscv,isa = "rv64imafdc";
- starfive,itim = <&itim1>;
- status = "okay";
- tlb-split;
- cpu1_intc: interrupt-controller {
- #interrupt-cells = <1>;
- compatible = "riscv,cpu-intc";
- interrupt-controller;
- };
- };
- };
- osc_sys: osc_sys {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
- osc_aud: osc_aud {
- compatible = "fixed-clock";
- #clock-cells = <0>;
- /* This value must be overridden by the board */
- clock-frequency = <0>;
- };
- soc {
- compatible = "simple-bus";
- interrupt-parent = <&plic>;
- #address-cells = <2>;
- #size-cells = <2>;
- ranges;
- ccache: cache-controller@2010000 {
- cache-block-size = <64>;
- cache-line-size = <64>;
- cache-level = <2>;
- cache-sets = <2048>;
- cache-size = <2097152>;
- cache-unified;
- #size-cells = <2>;
- compatible = "sifive,fu540-c000-ccache", "sifive,fu740-c000-ccache", "starfive,ccache0", "cache";
- interrupts = <128 131 129 130>;
- /*next-level-cache = <&L40 &L36>;*/
- reg = <0x0 0x2010000 0x0 0x1000>,
- <0x0 0x8000000 0x0 0x2000000>;
- reg-names = "control", "sideband";
- ranges = <0x0 0x0 0x0 0x80000000 0x8 0x0>;
- };
- dtim: dtim@1000000 {
- compatible = "starfive,dtim0";
- reg = <0x0 0x1000000 0x0 0x2000>;
- reg-names = "mem";
- };
- itim0: itim@1808000 {
- compatible = "starfive,itim0";
- reg = <0x0 0x1808000 0x0 0x8000>;
- reg-names = "mem";
- };
- itim1: itim@1820000 {
- compatible = "starfive,itim0";
- reg = <0x0 0x1820000 0x0 0x8000>;
- reg-names = "mem";
- };
- clint: clint@2000000 {
- #interrupt-cells = <1>;
- compatible = "riscv,clint0";
- interrupts-extended = <&cpu0_intc 3>,
- <&cpu0_intc 7>,
- <&cpu1_intc 3>,
- <&cpu1_intc 7>;
- reg = <0x0 0x2000000 0x0 0x10000>;
- reg-names = "control";
- };
- plic: interrupt-controller@c000000 {
- #interrupt-cells = <1>;
- compatible = "riscv,plic0";
- interrupt-controller;
- interrupts-extended = <&cpu0_intc 11>,
- <&cpu0_intc 9>,
- <&cpu1_intc 11>,
- <&cpu1_intc 9>;
- reg = <0x0 0xc000000 0x0 0x4000000>;
- reg-names = "control";
- riscv,max-priority = <7>;
- riscv,ndev = <127>;
- };
- clkgen: clock-controller@11800000 {
- compatible = "starfive,jh7100-clkgen";
- reg = <0x0 0x11800000 0x0 0x10000>;
- clocks = <&osc_sys>, <&osc_aud>;
- clock-names = "osc_sys", "osc_aud";
- #clock-cells = <1>;
- };
- uart0: serial@11870000 {
- compatible = "snps,dw-apb-uart";
- interrupts = <92>;
- reg = <0x0 0x11870000 0x0 0x10000>;
- reg-io-width = <4>;
- reg-shift = <2>;
- clocks = <&clkgen JH7100_CLK_UART0_CORE>,
- <&clkgen JH7100_CLK_UART0_APB>;
- clock-names = "baudclk", "apb_pclk";
- current-clock = <74250000>;
- current-speed = <115200>;
- status = "disabled";
- };
- uart1: serial@11880000 {
- compatible = "snps,dw-apb-uart";
- interrupts = <93>;
- reg = <0x0 0x11880000 0x0 0x10000>;
- reg-io-width = <4>;
- reg-shift = <2>;
- clocks = <&clkgen JH7100_CLK_UART1_CORE>,
- <&clkgen JH7100_CLK_UART1_APB>;
- clock-names = "baudclk", "apb_pclk";
- current-clock = <74250000>;
- current-speed = <115200>;
- status = "disabled";
- };
- uart2: serial@12430000 {
- compatible = "snps,dw-apb-uart";
- interrupts = <72>;
- reg = <0x0 0x12430000 0x0 0x10000>;
- reg-io-width = <4>;
- reg-shift = <2>;
- clocks = <&clkgen JH7100_CLK_UART2_CORE>,
- <&clkgen JH7100_CLK_UART2_APB>;
- clock-names = "baudclk", "apb_pclk";
- current-clock = <100000000>;
- current-speed = <115200>;
- status = "disabled";
- };
- uart3: serial@12440000 {
- compatible = "snps,dw-apb-uart", "starfive,uart0";
- interrupts = <73>;
- reg = <0x0 0x12440000 0x0 0x10000>;
- reg-io-width = <4>;
- reg-shift = <2>;
- clocks = <&clkgen JH7100_CLK_UART3_CORE>,
- <&clkgen JH7100_CLK_UART3_APB>;
- clock-names = "baudclk", "apb_pclk";
- current-clock = <100000000>;
- current-speed = <115200>;
- status = "disabled";
- };
- dma2p: dma-controller@100b0000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x0 0x100b0000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SGDMA2P_AXI>,
- <&clkgen JH7100_CLK_SGDMA2P_AHB>;
- clock-names = "core-clk", "cfgr-clk";
- interrupts = <2>;
- #dma-cells = <1>;
- dma-channels = <4>;
- snps,dma-masters = <1>;
- snps,data-width = <4>;
- snps,block-size = <4096 4096 4096 4096>;
- snps,priority = <0 1 2 3>;
- snps,axi-max-burst-len = <128>;
- status = "okay";
- };
- dma1p: dma-controller@10500000 {
- compatible = "snps,axi-dma-1.01a";
- reg = <0x0 0x10500000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SGDMA1P_AXI>,
- <&clkgen JH7100_CLK_SGDMA1P_BUS>;
- clock-names = "core-clk", "cfgr-clk";
- interrupts = <1>;
- #dma-cells = <1>;
- dma-channels = <16>;
- snps,dma-masters = <1>;
- snps,data-width = <3>;
- snps,block-size = <4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096 4096>;
- snps,priority = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
- snps,axi-max-burst-len = <64>;
- status = "okay";
- };
- usb3: usb@104c0000 {
- compatible = "cdns,usb3";
- reg = <0x0 0x104c0000 0x0 0x10000>, // memory area for HOST registers
- <0x0 0x104d0000 0x0 0x10000>, // memory area for DEVICE registers
- <0x0 0x104e0000 0x0 0x10000>; // memory area for OTG/DRD registers
- reg-names = "otg", "xhci", "dev";
- interrupts = <44>, <52>, <43>;
- interrupt-names = "host", "peripheral", "otg";
- phy-names = "cdns3,usb3-phy", "cdns3,usb2-phy";
- maximum-speed = "super-speed";
- status = "disabled";
- };
- gpio: gpio@11910000 {
- compatible = "starfive,jh7100-gpio";
- reg = <0x0 0x11910000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_GPIO_APB>;
- gpio-controller;
- #gpio-cells = <2>;
- interrupt-controller;
- #interrupt-cells = <2>;
- interrupts = <32>;
- };
- i2c0: i2c@118b0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x0 0x118b0000 0x0 0x10000>;
- interrupts = <96>;
- clocks = <&clkgen JH7100_CLK_I2C0_CORE>,
- <&clkgen JH7100_CLK_I2C0_APB>;
- clock-names = "ref", "pclk";
- status = "disabled";
- };
- i2c1: i2c@118c0000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x0 0x118c0000 0x0 0x10000>;
- interrupts = <97>;
- clocks = <&clkgen JH7100_CLK_I2C1_CORE>,
- <&clkgen JH7100_CLK_I2C1_APB>;
- clock-names = "ref", "pclk";
- status = "disabled";
- };
- i2c2: i2c@12450000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x0 0x12450000 0x0 0x10000>;
- interrupts = <74>;
- clocks = <&clkgen JH7100_CLK_I2C2_CORE>,
- <&clkgen JH7100_CLK_I2C2_APB>;
- clock-names = "ref", "pclk";
- status = "disabled";
- };
- i2c3: i2c@12460000 {
- #address-cells = <1>;
- #size-cells = <0>;
- compatible = "snps,designware-i2c";
- reg = <0x0 0x12460000 0x0 0x10000>;
- interrupts = <75>;
- clocks = <&clkgen JH7100_CLK_I2C3_CORE>,
- <&clkgen JH7100_CLK_I2C3_APB>;
- clock-names = "ref", "pclk";
- status = "disabled";
- };
- trng: trng@118d0000 {
- compatible = "starfive,vic-rng";
- reg = <0x0 0x118d0000 0x0 0x10000>;
- interrupts = <98>;
- clocks = <&clkgen JH7100_CLK_TRNG_APB>;
- };
- crypto: crypto@100d0000 {
- compatible = "starfive,vic-sec";
- reg = <0x0 0x100d0000 0x0 0x20000>,
- <0x0 0x11800234 0x0 0xc>;
- reg-names = "secmem", "secclk";
- interrupts = <31>;
- clocks = <&clkgen JH7100_CLK_SEC_AHB>;
- };
- /* gmac device configuration */
- stmmac_axi_setup: stmmac-axi-config {
- snps,wr_osr_lmt = <0xf>;
- snps,rd_osr_lmt = <0xf>;
- snps,blen = <256 128 64 32 0 0 0>;
- };
- gmac: ethernet@10020000 {
- compatible = "snps,dwmac";
- reg = <0x0 0x10020000 0x0 0x10000>;
- interrupts = <6 7>;
- interrupt-names = "macirq", "eth_wake_irq";
- max-frame-size = <9000>;
- phy-mode = "rgmii-txid";
- snps,multicast-filter-bins = <256>;
- snps,perfect-filter-entries = <128>;
- rx-fifo-depth = <32768>;
- tx-fifo-depth = <16384>;
- clocks = <&clkgen JH7100_CLK_GMAC_AHB>,
- <&clkgen JH7100_CLK_GMAC_AHB>,
- <&clkgen JH7100_CLK_GMAC_PTP_REF>;
- clock-names = "stmmaceth", "pclk", "ptp_ref";
- snps,fixed-burst;
- snps,no-pbl-x8 = <1>;
- /*snps,force_sf_dma_mode;*/
- snps,force_thresh_dma_mode;
- snps,axi-config = <&stmmac_axi_setup>;
- };
- nvdla@11940000 {
- compatible = "nvidia,nvdla_os_initial";
- interrupts = <22>;
- memory-region = <&nvdla_reserved>;
- reg = <0x0 0x11940000 0x0 0x40000>;
- status = "okay";
- };
- jpu: coadj12@11900000 {
- compatible = "cm,codaj12-jpu-1";
- reg = <0x0 0x11900000 0x0 0x300>;
- memory-region = <&jpu_reserved>;
- interrupts = <24>;
- clocks = <&clkgen JH7100_CLK_JPEG_APB>;
- clock-names = "jpege";
- reg-names = "control";
- status = "okay";
- };
- vpu_dec: vpu_dec@118f0000 {
- compatible = "c&m,cm511-vpu";
- reg = <0 0x118f0000 0 0x10000>;
- //memory-region = <&vpu_reserved>;
- interrupts = <23>;
- clocks = <&clkgen JH7100_CLK_VP6_CORE>;
- clock-names = "vcodec";
- status = "okay";
- };
- vpu_enc: vpu_enc@118e0000 {
- compatible = "cm,cm521-vpu";
- reg = <0x0 0x118e0000 0x0 0x4000>;
- interrupts = <26>;
- clocks = <&clkgen JH7100_CLK_VP6_CORE>;
- clock-names = "vcodec";
- reg-names = "control";
- };
- ptc: pwm@12490000 {
- compatible = "starfive,pwm0";
- reg = <0x0 0x12490000 0x0 0x10000>;
- reg-names = "control";
- sifive,approx-period = <100000000>;
- clocks = <&clkgen JH7100_CLK_PWM_APB>;
- #pwm-cells = <3>;
- sifive,npwm = <8>;
- };
- qspi: spi@11860000 {
- compatible = "cadence,qspi","cdns,qspi-nor";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x0 0x11860000 0x0 0x10000>,
- <0x0 0x20000000 0x0 0x20000000>;
- interrupts = <3>;
- clocks = <&clkgen JH7100_CLK_QSPI_AHB>;
- cdns,fifo-depth = <256>;
- cdns,fifo-width = <4>;
- cdns,trigger-address = <0x0>;
- status = "okay";
- spi-max-frequency = <250000000>;
- };
- spi0: spi@11890000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <94>;
- reg = <0x0 0x11890000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SPI0_CORE>,
- <&clkgen JH7100_CLK_SPI0_APB>;
- clock-names = "ssi_clk", "pclk";
- status = "disabled";
- };
- spi1: spi@118a0000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <95>;
- reg = <0x0 0x118a0000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SPI1_CORE>,
- <&clkgen JH7100_CLK_SPI1_APB>;
- clock-names = "ssi_clk", "pclk";
- status = "disabled";
- };
- spi2: spi@12410000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <70>;
- reg = <0x0 0x12410000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SPI2_CORE>,
- <&clkgen JH7100_CLK_SPI2_APB>;
- clock-names = "ssi_clk", "pclk";
- status = "disabled";
- };
- spi3: spi@12420000 {
- compatible = "snps,dw-apb-ssi";
- #address-cells = <1>;
- #size-cells = <0>;
- interrupts = <71>;
- reg = <0x0 0x12420000 0x0 0x10000>;
- clocks = <&clkgen JH7100_CLK_SPI3_CORE>,
- <&clkgen JH7100_CLK_SPI3_APB>;
- clock-names = "ssi_clk", "pclk";
- status = "disabled";
- };
- xrp@f0000000 {
- compatible = "cdns,xrp";
- reg = <0x0 0xf0000000 0x0 0x01ffffff>,
- <0x10 0x72000000 0x0 0x00001000>,
- <0x10 0x72001000 0x0 0x00fff000>,
- <0x0 0x124b0000 0x0 0x00010000>;
- clocks = <&clkgen JH7100_CLK_VP6_CORE>;
- firmware-name = "vp6_elf";
- dsp-irq = <19 20>;
- dsp-irq-src = <0x20 0x21>;
- intc-irq-mode = <1>;
- intc-irq = <0 1>;
- interrupts = <27 28>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges = <0x40000000 0x0 0x40000000 0x01000000>,
- <0xb0000000 0x10 0x70000000 0x3000000>;
- dsp@0 {
- };
- };
- sdio0: mmc@10000000 {
- compatible = "snps,dw-mshc";
- reg = <0x0 0x10000000 0x0 0x10000>;
- interrupts = <4>;
- clocks = <&clkgen JH7100_CLK_SDIO0_AHB>,
- <&clkgen JH7100_CLK_SDIO0_CCLKINT>;
- clock-names = "biu", "ciu";
- clock-frequency = <100000000>;
- data-addr = <0>;
- fifo-depth = <32>;
- fifo-watermark-aligned;
- bus-width = <4>;
- max-frequency = <10000000>;
- status = "disabled";
- };
- sdio1: mmc@10010000 {
- compatible = "snps,dw-mshc";
- reg = <0x0 0x10010000 0x0 0x10000>;
- interrupts = <5>;
- clocks = <&clkgen JH7100_CLK_SDIO1_AHB>,
- <&clkgen JH7100_CLK_SDIO1_CCLKINT>;
- clock-names = "biu", "ciu";
- clock-frequency = <100000000>;
- data-addr = <0>;
- fifo-depth = <32>;
- fifo-watermark-aligned;
- bus-width = <4>;
- max-frequency = <50000000>;
- status = "disabled";
- };
- sfivefb: sfivefb@12000000 {
- compatible = "starfive,vpp-lcdc";
- interrupts = <101>, <103>;
- interrupt-names = "lcdc_irq", "vpp1_irq";
- reg = <0x0 0x12000000 0x0 0x10000>,
- <0x0 0x12100000 0x0 0x10000>,
- <0x0 0x12040000 0x0 0x10000>,
- <0x0 0x12080000 0x0 0x10000>,
- <0x0 0x120c0000 0x0 0x10000>,
- <0x0 0x12240000 0x0 0x10000>,
- <0x0 0x12250000 0x0 0x10000>,
- <0x0 0x12260000 0x0 0x10000>;
- reg-names = "lcdc", "dsitx", "vpp0", "vpp1", "vpp2", "clk", "rst", "sys";
- memory-region = <&sffb_reserved>;
- #if 0 // FIXME uart clocks can't be right for lcdc
- clocks = <&clkgen JH7100_CLK_UART>,
- <&clkgen JH7100_CLK_APB2>;
- #endif
- clock-names = "baudclk", "apb_pclk";
- ddr-format = <WIN_FMT_RGB565>;/*LCDC win_format*/
- status = "disabled";
- };
- vin_sysctl: vin_sysctl@19800000 {
- compatible = "starfive,stf-vin";
- reg = <0x0 0x19800000 0x0 0x10000>,
- <0x0 0x19810000 0x0 0x10000>,
- <0x0 0x19820000 0x0 0x10000>,
- <0x0 0x19830000 0x0 0x10000>,
- <0x0 0x19840000 0x0 0x10000>,
- <0x0 0x19870000 0x0 0x30000>,
- <0x0 0x198a0000 0x0 0x30000>,
- <0x0 0x11800000 0x0 0x10000>,
- <0x0 0x11840000 0x0 0x10000>,
- <0x0 0x11858000 0x0 0x10000>;
- reg-names = "mipi0", "vclk", "vrst", "mipi1", "sctrl",
- "isp0", "isp1", "tclk", "trst", "iopad";
- interrupts = <119 109>;
- memory-region = <&vin_reserved>;
- /*defaule config for imx219 vin&isp*/
- format = <SRC_CSI2RX_VIN_ISP>;
- frame-width = <800>;
- frame-height =<480>;
- isp0_enable;
- csi-lane = <2>;
- csi-dlane-swaps = /bits/ 8 <1>,/bits/ 8 <2>,/bits/ 8 <3>,/bits/ 8 <4>;
- csi-dlane-pn-swaps = /bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>,/bits/ 8 <0>;
- csi-clane-swap = /bits/ 8 <0>;
- csi-clane-pn-swap = /bits/ 8 <0>;
- csi-mipiID = <0>;
- csi-width = <1920>;
- csi-height = <1080>;
- csi-dt = <0x2b>;
- };
- sfctemp: tmon@124a0000 {
- compatible = "starfive,jh7100-temp";
- reg = <0x0 0x124a0000 0x0 0x10000>;
- #thermal-sensor-cells = <0>;
- interrupts = <122>;
- };
- thermal-zones {
- cpu-thermal {
- polling-delay-passive = <250>;
- polling-delay = <15000>;
- thermal-sensors = <&sfctemp>;
- cooling-maps {
- };
- trips {
- cpu_alert0: cpu_alert0 {
- /* milliCelsius */
- temperature = <75000>;
- hysteresis = <2000>;
- type = "passive";
- };
- cpu_crit: cpu_crit {
- /* milliCelsius */
- temperature = <90000>;
- hysteresis = <2000>;
- type = "critical";
- };
- };
- };
- };
- otp: otp@11810000 {
- compatible = "starfive,fu740-otp";
- reg = <0x0 0x11810000 0x0 0x10000>;
- fuse-count = <0x200>;
- clocks = <&clkgen JH7100_CLK_OTP_APB>;
- };
- };
- };
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