board.c 28 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012-2013 Henrik Nordstrom <henrik@henriknordstrom.net>
  4. * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
  5. *
  6. * (C) Copyright 2007-2011
  7. * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
  8. * Tom Cubie <tangliang@allwinnertech.com>
  9. *
  10. * Some board init for the Allwinner A10-evb board.
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <env.h>
  15. #include <hang.h>
  16. #include <image.h>
  17. #include <init.h>
  18. #include <log.h>
  19. #include <mmc.h>
  20. #include <axp_pmic.h>
  21. #include <generic-phy.h>
  22. #include <phy-sun4i-usb.h>
  23. #include <asm/arch/clock.h>
  24. #include <asm/arch/cpu.h>
  25. #include <asm/arch/display.h>
  26. #include <asm/arch/dram.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/mmc.h>
  29. #include <asm/arch/prcm.h>
  30. #include <asm/arch/spl.h>
  31. #include <linux/delay.h>
  32. #include <u-boot/crc.h>
  33. #ifndef CONFIG_ARM64
  34. #include <asm/armv7.h>
  35. #endif
  36. #include <asm/gpio.h>
  37. #include <asm/io.h>
  38. #include <u-boot/crc.h>
  39. #include <env_internal.h>
  40. #include <linux/libfdt.h>
  41. #include <fdt_support.h>
  42. #include <nand.h>
  43. #include <net.h>
  44. #include <spl.h>
  45. #include <sy8106a.h>
  46. #include <asm/setup.h>
  47. #if defined CONFIG_VIDEO_LCD_PANEL_I2C && !(defined CONFIG_SPL_BUILD)
  48. /* So that we can use pin names in Kconfig and sunxi_name_to_gpio() */
  49. int soft_i2c_gpio_sda;
  50. int soft_i2c_gpio_scl;
  51. static int soft_i2c_board_init(void)
  52. {
  53. int ret;
  54. soft_i2c_gpio_sda = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SDA);
  55. if (soft_i2c_gpio_sda < 0) {
  56. printf("Error invalid soft i2c sda pin: '%s', err %d\n",
  57. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, soft_i2c_gpio_sda);
  58. return soft_i2c_gpio_sda;
  59. }
  60. ret = gpio_request(soft_i2c_gpio_sda, "soft-i2c-sda");
  61. if (ret) {
  62. printf("Error requesting soft i2c sda pin: '%s', err %d\n",
  63. CONFIG_VIDEO_LCD_PANEL_I2C_SDA, ret);
  64. return ret;
  65. }
  66. soft_i2c_gpio_scl = sunxi_name_to_gpio(CONFIG_VIDEO_LCD_PANEL_I2C_SCL);
  67. if (soft_i2c_gpio_scl < 0) {
  68. printf("Error invalid soft i2c scl pin: '%s', err %d\n",
  69. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, soft_i2c_gpio_scl);
  70. return soft_i2c_gpio_scl;
  71. }
  72. ret = gpio_request(soft_i2c_gpio_scl, "soft-i2c-scl");
  73. if (ret) {
  74. printf("Error requesting soft i2c scl pin: '%s', err %d\n",
  75. CONFIG_VIDEO_LCD_PANEL_I2C_SCL, ret);
  76. return ret;
  77. }
  78. return 0;
  79. }
  80. #else
  81. static int soft_i2c_board_init(void) { return 0; }
  82. #endif
  83. DECLARE_GLOBAL_DATA_PTR;
  84. void i2c_init_board(void)
  85. {
  86. #ifdef CONFIG_I2C0_ENABLE
  87. #if defined(CONFIG_MACH_SUN4I) || \
  88. defined(CONFIG_MACH_SUN5I) || \
  89. defined(CONFIG_MACH_SUN7I) || \
  90. defined(CONFIG_MACH_SUN8I_R40)
  91. sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN4I_GPB_TWI0);
  92. sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN4I_GPB_TWI0);
  93. clock_twi_onoff(0, 1);
  94. #elif defined(CONFIG_MACH_SUN6I)
  95. sunxi_gpio_set_cfgpin(SUNXI_GPH(14), SUN6I_GPH_TWI0);
  96. sunxi_gpio_set_cfgpin(SUNXI_GPH(15), SUN6I_GPH_TWI0);
  97. clock_twi_onoff(0, 1);
  98. #elif defined(CONFIG_MACH_SUN8I_V3S)
  99. sunxi_gpio_set_cfgpin(SUNXI_GPB(6), SUN8I_V3S_GPB_TWI0);
  100. sunxi_gpio_set_cfgpin(SUNXI_GPB(7), SUN8I_V3S_GPB_TWI0);
  101. clock_twi_onoff(0, 1);
  102. #elif defined(CONFIG_MACH_SUN8I)
  103. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN8I_GPH_TWI0);
  104. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN8I_GPH_TWI0);
  105. clock_twi_onoff(0, 1);
  106. #elif defined(CONFIG_MACH_SUN50I)
  107. sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_GPH_TWI0);
  108. sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_GPH_TWI0);
  109. clock_twi_onoff(0, 1);
  110. #endif
  111. #endif
  112. #ifdef CONFIG_I2C1_ENABLE
  113. #if defined(CONFIG_MACH_SUN4I) || \
  114. defined(CONFIG_MACH_SUN7I) || \
  115. defined(CONFIG_MACH_SUN8I_R40)
  116. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN4I_GPB_TWI1);
  117. sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN4I_GPB_TWI1);
  118. clock_twi_onoff(1, 1);
  119. #elif defined(CONFIG_MACH_SUN5I)
  120. sunxi_gpio_set_cfgpin(SUNXI_GPB(15), SUN5I_GPB_TWI1);
  121. sunxi_gpio_set_cfgpin(SUNXI_GPB(16), SUN5I_GPB_TWI1);
  122. clock_twi_onoff(1, 1);
  123. #elif defined(CONFIG_MACH_SUN6I)
  124. sunxi_gpio_set_cfgpin(SUNXI_GPH(16), SUN6I_GPH_TWI1);
  125. sunxi_gpio_set_cfgpin(SUNXI_GPH(17), SUN6I_GPH_TWI1);
  126. clock_twi_onoff(1, 1);
  127. #elif defined(CONFIG_MACH_SUN8I)
  128. sunxi_gpio_set_cfgpin(SUNXI_GPH(4), SUN8I_GPH_TWI1);
  129. sunxi_gpio_set_cfgpin(SUNXI_GPH(5), SUN8I_GPH_TWI1);
  130. clock_twi_onoff(1, 1);
  131. #elif defined(CONFIG_MACH_SUN50I)
  132. sunxi_gpio_set_cfgpin(SUNXI_GPH(2), SUN50I_GPH_TWI1);
  133. sunxi_gpio_set_cfgpin(SUNXI_GPH(3), SUN50I_GPH_TWI1);
  134. clock_twi_onoff(1, 1);
  135. #endif
  136. #endif
  137. #ifdef CONFIG_I2C2_ENABLE
  138. #if defined(CONFIG_MACH_SUN4I) || \
  139. defined(CONFIG_MACH_SUN7I) || \
  140. defined(CONFIG_MACH_SUN8I_R40)
  141. sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN4I_GPB_TWI2);
  142. sunxi_gpio_set_cfgpin(SUNXI_GPB(21), SUN4I_GPB_TWI2);
  143. clock_twi_onoff(2, 1);
  144. #elif defined(CONFIG_MACH_SUN5I)
  145. sunxi_gpio_set_cfgpin(SUNXI_GPB(17), SUN5I_GPB_TWI2);
  146. sunxi_gpio_set_cfgpin(SUNXI_GPB(18), SUN5I_GPB_TWI2);
  147. clock_twi_onoff(2, 1);
  148. #elif defined(CONFIG_MACH_SUN6I)
  149. sunxi_gpio_set_cfgpin(SUNXI_GPH(18), SUN6I_GPH_TWI2);
  150. sunxi_gpio_set_cfgpin(SUNXI_GPH(19), SUN6I_GPH_TWI2);
  151. clock_twi_onoff(2, 1);
  152. #elif defined(CONFIG_MACH_SUN8I)
  153. sunxi_gpio_set_cfgpin(SUNXI_GPE(12), SUN8I_GPE_TWI2);
  154. sunxi_gpio_set_cfgpin(SUNXI_GPE(13), SUN8I_GPE_TWI2);
  155. clock_twi_onoff(2, 1);
  156. #elif defined(CONFIG_MACH_SUN50I)
  157. sunxi_gpio_set_cfgpin(SUNXI_GPE(14), SUN50I_GPE_TWI2);
  158. sunxi_gpio_set_cfgpin(SUNXI_GPE(15), SUN50I_GPE_TWI2);
  159. clock_twi_onoff(2, 1);
  160. #endif
  161. #endif
  162. #ifdef CONFIG_I2C3_ENABLE
  163. #if defined(CONFIG_MACH_SUN6I)
  164. sunxi_gpio_set_cfgpin(SUNXI_GPG(10), SUN6I_GPG_TWI3);
  165. sunxi_gpio_set_cfgpin(SUNXI_GPG(11), SUN6I_GPG_TWI3);
  166. clock_twi_onoff(3, 1);
  167. #elif defined(CONFIG_MACH_SUN7I) || \
  168. defined(CONFIG_MACH_SUN8I_R40)
  169. sunxi_gpio_set_cfgpin(SUNXI_GPI(0), SUN7I_GPI_TWI3);
  170. sunxi_gpio_set_cfgpin(SUNXI_GPI(1), SUN7I_GPI_TWI3);
  171. clock_twi_onoff(3, 1);
  172. #endif
  173. #endif
  174. #ifdef CONFIG_I2C4_ENABLE
  175. #if defined(CONFIG_MACH_SUN7I) || \
  176. defined(CONFIG_MACH_SUN8I_R40)
  177. sunxi_gpio_set_cfgpin(SUNXI_GPI(2), SUN7I_GPI_TWI4);
  178. sunxi_gpio_set_cfgpin(SUNXI_GPI(3), SUN7I_GPI_TWI4);
  179. clock_twi_onoff(4, 1);
  180. #endif
  181. #endif
  182. #ifdef CONFIG_R_I2C_ENABLE
  183. #ifdef CONFIG_MACH_SUN50I
  184. clock_twi_onoff(5, 1);
  185. sunxi_gpio_set_cfgpin(SUNXI_GPL(8), SUN50I_GPL_R_TWI);
  186. sunxi_gpio_set_cfgpin(SUNXI_GPL(9), SUN50I_GPL_R_TWI);
  187. #else
  188. clock_twi_onoff(5, 1);
  189. sunxi_gpio_set_cfgpin(SUNXI_GPL(0), SUN8I_H3_GPL_R_TWI);
  190. sunxi_gpio_set_cfgpin(SUNXI_GPL(1), SUN8I_H3_GPL_R_TWI);
  191. #endif
  192. #endif
  193. }
  194. #if defined(CONFIG_ENV_IS_IN_MMC) && defined(CONFIG_ENV_IS_IN_FAT)
  195. enum env_location env_get_location(enum env_operation op, int prio)
  196. {
  197. switch (prio) {
  198. case 0:
  199. return ENVL_FAT;
  200. case 1:
  201. return ENVL_MMC;
  202. default:
  203. return ENVL_UNKNOWN;
  204. }
  205. }
  206. #endif
  207. #ifdef CONFIG_DM_MMC
  208. static void mmc_pinmux_setup(int sdc);
  209. #endif
  210. /* add board specific code here */
  211. int board_init(void)
  212. {
  213. __maybe_unused int id_pfr1, ret, satapwr_pin, macpwr_pin;
  214. gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100);
  215. #ifndef CONFIG_ARM64
  216. asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1));
  217. debug("id_pfr1: 0x%08x\n", id_pfr1);
  218. /* Generic Timer Extension available? */
  219. if ((id_pfr1 >> CPUID_ARM_GENTIMER_SHIFT) & 0xf) {
  220. uint32_t freq;
  221. debug("Setting CNTFRQ\n");
  222. /*
  223. * CNTFRQ is a secure register, so we will crash if we try to
  224. * write this from the non-secure world (read is OK, though).
  225. * In case some bootcode has already set the correct value,
  226. * we avoid the risk of writing to it.
  227. */
  228. asm volatile("mrc p15, 0, %0, c14, c0, 0" : "=r"(freq));
  229. if (freq != COUNTER_FREQUENCY) {
  230. debug("arch timer frequency is %d Hz, should be %d, fixing ...\n",
  231. freq, COUNTER_FREQUENCY);
  232. #ifdef CONFIG_NON_SECURE
  233. printf("arch timer frequency is wrong, but cannot adjust it\n");
  234. #else
  235. asm volatile("mcr p15, 0, %0, c14, c0, 0"
  236. : : "r"(COUNTER_FREQUENCY));
  237. #endif
  238. }
  239. }
  240. #endif /* !CONFIG_ARM64 */
  241. ret = axp_gpio_init();
  242. if (ret)
  243. return ret;
  244. /* strcmp() would look better, but doesn't get optimised away. */
  245. if (CONFIG_SATAPWR[0]) {
  246. satapwr_pin = sunxi_name_to_gpio(CONFIG_SATAPWR);
  247. if (satapwr_pin >= 0) {
  248. gpio_request(satapwr_pin, "satapwr");
  249. gpio_direction_output(satapwr_pin, 1);
  250. /*
  251. * Give the attached SATA device time to power-up
  252. * to avoid link timeouts
  253. */
  254. mdelay(500);
  255. }
  256. }
  257. if (CONFIG_MACPWR[0]) {
  258. macpwr_pin = sunxi_name_to_gpio(CONFIG_MACPWR);
  259. if (macpwr_pin >= 0) {
  260. gpio_request(macpwr_pin, "macpwr");
  261. gpio_direction_output(macpwr_pin, 1);
  262. }
  263. }
  264. #ifdef CONFIG_DM_I2C
  265. /*
  266. * Temporary workaround for enabling I2C clocks until proper sunxi DM
  267. * clk, reset and pinctrl drivers land.
  268. */
  269. i2c_init_board();
  270. #endif
  271. #ifdef CONFIG_DM_MMC
  272. /*
  273. * Temporary workaround for enabling MMC clocks until a sunxi DM
  274. * pinctrl driver lands.
  275. */
  276. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  277. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  278. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  279. #endif
  280. #endif /* CONFIG_DM_MMC */
  281. /* Uses dm gpio code so do this here and not in i2c_init_board() */
  282. return soft_i2c_board_init();
  283. }
  284. /*
  285. * On older SoCs the SPL is actually at address zero, so using NULL as
  286. * an error value does not work.
  287. */
  288. #define INVALID_SPL_HEADER ((void *)~0UL)
  289. static struct boot_file_head * get_spl_header(uint8_t req_version)
  290. {
  291. struct boot_file_head *spl = (void *)(ulong)SPL_ADDR;
  292. uint8_t spl_header_version = spl->spl_signature[3];
  293. /* Is there really the SPL header (still) there? */
  294. if (memcmp(spl->spl_signature, SPL_SIGNATURE, 3) != 0)
  295. return INVALID_SPL_HEADER;
  296. if (spl_header_version < req_version) {
  297. printf("sunxi SPL version mismatch: expected %u, got %u\n",
  298. req_version, spl_header_version);
  299. return INVALID_SPL_HEADER;
  300. }
  301. return spl;
  302. }
  303. static const char *get_spl_dt_name(void)
  304. {
  305. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  306. /* Check if there is a DT name stored in the SPL header. */
  307. if (spl != INVALID_SPL_HEADER && spl->dt_name_offset)
  308. return (char *)spl + spl->dt_name_offset;
  309. return NULL;
  310. }
  311. int dram_init(void)
  312. {
  313. struct boot_file_head *spl = get_spl_header(SPL_DRAM_HEADER_VERSION);
  314. if (spl == INVALID_SPL_HEADER)
  315. gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0,
  316. PHYS_SDRAM_0_SIZE);
  317. else
  318. gd->ram_size = (phys_addr_t)spl->dram_size << 20;
  319. if (gd->ram_size > CONFIG_SUNXI_DRAM_MAX_SIZE)
  320. gd->ram_size = CONFIG_SUNXI_DRAM_MAX_SIZE;
  321. return 0;
  322. }
  323. #if defined(CONFIG_NAND_SUNXI)
  324. static void nand_pinmux_setup(void)
  325. {
  326. unsigned int pin;
  327. for (pin = SUNXI_GPC(0); pin <= SUNXI_GPC(19); pin++)
  328. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  329. #if defined CONFIG_MACH_SUN4I || defined CONFIG_MACH_SUN7I
  330. for (pin = SUNXI_GPC(20); pin <= SUNXI_GPC(22); pin++)
  331. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_NAND);
  332. #endif
  333. /* sun4i / sun7i do have a PC23, but it is not used for nand,
  334. * only sun7i has a PC24 */
  335. #ifdef CONFIG_MACH_SUN7I
  336. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_NAND);
  337. #endif
  338. }
  339. static void nand_clock_setup(void)
  340. {
  341. struct sunxi_ccm_reg *const ccm =
  342. (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  343. setbits_le32(&ccm->ahb_gate0, (CLK_GATE_OPEN << AHB_GATE_OFFSET_NAND0));
  344. #if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I || \
  345. defined CONFIG_MACH_SUN9I || defined CONFIG_MACH_SUN50I
  346. setbits_le32(&ccm->ahb_reset0_cfg, (1 << AHB_GATE_OFFSET_NAND0));
  347. #endif
  348. setbits_le32(&ccm->nand0_clk_cfg, CCM_NAND_CTRL_ENABLE | AHB_DIV_1);
  349. }
  350. void board_nand_init(void)
  351. {
  352. nand_pinmux_setup();
  353. nand_clock_setup();
  354. #ifndef CONFIG_SPL_BUILD
  355. sunxi_nand_init();
  356. #endif
  357. }
  358. #endif
  359. #ifdef CONFIG_MMC
  360. static void mmc_pinmux_setup(int sdc)
  361. {
  362. unsigned int pin;
  363. __maybe_unused int pins;
  364. switch (sdc) {
  365. case 0:
  366. /* SDC0: PF0-PF5 */
  367. for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) {
  368. sunxi_gpio_set_cfgpin(pin, SUNXI_GPF_SDC0);
  369. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  370. sunxi_gpio_set_drv(pin, 2);
  371. }
  372. break;
  373. case 1:
  374. pins = sunxi_name_to_gpio_bank(CONFIG_MMC1_PINS);
  375. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  376. defined(CONFIG_MACH_SUN8I_R40)
  377. if (pins == SUNXI_GPIO_H) {
  378. /* SDC1: PH22-PH-27 */
  379. for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) {
  380. sunxi_gpio_set_cfgpin(pin, SUN4I_GPH_SDC1);
  381. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  382. sunxi_gpio_set_drv(pin, 2);
  383. }
  384. } else {
  385. /* SDC1: PG0-PG5 */
  386. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  387. sunxi_gpio_set_cfgpin(pin, SUN4I_GPG_SDC1);
  388. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  389. sunxi_gpio_set_drv(pin, 2);
  390. }
  391. }
  392. #elif defined(CONFIG_MACH_SUN5I)
  393. /* SDC1: PG3-PG8 */
  394. for (pin = SUNXI_GPG(3); pin <= SUNXI_GPG(8); pin++) {
  395. sunxi_gpio_set_cfgpin(pin, SUN5I_GPG_SDC1);
  396. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  397. sunxi_gpio_set_drv(pin, 2);
  398. }
  399. #elif defined(CONFIG_MACH_SUN6I)
  400. /* SDC1: PG0-PG5 */
  401. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  402. sunxi_gpio_set_cfgpin(pin, SUN6I_GPG_SDC1);
  403. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  404. sunxi_gpio_set_drv(pin, 2);
  405. }
  406. #elif defined(CONFIG_MACH_SUN8I)
  407. if (pins == SUNXI_GPIO_D) {
  408. /* SDC1: PD2-PD7 */
  409. for (pin = SUNXI_GPD(2); pin <= SUNXI_GPD(7); pin++) {
  410. sunxi_gpio_set_cfgpin(pin, SUN8I_GPD_SDC1);
  411. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  412. sunxi_gpio_set_drv(pin, 2);
  413. }
  414. } else {
  415. /* SDC1: PG0-PG5 */
  416. for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) {
  417. sunxi_gpio_set_cfgpin(pin, SUN8I_GPG_SDC1);
  418. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  419. sunxi_gpio_set_drv(pin, 2);
  420. }
  421. }
  422. #endif
  423. break;
  424. case 2:
  425. pins = sunxi_name_to_gpio_bank(CONFIG_MMC2_PINS);
  426. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I)
  427. /* SDC2: PC6-PC11 */
  428. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) {
  429. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  430. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  431. sunxi_gpio_set_drv(pin, 2);
  432. }
  433. #elif defined(CONFIG_MACH_SUN5I)
  434. if (pins == SUNXI_GPIO_E) {
  435. /* SDC2: PE4-PE9 */
  436. for (pin = SUNXI_GPE(4); pin <= SUNXI_GPD(9); pin++) {
  437. sunxi_gpio_set_cfgpin(pin, SUN5I_GPE_SDC2);
  438. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  439. sunxi_gpio_set_drv(pin, 2);
  440. }
  441. } else {
  442. /* SDC2: PC6-PC15 */
  443. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  444. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  445. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  446. sunxi_gpio_set_drv(pin, 2);
  447. }
  448. }
  449. #elif defined(CONFIG_MACH_SUN6I)
  450. if (pins == SUNXI_GPIO_A) {
  451. /* SDC2: PA9-PA14 */
  452. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  453. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC2);
  454. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  455. sunxi_gpio_set_drv(pin, 2);
  456. }
  457. } else {
  458. /* SDC2: PC6-PC15, PC24 */
  459. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  460. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  461. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  462. sunxi_gpio_set_drv(pin, 2);
  463. }
  464. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  465. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  466. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  467. }
  468. #elif defined(CONFIG_MACH_SUN8I_R40)
  469. /* SDC2: PC6-PC15, PC24 */
  470. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  471. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  472. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  473. sunxi_gpio_set_drv(pin, 2);
  474. }
  475. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUNXI_GPC_SDC2);
  476. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  477. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  478. #elif defined(CONFIG_MACH_SUN8I) || defined(CONFIG_MACH_SUN50I)
  479. /* SDC2: PC5-PC6, PC8-PC16 */
  480. for (pin = SUNXI_GPC(5); pin <= SUNXI_GPC(6); pin++) {
  481. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  482. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  483. sunxi_gpio_set_drv(pin, 2);
  484. }
  485. for (pin = SUNXI_GPC(8); pin <= SUNXI_GPC(16); pin++) {
  486. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  487. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  488. sunxi_gpio_set_drv(pin, 2);
  489. }
  490. #elif defined(CONFIG_MACH_SUN50I_H6)
  491. /* SDC2: PC4-PC14 */
  492. for (pin = SUNXI_GPC(4); pin <= SUNXI_GPC(14); pin++) {
  493. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  494. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  495. sunxi_gpio_set_drv(pin, 2);
  496. }
  497. #elif defined(CONFIG_MACH_SUN9I)
  498. /* SDC2: PC6-PC16 */
  499. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(16); pin++) {
  500. sunxi_gpio_set_cfgpin(pin, SUNXI_GPC_SDC2);
  501. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  502. sunxi_gpio_set_drv(pin, 2);
  503. }
  504. #endif
  505. break;
  506. case 3:
  507. pins = sunxi_name_to_gpio_bank(CONFIG_MMC3_PINS);
  508. #if defined(CONFIG_MACH_SUN4I) || defined(CONFIG_MACH_SUN7I) || \
  509. defined(CONFIG_MACH_SUN8I_R40)
  510. /* SDC3: PI4-PI9 */
  511. for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) {
  512. sunxi_gpio_set_cfgpin(pin, SUNXI_GPI_SDC3);
  513. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  514. sunxi_gpio_set_drv(pin, 2);
  515. }
  516. #elif defined(CONFIG_MACH_SUN6I)
  517. if (pins == SUNXI_GPIO_A) {
  518. /* SDC3: PA9-PA14 */
  519. for (pin = SUNXI_GPA(9); pin <= SUNXI_GPA(14); pin++) {
  520. sunxi_gpio_set_cfgpin(pin, SUN6I_GPA_SDC3);
  521. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  522. sunxi_gpio_set_drv(pin, 2);
  523. }
  524. } else {
  525. /* SDC3: PC6-PC15, PC24 */
  526. for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(15); pin++) {
  527. sunxi_gpio_set_cfgpin(pin, SUN6I_GPC_SDC3);
  528. sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP);
  529. sunxi_gpio_set_drv(pin, 2);
  530. }
  531. sunxi_gpio_set_cfgpin(SUNXI_GPC(24), SUN6I_GPC_SDC3);
  532. sunxi_gpio_set_pull(SUNXI_GPC(24), SUNXI_GPIO_PULL_UP);
  533. sunxi_gpio_set_drv(SUNXI_GPC(24), 2);
  534. }
  535. #endif
  536. break;
  537. default:
  538. printf("sunxi: invalid MMC slot %d for pinmux setup\n", sdc);
  539. break;
  540. }
  541. }
  542. int board_mmc_init(struct bd_info *bis)
  543. {
  544. __maybe_unused struct mmc *mmc0, *mmc1;
  545. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT);
  546. mmc0 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT);
  547. if (!mmc0)
  548. return -1;
  549. #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1
  550. mmc_pinmux_setup(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  551. mmc1 = sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA);
  552. if (!mmc1)
  553. return -1;
  554. #endif
  555. return 0;
  556. }
  557. #endif
  558. #ifdef CONFIG_SPL_BUILD
  559. static void sunxi_spl_store_dram_size(phys_addr_t dram_size)
  560. {
  561. struct boot_file_head *spl = get_spl_header(SPL_DT_HEADER_VERSION);
  562. if (spl == INVALID_SPL_HEADER)
  563. return;
  564. /* Promote the header version for U-Boot proper, if needed. */
  565. if (spl->spl_signature[3] < SPL_DRAM_HEADER_VERSION)
  566. spl->spl_signature[3] = SPL_DRAM_HEADER_VERSION;
  567. spl->dram_size = dram_size >> 20;
  568. }
  569. void sunxi_board_init(void)
  570. {
  571. int power_failed = 0;
  572. #ifdef CONFIG_SY8106A_POWER
  573. power_failed = sy8106a_set_vout1(CONFIG_SY8106A_VOUT1_VOLT);
  574. #endif
  575. #if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || \
  576. defined CONFIG_AXP221_POWER || defined CONFIG_AXP305_POWER || \
  577. defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
  578. power_failed = axp_init();
  579. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  580. defined CONFIG_AXP818_POWER
  581. power_failed |= axp_set_dcdc1(CONFIG_AXP_DCDC1_VOLT);
  582. #endif
  583. #if !defined(CONFIG_AXP305_POWER)
  584. power_failed |= axp_set_dcdc2(CONFIG_AXP_DCDC2_VOLT);
  585. power_failed |= axp_set_dcdc3(CONFIG_AXP_DCDC3_VOLT);
  586. #endif
  587. #if !defined(CONFIG_AXP209_POWER) && !defined(CONFIG_AXP818_POWER)
  588. power_failed |= axp_set_dcdc4(CONFIG_AXP_DCDC4_VOLT);
  589. #endif
  590. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  591. defined CONFIG_AXP818_POWER
  592. power_failed |= axp_set_dcdc5(CONFIG_AXP_DCDC5_VOLT);
  593. #endif
  594. #if defined CONFIG_AXP221_POWER || defined CONFIG_AXP809_POWER || \
  595. defined CONFIG_AXP818_POWER
  596. power_failed |= axp_set_aldo1(CONFIG_AXP_ALDO1_VOLT);
  597. #endif
  598. #if !defined(CONFIG_AXP305_POWER)
  599. power_failed |= axp_set_aldo2(CONFIG_AXP_ALDO2_VOLT);
  600. #endif
  601. #if !defined(CONFIG_AXP152_POWER) && !defined(CONFIG_AXP305_POWER)
  602. power_failed |= axp_set_aldo3(CONFIG_AXP_ALDO3_VOLT);
  603. #endif
  604. #ifdef CONFIG_AXP209_POWER
  605. power_failed |= axp_set_aldo4(CONFIG_AXP_ALDO4_VOLT);
  606. #endif
  607. #if defined(CONFIG_AXP221_POWER) || defined(CONFIG_AXP809_POWER) || \
  608. defined(CONFIG_AXP818_POWER)
  609. power_failed |= axp_set_dldo(1, CONFIG_AXP_DLDO1_VOLT);
  610. power_failed |= axp_set_dldo(2, CONFIG_AXP_DLDO2_VOLT);
  611. #if !defined CONFIG_AXP809_POWER
  612. power_failed |= axp_set_dldo(3, CONFIG_AXP_DLDO3_VOLT);
  613. power_failed |= axp_set_dldo(4, CONFIG_AXP_DLDO4_VOLT);
  614. #endif
  615. power_failed |= axp_set_eldo(1, CONFIG_AXP_ELDO1_VOLT);
  616. power_failed |= axp_set_eldo(2, CONFIG_AXP_ELDO2_VOLT);
  617. power_failed |= axp_set_eldo(3, CONFIG_AXP_ELDO3_VOLT);
  618. #endif
  619. #ifdef CONFIG_AXP818_POWER
  620. power_failed |= axp_set_fldo(1, CONFIG_AXP_FLDO1_VOLT);
  621. power_failed |= axp_set_fldo(2, CONFIG_AXP_FLDO2_VOLT);
  622. power_failed |= axp_set_fldo(3, CONFIG_AXP_FLDO3_VOLT);
  623. #endif
  624. #if defined CONFIG_AXP809_POWER || defined CONFIG_AXP818_POWER
  625. power_failed |= axp_set_sw(IS_ENABLED(CONFIG_AXP_SW_ON));
  626. #endif
  627. #endif
  628. printf("DRAM:");
  629. gd->ram_size = sunxi_dram_init();
  630. printf(" %d MiB\n", (int)(gd->ram_size >> 20));
  631. if (!gd->ram_size)
  632. hang();
  633. sunxi_spl_store_dram_size(gd->ram_size);
  634. /*
  635. * Only clock up the CPU to full speed if we are reasonably
  636. * assured it's being powered with suitable core voltage
  637. */
  638. if (!power_failed)
  639. clock_set_pll1(CONFIG_SYS_CLK_FREQ);
  640. else
  641. printf("Failed to set core voltage! Can't set CPU frequency\n");
  642. }
  643. #endif
  644. #ifdef CONFIG_USB_GADGET
  645. int g_dnl_board_usb_cable_connected(void)
  646. {
  647. struct udevice *dev;
  648. struct phy phy;
  649. int ret;
  650. ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);
  651. if (ret) {
  652. pr_err("%s: Cannot find USB device\n", __func__);
  653. return ret;
  654. }
  655. ret = generic_phy_get_by_name(dev, "usb", &phy);
  656. if (ret) {
  657. pr_err("failed to get %s USB PHY\n", dev->name);
  658. return ret;
  659. }
  660. ret = generic_phy_init(&phy);
  661. if (ret) {
  662. pr_debug("failed to init %s USB PHY\n", dev->name);
  663. return ret;
  664. }
  665. ret = sun4i_usb_phy_vbus_detect(&phy);
  666. if (ret == 1) {
  667. pr_err("A charger is plugged into the OTG\n");
  668. return -ENODEV;
  669. }
  670. return ret;
  671. }
  672. #endif
  673. #ifdef CONFIG_SERIAL_TAG
  674. void get_board_serial(struct tag_serialnr *serialnr)
  675. {
  676. char *serial_string;
  677. unsigned long long serial;
  678. serial_string = env_get("serial#");
  679. if (serial_string) {
  680. serial = simple_strtoull(serial_string, NULL, 16);
  681. serialnr->high = (unsigned int) (serial >> 32);
  682. serialnr->low = (unsigned int) (serial & 0xffffffff);
  683. } else {
  684. serialnr->high = 0;
  685. serialnr->low = 0;
  686. }
  687. }
  688. #endif
  689. /*
  690. * Check the SPL header for the "sunxi" variant. If found: parse values
  691. * that might have been passed by the loader ("fel" utility), and update
  692. * the environment accordingly.
  693. */
  694. static void parse_spl_header(const uint32_t spl_addr)
  695. {
  696. struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
  697. if (spl == INVALID_SPL_HEADER)
  698. return;
  699. if (!spl->fel_script_address)
  700. return;
  701. if (spl->fel_uEnv_length != 0) {
  702. /*
  703. * data is expected in uEnv.txt compatible format, so "env
  704. * import -t" the string(s) at fel_script_address right away.
  705. */
  706. himport_r(&env_htab, (char *)(uintptr_t)spl->fel_script_address,
  707. spl->fel_uEnv_length, '\n', H_NOCLEAR, 0, 0, NULL);
  708. return;
  709. }
  710. /* otherwise assume .scr format (mkimage-type script) */
  711. env_set_hex("fel_scriptaddr", spl->fel_script_address);
  712. }
  713. static bool get_unique_sid(unsigned int *sid)
  714. {
  715. if (sunxi_get_sid(sid) != 0)
  716. return false;
  717. if (!sid[0])
  718. return false;
  719. /*
  720. * The single words 1 - 3 of the SID have quite a few bits
  721. * which are the same on many models, so we take a crc32
  722. * of all 3 words, to get a more unique value.
  723. *
  724. * Note we only do this on newer SoCs as we cannot change
  725. * the algorithm on older SoCs since those have been using
  726. * fixed mac-addresses based on only using word 3 for a
  727. * long time and changing a fixed mac-address with an
  728. * u-boot update is not good.
  729. */
  730. #if !defined(CONFIG_MACH_SUN4I) && !defined(CONFIG_MACH_SUN5I) && \
  731. !defined(CONFIG_MACH_SUN6I) && !defined(CONFIG_MACH_SUN7I) && \
  732. !defined(CONFIG_MACH_SUN8I_A23) && !defined(CONFIG_MACH_SUN8I_A33)
  733. sid[3] = crc32(0, (unsigned char *)&sid[1], 12);
  734. #endif
  735. /* Ensure the NIC specific bytes of the mac are not all 0 */
  736. if ((sid[3] & 0xffffff) == 0)
  737. sid[3] |= 0x800000;
  738. return true;
  739. }
  740. /*
  741. * Note this function gets called multiple times.
  742. * It must not make any changes to env variables which already exist.
  743. */
  744. static void setup_environment(const void *fdt)
  745. {
  746. char serial_string[17] = { 0 };
  747. unsigned int sid[4];
  748. uint8_t mac_addr[6];
  749. char ethaddr[16];
  750. int i;
  751. if (!get_unique_sid(sid))
  752. return;
  753. for (i = 0; i < 4; i++) {
  754. sprintf(ethaddr, "ethernet%d", i);
  755. if (!fdt_get_alias(fdt, ethaddr))
  756. continue;
  757. if (i == 0)
  758. strcpy(ethaddr, "ethaddr");
  759. else
  760. sprintf(ethaddr, "eth%daddr", i);
  761. if (env_get(ethaddr))
  762. continue;
  763. /* Non OUI / registered MAC address */
  764. mac_addr[0] = (i << 4) | 0x02;
  765. mac_addr[1] = (sid[0] >> 0) & 0xff;
  766. mac_addr[2] = (sid[3] >> 24) & 0xff;
  767. mac_addr[3] = (sid[3] >> 16) & 0xff;
  768. mac_addr[4] = (sid[3] >> 8) & 0xff;
  769. mac_addr[5] = (sid[3] >> 0) & 0xff;
  770. eth_env_set_enetaddr(ethaddr, mac_addr);
  771. }
  772. if (!env_get("serial#")) {
  773. snprintf(serial_string, sizeof(serial_string),
  774. "%08x%08x", sid[0], sid[3]);
  775. env_set("serial#", serial_string);
  776. }
  777. }
  778. int misc_init_r(void)
  779. {
  780. const char *spl_dt_name;
  781. uint boot;
  782. env_set("fel_booted", NULL);
  783. env_set("fel_scriptaddr", NULL);
  784. env_set("mmc_bootdev", NULL);
  785. boot = sunxi_get_boot_device();
  786. /* determine if we are running in FEL mode */
  787. if (boot == BOOT_DEVICE_BOARD) {
  788. env_set("fel_booted", "1");
  789. parse_spl_header(SPL_ADDR);
  790. /* or if we booted from MMC, and which one */
  791. } else if (boot == BOOT_DEVICE_MMC1) {
  792. env_set("mmc_bootdev", "0");
  793. } else if (boot == BOOT_DEVICE_MMC2) {
  794. env_set("mmc_bootdev", "1");
  795. }
  796. /* Set fdtfile to match the FIT configuration chosen in SPL. */
  797. spl_dt_name = get_spl_dt_name();
  798. if (spl_dt_name) {
  799. char *prefix = IS_ENABLED(CONFIG_ARM64) ? "allwinner/" : "";
  800. char str[64];
  801. snprintf(str, sizeof(str), "%s%s.dtb", prefix, spl_dt_name);
  802. env_set("fdtfile", str);
  803. }
  804. setup_environment(gd->fdt_blob);
  805. return 0;
  806. }
  807. int board_late_init(void)
  808. {
  809. #ifdef CONFIG_USB_ETHER
  810. usb_ether_init();
  811. #endif
  812. return 0;
  813. }
  814. static void bluetooth_dt_fixup(void *blob)
  815. {
  816. /* Some devices ship with a Bluetooth controller default address.
  817. * Set a valid address through the device tree.
  818. */
  819. uchar tmp[ETH_ALEN], bdaddr[ETH_ALEN];
  820. unsigned int sid[4];
  821. int i;
  822. if (!CONFIG_BLUETOOTH_DT_DEVICE_FIXUP[0])
  823. return;
  824. if (eth_env_get_enetaddr("bdaddr", tmp)) {
  825. /* Convert between the binary formats of the corresponding stacks */
  826. for (i = 0; i < ETH_ALEN; ++i)
  827. bdaddr[i] = tmp[ETH_ALEN - i - 1];
  828. } else {
  829. if (!get_unique_sid(sid))
  830. return;
  831. bdaddr[0] = ((sid[3] >> 0) & 0xff) ^ 1;
  832. bdaddr[1] = (sid[3] >> 8) & 0xff;
  833. bdaddr[2] = (sid[3] >> 16) & 0xff;
  834. bdaddr[3] = (sid[3] >> 24) & 0xff;
  835. bdaddr[4] = (sid[0] >> 0) & 0xff;
  836. bdaddr[5] = 0x02;
  837. }
  838. do_fixup_by_compat(blob, CONFIG_BLUETOOTH_DT_DEVICE_FIXUP,
  839. "local-bd-address", bdaddr, ETH_ALEN, 1);
  840. }
  841. int ft_board_setup(void *blob, struct bd_info *bd)
  842. {
  843. int __maybe_unused r;
  844. /*
  845. * Call setup_environment again in case the boot fdt has
  846. * ethernet aliases the u-boot copy does not have.
  847. */
  848. setup_environment(blob);
  849. bluetooth_dt_fixup(blob);
  850. #ifdef CONFIG_VIDEO_DT_SIMPLEFB
  851. r = sunxi_simplefb_setup(blob);
  852. if (r)
  853. return r;
  854. #endif
  855. return 0;
  856. }
  857. #ifdef CONFIG_SPL_LOAD_FIT
  858. static void set_spl_dt_name(const char *name)
  859. {
  860. struct boot_file_head *spl = get_spl_header(SPL_ENV_HEADER_VERSION);
  861. if (spl == INVALID_SPL_HEADER)
  862. return;
  863. /* Promote the header version for U-Boot proper, if needed. */
  864. if (spl->spl_signature[3] < SPL_DT_HEADER_VERSION)
  865. spl->spl_signature[3] = SPL_DT_HEADER_VERSION;
  866. strcpy((char *)&spl->string_pool, name);
  867. spl->dt_name_offset = offsetof(struct boot_file_head, string_pool);
  868. }
  869. int board_fit_config_name_match(const char *name)
  870. {
  871. const char *best_dt_name = get_spl_dt_name();
  872. int ret;
  873. #ifdef CONFIG_DEFAULT_DEVICE_TREE
  874. if (best_dt_name == NULL)
  875. best_dt_name = CONFIG_DEFAULT_DEVICE_TREE;
  876. #endif
  877. if (best_dt_name == NULL) {
  878. /* No DT name was provided, so accept the first config. */
  879. return 0;
  880. }
  881. #ifdef CONFIG_PINE64_DT_SELECTION
  882. if (strstr(best_dt_name, "-pine64-plus")) {
  883. /* Differentiate the Pine A64 boards by their DRAM size. */
  884. if ((gd->ram_size == 512 * 1024 * 1024))
  885. best_dt_name = "sun50i-a64-pine64";
  886. }
  887. #endif
  888. #ifdef CONFIG_PINEPHONE_DT_SELECTION
  889. if (strstr(best_dt_name, "-pinephone")) {
  890. /* Differentiate the PinePhone revisions by GPIO inputs. */
  891. prcm_apb0_enable(PRCM_APB0_GATE_PIO);
  892. sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_UP);
  893. sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_INPUT);
  894. udelay(100);
  895. /* PL6 is pulled low by the modem on v1.2. */
  896. if (gpio_get_value(SUNXI_GPL(6)) == 0)
  897. best_dt_name = "sun50i-a64-pinephone-1.2";
  898. else
  899. best_dt_name = "sun50i-a64-pinephone-1.1";
  900. sunxi_gpio_set_cfgpin(SUNXI_GPL(6), SUNXI_GPIO_DISABLE);
  901. sunxi_gpio_set_pull(SUNXI_GPL(6), SUNXI_GPIO_PULL_DISABLE);
  902. prcm_apb0_disable(PRCM_APB0_GATE_PIO);
  903. }
  904. #endif
  905. ret = strcmp(name, best_dt_name);
  906. /*
  907. * If one of the FIT configurations matches the most accurate DT name,
  908. * update the SPL header to provide that DT name to U-Boot proper.
  909. */
  910. if (ret == 0)
  911. set_spl_dt_name(best_dt_name);
  912. return ret;
  913. }
  914. #endif