sh7753evb.c 8.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <init.h>
  8. #include <malloc.h>
  9. #include <asm/processor.h>
  10. #include <asm/io.h>
  11. #include <asm/mmc.h>
  12. #include <spi.h>
  13. #include <spi_flash.h>
  14. int checkboard(void)
  15. {
  16. puts("BOARD: SH7753 EVB\n");
  17. return 0;
  18. }
  19. static void init_gpio(void)
  20. {
  21. struct gpio_regs *gpio = GPIO_BASE;
  22. struct sermux_regs *sermux = SERMUX_BASE;
  23. /* GPIO */
  24. writew(0x0000, &gpio->pacr); /* GETHER */
  25. writew(0x0001, &gpio->pbcr); /* INTC */
  26. writew(0x0000, &gpio->pccr); /* PWMU, INTC */
  27. writew(0x0000, &gpio->pdcr); /* SPI0 */
  28. writew(0xeaff, &gpio->pecr); /* GPIO */
  29. writew(0x0000, &gpio->pfcr); /* WDT */
  30. writew(0x0004, &gpio->pgcr); /* SPI0, GETHER MDIO gate(PTG1) */
  31. writew(0x0000, &gpio->phcr); /* SPI1 */
  32. writew(0x0000, &gpio->picr); /* SDHI */
  33. writew(0x0000, &gpio->pjcr); /* SCIF4 */
  34. writew(0x0003, &gpio->pkcr); /* SerMux */
  35. writew(0x0000, &gpio->plcr); /* SerMux */
  36. writew(0x0000, &gpio->pmcr); /* RIIC */
  37. writew(0x0000, &gpio->pncr); /* USB, SGPIO */
  38. writew(0x0000, &gpio->pocr); /* SGPIO */
  39. writew(0xd555, &gpio->pqcr); /* GPIO */
  40. writew(0x0000, &gpio->prcr); /* RIIC */
  41. writew(0x0000, &gpio->pscr); /* RIIC */
  42. writew(0x0000, &gpio->ptcr); /* STATUS */
  43. writeb(0x00, &gpio->pudr);
  44. writew(0x5555, &gpio->pucr); /* Debug LED */
  45. writew(0x0000, &gpio->pvcr); /* RSPI */
  46. writew(0x0000, &gpio->pwcr); /* EVC */
  47. writew(0x0000, &gpio->pxcr); /* LBSC */
  48. writew(0x0000, &gpio->pycr); /* LBSC */
  49. writew(0x0000, &gpio->pzcr); /* eMMC */
  50. writew(0xfe00, &gpio->psel0);
  51. writew(0x0000, &gpio->psel1);
  52. writew(0x3000, &gpio->psel2);
  53. writew(0xff00, &gpio->psel3);
  54. writew(0x771f, &gpio->psel4);
  55. writew(0x0ffc, &gpio->psel5);
  56. writew(0x00ff, &gpio->psel6);
  57. writew(0xfc00, &gpio->psel7);
  58. writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
  59. }
  60. static void init_usb_phy(void)
  61. {
  62. struct usb_common_regs *common0 = USB0_COMMON_BASE;
  63. struct usb_common_regs *common1 = USB1_COMMON_BASE;
  64. struct usb0_phy_regs *phy = USB0_PHY_BASE;
  65. struct usb1_port_regs *port = USB1_PORT_BASE;
  66. struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  67. writew(0x0100, &phy->reset); /* set reset */
  68. /* port0 = USB0, port1 = USB1 */
  69. writew(0x0002, &phy->portsel);
  70. writel(0x0001, &port->port1sel); /* port1 = Host */
  71. writew(0x0111, &phy->reset); /* clear reset */
  72. writew(0x4000, &common0->suspmode);
  73. writew(0x4000, &common1->suspmode);
  74. #if defined(__LITTLE_ENDIAN)
  75. writel(0x00000000, &align->ehcidatac);
  76. writel(0x00000000, &align->ohcidatac);
  77. #endif
  78. }
  79. static void init_gether_mdio(void)
  80. {
  81. struct gpio_regs *gpio = GPIO_BASE;
  82. writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  83. writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  84. }
  85. static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  86. {
  87. struct ether_mac_regs *ether;
  88. unsigned char mac[6];
  89. unsigned long val;
  90. string_to_enetaddr(mac_string, mac);
  91. if (!channel)
  92. ether = GETHER0_MAC_BASE;
  93. else
  94. ether = GETHER1_MAC_BASE;
  95. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  96. writel(val, &ether->mahr);
  97. val = (mac[4] << 8) | mac[5];
  98. writel(val, &ether->malr);
  99. }
  100. #if defined(CONFIG_SH_32BIT)
  101. /*****************************************************************
  102. * This PMB must be set on this timing. The lowlevel_init is run on
  103. * Area 0(phys 0x00000000), so we have to map it.
  104. *
  105. * The new PMB table is following:
  106. * ent virt phys v sz c wt
  107. * 0 0xa0000000 0x40000000 1 128M 0 1
  108. * 1 0xa8000000 0x48000000 1 128M 0 1
  109. * 2 0xb0000000 0x50000000 1 128M 0 1
  110. * 3 0xb8000000 0x58000000 1 128M 0 1
  111. * 4 0x80000000 0x40000000 1 128M 1 1
  112. * 5 0x88000000 0x48000000 1 128M 1 1
  113. * 6 0x90000000 0x50000000 1 128M 1 1
  114. * 7 0x98000000 0x58000000 1 128M 1 1
  115. */
  116. static void set_pmb_on_board_init(void)
  117. {
  118. struct mmu_regs *mmu = MMU_BASE;
  119. /* clear ITLB */
  120. writel(0x00000004, &mmu->mmucr);
  121. /* delete PMB for SPIBOOT */
  122. writel(0, PMB_ADDR_BASE(0));
  123. writel(0, PMB_DATA_BASE(0));
  124. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  125. /* ppn ub v s1 s0 c wt */
  126. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  127. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  128. writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  129. writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  130. writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  131. writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  132. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  133. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  134. writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  135. writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  136. writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  137. writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  138. }
  139. #endif
  140. int board_init(void)
  141. {
  142. struct gether_control_regs *gether = GETHER_CONTROL_BASE;
  143. init_gpio();
  144. #if defined(CONFIG_SH_32BIT)
  145. set_pmb_on_board_init();
  146. #endif
  147. /* Sets TXnDLY to B'010 */
  148. writel(0x00000202, &gether->gbecont);
  149. init_usb_phy();
  150. init_gether_mdio();
  151. return 0;
  152. }
  153. int board_mmc_init(bd_t *bis)
  154. {
  155. struct gpio_regs *gpio = GPIO_BASE;
  156. writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
  157. writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
  158. udelay(1);
  159. writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
  160. udelay(200);
  161. return mmcif_mmc_init();
  162. }
  163. static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  164. {
  165. #ifdef CONFIG_DEPRECATED
  166. struct spi_flash *spi;
  167. int ret;
  168. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  169. if (spi == NULL) {
  170. printf("%s: spi_flash probe failed.\n", __func__);
  171. return 1;
  172. }
  173. ret = spi_flash_read(spi, SH7753EVB_ETHERNET_MAC_BASE, size, buf);
  174. if (ret) {
  175. printf("%s: spi_flash read failed.\n", __func__);
  176. spi_flash_free(spi);
  177. return 1;
  178. }
  179. spi_flash_free(spi);
  180. #endif
  181. return 0;
  182. }
  183. static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  184. {
  185. memcpy(mac_string, &buf[channel * (SH7753EVB_ETHERNET_MAC_SIZE + 1)],
  186. SH7753EVB_ETHERNET_MAC_SIZE);
  187. mac_string[SH7753EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  188. return 0;
  189. }
  190. static void init_ethernet_mac(void)
  191. {
  192. char mac_string[64];
  193. char env_string[64];
  194. int i;
  195. unsigned char *buf;
  196. buf = malloc(256);
  197. if (!buf) {
  198. printf("%s: malloc failed.\n", __func__);
  199. return;
  200. }
  201. get_sh_eth_mac_raw(buf, 256);
  202. /* Gigabit Ethernet */
  203. for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
  204. get_sh_eth_mac(i, mac_string, buf);
  205. if (i == 0)
  206. env_set("ethaddr", mac_string);
  207. else {
  208. sprintf(env_string, "eth%daddr", i);
  209. env_set(env_string, mac_string);
  210. }
  211. set_mac_to_sh_giga_eth_register(i, mac_string);
  212. }
  213. free(buf);
  214. }
  215. int board_late_init(void)
  216. {
  217. init_ethernet_mac();
  218. return 0;
  219. }
  220. #ifdef CONFIG_DEPRECATED
  221. int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  222. {
  223. int i, ret;
  224. char mac_string[256];
  225. struct spi_flash *spi;
  226. unsigned char *buf;
  227. if (argc != 3) {
  228. buf = malloc(256);
  229. if (!buf) {
  230. printf("%s: malloc failed.\n", __func__);
  231. return 1;
  232. }
  233. get_sh_eth_mac_raw(buf, 256);
  234. /* print current MAC address */
  235. for (i = 0; i < SH7753EVB_ETHERNET_NUM_CH; i++) {
  236. get_sh_eth_mac(i, mac_string, buf);
  237. printf("GETHERC ch%d = %s\n", i, mac_string);
  238. }
  239. free(buf);
  240. return 0;
  241. }
  242. /* new setting */
  243. memset(mac_string, 0xff, sizeof(mac_string));
  244. sprintf(mac_string, "%s\t%s",
  245. argv[1], argv[2]);
  246. /* write MAC data to SPI rom */
  247. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  248. if (!spi) {
  249. printf("%s: spi_flash probe failed.\n", __func__);
  250. return 1;
  251. }
  252. ret = spi_flash_erase(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
  253. SH7753EVB_SPI_SECTOR_SIZE);
  254. if (ret) {
  255. printf("%s: spi_flash erase failed.\n", __func__);
  256. return 1;
  257. }
  258. ret = spi_flash_write(spi, SH7753EVB_ETHERNET_MAC_BASE_SPI,
  259. sizeof(mac_string), mac_string);
  260. if (ret) {
  261. printf("%s: spi_flash write failed.\n", __func__);
  262. spi_flash_free(spi);
  263. return 1;
  264. }
  265. spi_flash_free(spi);
  266. puts("The writing of the MAC address to SPI ROM was completed.\n");
  267. return 0;
  268. }
  269. U_BOOT_CMD(
  270. write_mac, 3, 1, do_write_mac,
  271. "write MAC address for GETHERC",
  272. "[GETHERC ch0] [GETHERC ch1]\n"
  273. );
  274. #endif