sh7752evb.c 7.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Renesas Solutions Corp.
  4. */
  5. #include <common.h>
  6. #include <env.h>
  7. #include <init.h>
  8. #include <malloc.h>
  9. #include <asm/processor.h>
  10. #include <asm/io.h>
  11. #include <asm/mmc.h>
  12. #include <spi.h>
  13. #include <spi_flash.h>
  14. int checkboard(void)
  15. {
  16. puts("BOARD: SH7752 evaluation board (R0P7752C00000RZ)\n");
  17. return 0;
  18. }
  19. static void init_gpio(void)
  20. {
  21. struct gpio_regs *gpio = GPIO_BASE;
  22. struct sermux_regs *sermux = SERMUX_BASE;
  23. /* GPIO */
  24. writew(0x0000, &gpio->pacr); /* GETHER */
  25. writew(0x0001, &gpio->pbcr); /* INTC */
  26. writew(0x0000, &gpio->pccr); /* PWMU, INTC */
  27. writew(0xeaff, &gpio->pecr); /* GPIO */
  28. writew(0x0000, &gpio->pfcr); /* WDT */
  29. writew(0x0000, &gpio->phcr); /* SPI1 */
  30. writew(0x0000, &gpio->picr); /* SDHI */
  31. writew(0x0003, &gpio->pkcr); /* SerMux */
  32. writew(0x0000, &gpio->plcr); /* SerMux */
  33. writew(0x0000, &gpio->pmcr); /* RIIC */
  34. writew(0x0000, &gpio->pncr); /* USB, SGPIO */
  35. writew(0x0000, &gpio->pocr); /* SGPIO */
  36. writew(0xd555, &gpio->pqcr); /* GPIO */
  37. writew(0x0000, &gpio->prcr); /* RIIC */
  38. writew(0x0000, &gpio->pscr); /* RIIC */
  39. writeb(0x00, &gpio->pudr);
  40. writew(0x5555, &gpio->pucr); /* Debug LED */
  41. writew(0x0000, &gpio->pvcr); /* RSPI */
  42. writew(0x0000, &gpio->pwcr); /* EVC */
  43. writew(0x0000, &gpio->pxcr); /* LBSC */
  44. writew(0x0000, &gpio->pycr); /* LBSC */
  45. writew(0x0000, &gpio->pzcr); /* eMMC */
  46. writew(0xfe00, &gpio->psel0);
  47. writew(0xff00, &gpio->psel3);
  48. writew(0x771f, &gpio->psel4);
  49. writew(0x00ff, &gpio->psel6);
  50. writew(0xfc00, &gpio->psel7);
  51. writeb(0x10, &sermux->smr0); /* SMR0: SerMux mode 0 */
  52. }
  53. static void init_usb_phy(void)
  54. {
  55. struct usb_common_regs *common0 = USB0_COMMON_BASE;
  56. struct usb_common_regs *common1 = USB1_COMMON_BASE;
  57. struct usb0_phy_regs *phy = USB0_PHY_BASE;
  58. struct usb1_port_regs *port = USB1_PORT_BASE;
  59. struct usb1_alignment_regs *align = USB1_ALIGNMENT_BASE;
  60. writew(0x0100, &phy->reset); /* set reset */
  61. /* port0 = USB0, port1 = USB1 */
  62. writew(0x0002, &phy->portsel);
  63. writel(0x0001, &port->port1sel); /* port1 = Host */
  64. writew(0x0111, &phy->reset); /* clear reset */
  65. writew(0x4000, &common0->suspmode);
  66. writew(0x4000, &common1->suspmode);
  67. #if defined(__LITTLE_ENDIAN)
  68. writel(0x00000000, &align->ehcidatac);
  69. writel(0x00000000, &align->ohcidatac);
  70. #endif
  71. }
  72. static void init_gether_mdio(void)
  73. {
  74. struct gpio_regs *gpio = GPIO_BASE;
  75. writew(readw(&gpio->pgcr) | 0x0004, &gpio->pgcr);
  76. writeb(readb(&gpio->pgdr) | 0x02, &gpio->pgdr); /* Use ET0-MDIO */
  77. }
  78. static void set_mac_to_sh_giga_eth_register(int channel, char *mac_string)
  79. {
  80. struct ether_mac_regs *ether;
  81. unsigned char mac[6];
  82. unsigned long val;
  83. string_to_enetaddr(mac_string, mac);
  84. if (!channel)
  85. ether = GETHER0_MAC_BASE;
  86. else
  87. ether = GETHER1_MAC_BASE;
  88. val = (mac[0] << 24) | (mac[1] << 16) | (mac[2] << 8) | mac[3];
  89. writel(val, &ether->mahr);
  90. val = (mac[4] << 8) | mac[5];
  91. writel(val, &ether->malr);
  92. }
  93. /*****************************************************************
  94. * This PMB must be set on this timing. The lowlevel_init is run on
  95. * Area 0(phys 0x00000000), so we have to map it.
  96. *
  97. * The new PMB table is following:
  98. * ent virt phys v sz c wt
  99. * 0 0xa0000000 0x40000000 1 128M 0 1
  100. * 1 0xa8000000 0x48000000 1 128M 0 1
  101. * 2 0xb0000000 0x50000000 1 128M 0 1
  102. * 3 0xb8000000 0x58000000 1 128M 0 1
  103. * 4 0x80000000 0x40000000 1 128M 1 1
  104. * 5 0x88000000 0x48000000 1 128M 1 1
  105. * 6 0x90000000 0x50000000 1 128M 1 1
  106. * 7 0x98000000 0x58000000 1 128M 1 1
  107. */
  108. static void set_pmb_on_board_init(void)
  109. {
  110. struct mmu_regs *mmu = MMU_BASE;
  111. /* clear ITLB */
  112. writel(0x00000004, &mmu->mmucr);
  113. /* delete PMB for SPIBOOT */
  114. writel(0, PMB_ADDR_BASE(0));
  115. writel(0, PMB_DATA_BASE(0));
  116. /* add PMB for SDRAM(0x40000000 - 0x47ffffff) */
  117. /* ppn ub v s1 s0 c wt */
  118. writel(mk_pmb_addr_val(0xa0), PMB_ADDR_BASE(0));
  119. writel(mk_pmb_data_val(0x40, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(0));
  120. writel(mk_pmb_addr_val(0xb0), PMB_ADDR_BASE(2));
  121. writel(mk_pmb_data_val(0x50, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(2));
  122. writel(mk_pmb_addr_val(0xb8), PMB_ADDR_BASE(3));
  123. writel(mk_pmb_data_val(0x58, 1, 1, 1, 0, 0, 1), PMB_DATA_BASE(3));
  124. writel(mk_pmb_addr_val(0x80), PMB_ADDR_BASE(4));
  125. writel(mk_pmb_data_val(0x40, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(4));
  126. writel(mk_pmb_addr_val(0x90), PMB_ADDR_BASE(6));
  127. writel(mk_pmb_data_val(0x50, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(6));
  128. writel(mk_pmb_addr_val(0x98), PMB_ADDR_BASE(7));
  129. writel(mk_pmb_data_val(0x58, 0, 1, 1, 0, 1, 1), PMB_DATA_BASE(7));
  130. }
  131. int board_init(void)
  132. {
  133. init_gpio();
  134. set_pmb_on_board_init();
  135. init_usb_phy();
  136. init_gether_mdio();
  137. return 0;
  138. }
  139. int board_mmc_init(bd_t *bis)
  140. {
  141. struct gpio_regs *gpio = GPIO_BASE;
  142. writew(readw(&gpio->pgcr) | 0x0040, &gpio->pgcr);
  143. writeb(readb(&gpio->pgdr) & ~0x08, &gpio->pgdr); /* Reset */
  144. udelay(1);
  145. writeb(readb(&gpio->pgdr) | 0x08, &gpio->pgdr); /* Release reset */
  146. udelay(200);
  147. return mmcif_mmc_init();
  148. }
  149. static int get_sh_eth_mac_raw(unsigned char *buf, int size)
  150. {
  151. #ifdef CONFIG_DEPRECATED
  152. struct spi_flash *spi;
  153. int ret;
  154. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  155. if (spi == NULL) {
  156. printf("%s: spi_flash probe failed.\n", __func__);
  157. return 1;
  158. }
  159. ret = spi_flash_read(spi, SH7752EVB_ETHERNET_MAC_BASE, size, buf);
  160. if (ret) {
  161. printf("%s: spi_flash read failed.\n", __func__);
  162. spi_flash_free(spi);
  163. return 1;
  164. }
  165. spi_flash_free(spi);
  166. #endif
  167. return 0;
  168. }
  169. static int get_sh_eth_mac(int channel, char *mac_string, unsigned char *buf)
  170. {
  171. memcpy(mac_string, &buf[channel * (SH7752EVB_ETHERNET_MAC_SIZE + 1)],
  172. SH7752EVB_ETHERNET_MAC_SIZE);
  173. mac_string[SH7752EVB_ETHERNET_MAC_SIZE] = 0x00; /* terminate */
  174. return 0;
  175. }
  176. static void init_ethernet_mac(void)
  177. {
  178. char mac_string[64];
  179. char env_string[64];
  180. int i;
  181. unsigned char *buf;
  182. buf = malloc(256);
  183. if (!buf) {
  184. printf("%s: malloc failed.\n", __func__);
  185. return;
  186. }
  187. get_sh_eth_mac_raw(buf, 256);
  188. /* Gigabit Ethernet */
  189. for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
  190. get_sh_eth_mac(i, mac_string, buf);
  191. if (i == 0)
  192. env_set("ethaddr", mac_string);
  193. else {
  194. sprintf(env_string, "eth%daddr", i);
  195. env_set(env_string, mac_string);
  196. }
  197. set_mac_to_sh_giga_eth_register(i, mac_string);
  198. }
  199. free(buf);
  200. }
  201. int board_late_init(void)
  202. {
  203. init_ethernet_mac();
  204. return 0;
  205. }
  206. #ifdef CONFIG_DEPRECATED
  207. int do_write_mac(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  208. {
  209. int i, ret;
  210. char mac_string[256];
  211. struct spi_flash *spi;
  212. unsigned char *buf;
  213. if (argc != 3) {
  214. buf = malloc(256);
  215. if (!buf) {
  216. printf("%s: malloc failed.\n", __func__);
  217. return 1;
  218. }
  219. get_sh_eth_mac_raw(buf, 256);
  220. /* print current MAC address */
  221. for (i = 0; i < SH7752EVB_ETHERNET_NUM_CH; i++) {
  222. get_sh_eth_mac(i, mac_string, buf);
  223. printf("GETHERC ch%d = %s\n", i, mac_string);
  224. }
  225. free(buf);
  226. return 0;
  227. }
  228. /* new setting */
  229. memset(mac_string, 0xff, sizeof(mac_string));
  230. sprintf(mac_string, "%s\t%s",
  231. argv[1], argv[2]);
  232. /* write MAC data to SPI rom */
  233. spi = spi_flash_probe(0, 0, 1000000, SPI_MODE_3);
  234. if (!spi) {
  235. printf("%s: spi_flash probe failed.\n", __func__);
  236. return 1;
  237. }
  238. ret = spi_flash_erase(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
  239. SH7752EVB_SPI_SECTOR_SIZE);
  240. if (ret) {
  241. printf("%s: spi_flash erase failed.\n", __func__);
  242. return 1;
  243. }
  244. ret = spi_flash_write(spi, SH7752EVB_ETHERNET_MAC_BASE_SPI,
  245. sizeof(mac_string), mac_string);
  246. if (ret) {
  247. printf("%s: spi_flash write failed.\n", __func__);
  248. spi_flash_free(spi);
  249. return 1;
  250. }
  251. spi_flash_free(spi);
  252. puts("The writing of the MAC address to SPI ROM was completed.\n");
  253. return 0;
  254. }
  255. U_BOOT_CMD(
  256. write_mac, 3, 1, do_write_mac,
  257. "write MAC address for GETHERC",
  258. "[GETHERC ch0] [GETHERC ch1]\n"
  259. );
  260. #endif