stm32mp157a-dk1-u-boot.dtsi 3.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. */
  5. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  6. #include "stm32mp15-u-boot.dtsi"
  7. #include "stm32mp15-ddr3-1x4Gb-1066-binG.dtsi"
  8. / {
  9. aliases {
  10. i2c3 = &i2c4;
  11. usb0 = &usbotg_hs;
  12. };
  13. config {
  14. u-boot,boot-led = "heartbeat";
  15. u-boot,error-led = "error";
  16. u-boot,mmc-env-partition = "ssbl";
  17. st,adc_usb_pd = <&adc1 18>, <&adc1 19>;
  18. st,fastboot-gpios = <&gpioa 13 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  19. st,stm32prog-gpios = <&gpioa 14 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>;
  20. };
  21. #ifdef CONFIG_STM32MP15x_STM32IMAGE
  22. /* only needed for boot with TF-A, witout FIP support */
  23. firmware {
  24. optee {
  25. compatible = "linaro,optee-tz";
  26. method = "smc";
  27. };
  28. };
  29. reserved-memory {
  30. u-boot,dm-spl;
  31. optee@de000000 {
  32. reg = <0xde000000 0x02000000>;
  33. no-map;
  34. u-boot,dm-spl;
  35. };
  36. };
  37. #endif
  38. led {
  39. red {
  40. label = "error";
  41. gpios = <&gpioa 13 GPIO_ACTIVE_LOW>;
  42. default-state = "off";
  43. status = "okay";
  44. };
  45. };
  46. };
  47. &adc {
  48. status = "okay";
  49. };
  50. &clk_hse {
  51. st,digbypass;
  52. };
  53. &i2c4 {
  54. u-boot,dm-pre-reloc;
  55. };
  56. &i2c4_pins_a {
  57. u-boot,dm-pre-reloc;
  58. pins {
  59. u-boot,dm-pre-reloc;
  60. };
  61. };
  62. &pmic {
  63. u-boot,dm-pre-reloc;
  64. };
  65. &rcc {
  66. st,clksrc = <
  67. CLK_MPU_PLL1P
  68. CLK_AXI_PLL2P
  69. CLK_MCU_PLL3P
  70. CLK_PLL12_HSE
  71. CLK_PLL3_HSE
  72. CLK_PLL4_HSE
  73. CLK_RTC_LSE
  74. CLK_MCO1_DISABLED
  75. CLK_MCO2_DISABLED
  76. >;
  77. st,clkdiv = <
  78. 1 /*MPU*/
  79. 0 /*AXI*/
  80. 0 /*MCU*/
  81. 1 /*APB1*/
  82. 1 /*APB2*/
  83. 1 /*APB3*/
  84. 1 /*APB4*/
  85. 2 /*APB5*/
  86. 23 /*RTC*/
  87. 0 /*MCO1*/
  88. 0 /*MCO2*/
  89. >;
  90. st,pkcs = <
  91. CLK_CKPER_HSE
  92. CLK_FMC_ACLK
  93. CLK_QSPI_ACLK
  94. CLK_ETH_DISABLED
  95. CLK_SDMMC12_PLL4P
  96. CLK_DSI_DSIPLL
  97. CLK_STGEN_HSE
  98. CLK_USBPHY_HSE
  99. CLK_SPI2S1_PLL3Q
  100. CLK_SPI2S23_PLL3Q
  101. CLK_SPI45_HSI
  102. CLK_SPI6_HSI
  103. CLK_I2C46_HSI
  104. CLK_SDMMC3_PLL4P
  105. CLK_USBO_USBPHY
  106. CLK_ADC_CKPER
  107. CLK_CEC_LSE
  108. CLK_I2C12_HSI
  109. CLK_I2C35_HSI
  110. CLK_UART1_HSI
  111. CLK_UART24_HSI
  112. CLK_UART35_HSI
  113. CLK_UART6_HSI
  114. CLK_UART78_HSI
  115. CLK_SPDIF_PLL4P
  116. CLK_FDCAN_PLL4R
  117. CLK_SAI1_PLL3Q
  118. CLK_SAI2_PLL3Q
  119. CLK_SAI3_PLL3Q
  120. CLK_SAI4_PLL3Q
  121. CLK_RNG1_LSI
  122. CLK_RNG2_LSI
  123. CLK_LPTIM1_PCLK1
  124. CLK_LPTIM23_PCLK3
  125. CLK_LPTIM45_LSE
  126. >;
  127. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  128. pll2: st,pll@1 {
  129. compatible = "st,stm32mp1-pll";
  130. reg = <1>;
  131. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  132. frac = < 0x1400 >;
  133. u-boot,dm-pre-reloc;
  134. };
  135. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  136. pll3: st,pll@2 {
  137. compatible = "st,stm32mp1-pll";
  138. reg = <2>;
  139. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  140. frac = < 0x1a04 >;
  141. u-boot,dm-pre-reloc;
  142. };
  143. /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
  144. pll4: st,pll@3 {
  145. compatible = "st,stm32mp1-pll";
  146. reg = <3>;
  147. cfg = < 3 98 5 7 7 PQR(1,1,1) >;
  148. u-boot,dm-pre-reloc;
  149. };
  150. };
  151. &sdmmc1 {
  152. u-boot,dm-spl;
  153. };
  154. &sdmmc1_b4_pins_a {
  155. u-boot,dm-spl;
  156. pins1 {
  157. u-boot,dm-spl;
  158. };
  159. pins2 {
  160. u-boot,dm-spl;
  161. };
  162. };
  163. &uart4 {
  164. u-boot,dm-pre-reloc;
  165. };
  166. &uart4_pins_a {
  167. u-boot,dm-pre-reloc;
  168. pins1 {
  169. u-boot,dm-pre-reloc;
  170. };
  171. pins2 {
  172. u-boot,dm-pre-reloc;
  173. /* pull-up on rx to avoid floating level */
  174. bias-pull-up;
  175. };
  176. };
  177. &usbotg_hs {
  178. u-boot,force-b-session-valid;
  179. };