zynqpl.h 2.4 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2012-2013, Xilinx, Michal Simek
  4. *
  5. * (C) Copyright 2012
  6. * Joe Hershberger <joe.hershberger@ni.com>
  7. */
  8. #ifndef _ZYNQPL_H_
  9. #define _ZYNQPL_H_
  10. #include <xilinx.h>
  11. #if defined(CONFIG_FPGA_ZYNQPL)
  12. extern struct xilinx_fpga_op zynq_op;
  13. # define FPGA_ZYNQPL_OPS &zynq_op
  14. #else
  15. # define FPGA_ZYNQPL_OPS NULL
  16. #endif
  17. #define XILINX_ZYNQ_7007S 0x3
  18. #define XILINX_ZYNQ_7010 0x2
  19. #define XILINX_ZYNQ_7012S 0x1c
  20. #define XILINX_ZYNQ_7014S 0x8
  21. #define XILINX_ZYNQ_7015 0x1b
  22. #define XILINX_ZYNQ_7020 0x7
  23. #define XILINX_ZYNQ_7030 0xc
  24. #define XILINX_ZYNQ_7035 0x12
  25. #define XILINX_ZYNQ_7045 0x11
  26. #define XILINX_ZYNQ_7100 0x16
  27. /* Device Image Sizes */
  28. #define XILINX_XC7Z007S_SIZE 16669920/8
  29. #define XILINX_XC7Z010_SIZE 16669920/8
  30. #define XILINX_XC7Z012S_SIZE 28085344/8
  31. #define XILINX_XC7Z014S_SIZE 32364512/8
  32. #define XILINX_XC7Z015_SIZE 28085344/8
  33. #define XILINX_XC7Z020_SIZE 32364512/8
  34. #define XILINX_XC7Z030_SIZE 47839328/8
  35. #define XILINX_XC7Z035_SIZE 106571232/8
  36. #define XILINX_XC7Z045_SIZE 106571232/8
  37. #define XILINX_XC7Z100_SIZE 139330784/8
  38. /* Descriptor Macros */
  39. #define XILINX_XC7Z007S_DESC(cookie) \
  40. { xilinx_zynq, devcfg, XILINX_XC7Z007S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  41. "7z007s" }
  42. #define XILINX_XC7Z010_DESC(cookie) \
  43. { xilinx_zynq, devcfg, XILINX_XC7Z010_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  44. "7z010" }
  45. #define XILINX_XC7Z012S_DESC(cookie) \
  46. { xilinx_zynq, devcfg, XILINX_XC7Z012S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  47. "7z012s" }
  48. #define XILINX_XC7Z014S_DESC(cookie) \
  49. { xilinx_zynq, devcfg, XILINX_XC7Z014S_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  50. "7z014s" }
  51. #define XILINX_XC7Z015_DESC(cookie) \
  52. { xilinx_zynq, devcfg, XILINX_XC7Z015_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  53. "7z015" }
  54. #define XILINX_XC7Z020_DESC(cookie) \
  55. { xilinx_zynq, devcfg, XILINX_XC7Z020_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  56. "7z020" }
  57. #define XILINX_XC7Z030_DESC(cookie) \
  58. { xilinx_zynq, devcfg, XILINX_XC7Z030_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  59. "7z030" }
  60. #define XILINX_XC7Z035_DESC(cookie) \
  61. { xilinx_zynq, devcfg, XILINX_XC7Z035_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  62. "7z035" }
  63. #define XILINX_XC7Z045_DESC(cookie) \
  64. { xilinx_zynq, devcfg, XILINX_XC7Z045_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  65. "7z045" }
  66. #define XILINX_XC7Z100_DESC(cookie) \
  67. { xilinx_zynq, devcfg, XILINX_XC7Z100_SIZE, NULL, cookie, FPGA_ZYNQPL_OPS, \
  68. "7z100" }
  69. #endif /* _ZYNQPL_H_ */