vsc9953.h 15 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2013, 2015 Freescale Semiconductor, Inc.
  4. *
  5. * Driver for the Vitesse VSC9953 L2 Switch
  6. */
  7. #ifndef _VSC9953_H_
  8. #define _VSC9953_H_
  9. #include <config.h>
  10. #include <miiphy.h>
  11. #include <asm/types.h>
  12. #define VSC9953_OFFSET (CONFIG_SYS_CCSRBAR_DEFAULT + 0x800000)
  13. #define VSC9953_SYS_OFFSET 0x010000
  14. #define VSC9953_REW_OFFSET 0x030000
  15. #define VSC9953_DEV_GMII_OFFSET 0x100000
  16. #define VSC9953_QSYS_OFFSET 0x200000
  17. #define VSC9953_ANA_OFFSET 0x280000
  18. #define VSC9953_DEVCPU_GCB 0x070000
  19. #define VSC9953_ES0 0x040000
  20. #define VSC9953_IS1 0x050000
  21. #define VSC9953_IS2 0x060000
  22. #define T1040_SWITCH_GMII_DEV_OFFSET 0x010000
  23. #define VSC9953_PHY_REGS_OFFST 0x0000AC
  24. /* Macros for vsc9953_chip_regs.soft_rst register */
  25. #define VSC9953_SOFT_SWC_RST_ENA 0x00000001
  26. /* Macros for vsc9953_sys_sys.reset_cfg register */
  27. #define VSC9953_CORE_ENABLE 0x80
  28. #define VSC9953_MEM_ENABLE 0x40
  29. #define VSC9953_MEM_INIT 0x20
  30. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ena_cfg register */
  31. #define VSC9953_MAC_ENA_CFG 0x00000011
  32. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_mode_cfg register */
  33. #define VSC9953_MAC_MODE_CFG 0x00000011
  34. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_ifg_cfg register */
  35. #define VSC9953_MAC_IFG_CFG 0x00000515
  36. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_hdx_cfg register */
  37. #define VSC9953_MAC_HDX_CFG 0x00001043
  38. /* Macros for vsc9953_dev_gmii_mac_cfg_status.mac_maxlen_cfg register */
  39. #define VSC9953_MAC_MAX_LEN 0x000005ee
  40. /* Macros for vsc9953_dev_gmii_port_mode.clock_cfg register */
  41. #define VSC9953_CLOCK_CFG 0x00000001
  42. #define VSC9953_CLOCK_CFG_1000M 0x00000001
  43. /* Macros for vsc9953_sys_sys.front_port_mode register */
  44. #define VSC9953_FRONT_PORT_MODE 0x00000000
  45. /* Macros for vsc9953_ana_pfc.pfc_cfg register */
  46. #define VSC9953_PFC_FC 0x00000001
  47. #define VSC9953_PFC_FC_QSGMII 0x00000000
  48. /* Macros for vsc9953_sys_pause_cfg.mac_fc_cfg register */
  49. #define VSC9953_MAC_FC_CFG 0x04700000
  50. #define VSC9953_MAC_FC_CFG_QSGMII 0x00700000
  51. /* Macros for vsc9953_sys_pause_cfg.pause_cfg register */
  52. #define VSC9953_PAUSE_CFG 0x001ffffe
  53. /* Macros for vsc9953_sys_pause_cfgtot_tail_drop_lvl register */
  54. #define VSC9953_TOT_TAIL_DROP_LVL 0x000003ff
  55. /* Macros for vsc9953_sys_sys.stat_cfg register */
  56. #define VSC9953_STAT_CLEAR_RX 0x00000400
  57. #define VSC9953_STAT_CLEAR_TX 0x00000800
  58. #define VSC9953_STAT_CLEAR_DR 0x00001000
  59. /* Macros for vsc9953_vcap_core_cfg.vcap_mv_cfg register */
  60. #define VSC9953_VCAP_MV_CFG 0x0000ffff
  61. #define VSC9953_VCAP_UPDATE_CTRL 0x01000004
  62. /* Macros for register vsc9953_ana_ana_tables.mac_access register */
  63. #define VSC9953_MAC_CMD_IDLE 0x00000000
  64. #define VSC9953_MAC_CMD_LEARN 0x00000001
  65. #define VSC9953_MAC_CMD_FORGET 0x00000002
  66. #define VSC9953_MAC_CMD_AGE 0x00000003
  67. #define VSC9953_MAC_CMD_NEXT 0x00000004
  68. #define VSC9953_MAC_CMD_READ 0x00000006
  69. #define VSC9953_MAC_CMD_WRITE 0x00000007
  70. #define VSC9953_MAC_CMD_MASK 0x00000007
  71. #define VSC9953_MAC_CMD_VALID 0x00000800
  72. #define VSC9953_MAC_ENTRYTYPE_NORMAL 0x00000000
  73. #define VSC9953_MAC_ENTRYTYPE_LOCKED 0x00000200
  74. #define VSC9953_MAC_ENTRYTYPE_IPV4MCAST 0x00000400
  75. #define VSC9953_MAC_ENTRYTYPE_IPV6MCAST 0x00000600
  76. #define VSC9953_MAC_ENTRYTYPE_MASK 0x00000600
  77. #define VSC9953_MAC_DESTIDX_MASK 0x000001f8
  78. #define VSC9953_MAC_VID_MASK 0x1fff0000
  79. #define VSC9953_MAC_MACH_MASK 0x0000ffff
  80. /* Macros for vsc9953_ana_port.vlan_cfg register */
  81. #define VSC9953_VLAN_CFG_AWARE_ENA 0x00100000
  82. #define VSC9953_VLAN_CFG_POP_CNT_MASK 0x000c0000
  83. #define VSC9953_VLAN_CFG_POP_CNT_NONE 0x00000000
  84. #define VSC9953_VLAN_CFG_POP_CNT_ONE 0x00040000
  85. #define VSC9953_VLAN_CFG_VID_MASK 0x00000fff
  86. /* Macros for vsc9953_rew_port.port_vlan_cfg register */
  87. #define VSC9953_PORT_VLAN_CFG_VID_MASK 0x00000fff
  88. /* Macros for vsc9953_ana_ana_tables.vlan_tidx register */
  89. #define VSC9953_ANA_TBL_VID_MASK 0x00000fff
  90. /* Macros for vsc9953_ana_ana_tables.vlan_access register */
  91. #define VSC9953_VLAN_PORT_MASK 0x00001ffc
  92. #define VSC9953_VLAN_CMD_MASK 0x00000003
  93. #define VSC9953_VLAN_CMD_IDLE 0x00000000
  94. #define VSC9953_VLAN_CMD_READ 0x00000001
  95. #define VSC9953_VLAN_CMD_WRITE 0x00000002
  96. #define VSC9953_VLAN_CMD_INIT 0x00000003
  97. /* Macros for vsc9953_ana_port.port_cfg register */
  98. #define VSC9953_PORT_CFG_LEARN_ENA 0x00000080
  99. #define VSC9953_PORT_CFG_LEARN_AUTO 0x00000100
  100. #define VSC9953_PORT_CFG_LEARN_CPU 0x00000200
  101. #define VSC9953_PORT_CFG_LEARN_DROP 0x00000400
  102. #define VSC9953_PORT_CFG_PORTID_MASK 0x0000003c
  103. /* Macros for vsc9953_qsys_sys.switch_port_mode register */
  104. #define VSC9953_PORT_ENA 0x00002000
  105. /* Macros for vsc9953_ana_ana.agen_ctrl register */
  106. #define VSC9953_FID_MASK_ALL 0x00fff000
  107. /* Macros for vsc9953_ana_ana.adv_learn register */
  108. #define VSC9953_VLAN_CHK 0x00000400
  109. /* Macros for vsc9953_ana_ana.auto_age register */
  110. #define VSC9953_AUTOAGE_PERIOD_MASK 0x001ffffe
  111. /* Macros for vsc9953_rew_port.port_tag_cfg register */
  112. #define VSC9953_TAG_CFG_MASK 0x00000180
  113. #define VSC9953_TAG_CFG_NONE 0x00000000
  114. #define VSC9953_TAG_CFG_ALL_BUT_PVID_ZERO 0x00000080
  115. #define VSC9953_TAG_CFG_ALL_BUT_ZERO 0x00000100
  116. #define VSC9953_TAG_CFG_ALL 0x00000180
  117. #define VSC9953_TAG_VID_PVID 0x00000010
  118. /* Macros for vsc9953_ana_ana.anag_efil register */
  119. #define VSC9953_AGE_PORT_EN 0x00080000
  120. #define VSC9953_AGE_PORT_MASK 0x0007c000
  121. #define VSC9953_AGE_VID_EN 0x00002000
  122. #define VSC9953_AGE_VID_MASK 0x00001fff
  123. /* Macros for vsc9953_ana_ana_tables.mach_data register */
  124. #define VSC9953_MACHDATA_VID_MASK 0x1fff0000
  125. /* Macros for vsc9953_ana_common.aggr_cfg register */
  126. #define VSC9953_AC_RND_ENA 0x00000080
  127. #define VSC9953_AC_DMAC_ENA 0x00000040
  128. #define VSC9953_AC_SMAC_ENA 0x00000020
  129. #define VSC9953_AC_IP6_LBL_ENA 0x00000010
  130. #define VSC9953_AC_IP6_TCPUDP_ENA 0x00000008
  131. #define VSC9953_AC_IP4_SIPDIP_ENA 0x00000004
  132. #define VSC9953_AC_IP4_TCPUDP_ENA 0x00000002
  133. #define VSC9953_AC_MASK 0x000000fe
  134. /* Macros for vsc9953_ana_pgid.port_grp_id[] registers */
  135. #define VSC9953_PGID_PORT_MASK 0x000003ff
  136. #define VSC9953_MAX_PORTS 10
  137. #define VSC9953_PORT_CHECK(port) \
  138. (((port) < 0 || (port) >= VSC9953_MAX_PORTS) ? 0 : 1)
  139. #define VSC9953_INTERNAL_PORT_CHECK(port) ( \
  140. ( \
  141. (port) < VSC9953_MAX_PORTS - 2 || (port) >= VSC9953_MAX_PORTS \
  142. ) ? 0 : 1 \
  143. )
  144. #define VSC9953_MAX_VLAN 4096
  145. #define VSC9953_VLAN_CHECK(vid) \
  146. (((vid) < 0 || (vid) >= VSC9953_MAX_VLAN) ? 0 : 1)
  147. #define VSC9953_DEFAULT_AGE_TIME 300
  148. #define DEFAULT_VSC9953_MDIO_NAME "VSC9953_MDIO0"
  149. #define MIIMIND_OPR_PEND 0x00000004
  150. struct vsc9953_mdio_info {
  151. struct vsc9953_mii_mng *regs;
  152. char *name;
  153. };
  154. /* VSC9953 ANA structure */
  155. struct vsc9953_ana_port {
  156. u32 vlan_cfg;
  157. u32 drop_cfg;
  158. u32 qos_cfg;
  159. u32 vcap_cfg;
  160. u32 vcap_s1_key_cfg[3];
  161. u32 vcap_s2_cfg;
  162. u32 qos_pcp_dei_map_cfg[16];
  163. u32 cpu_fwd_cfg;
  164. u32 cpu_fwd_bpdu_cfg;
  165. u32 cpu_fwd_garp_cfg;
  166. u32 cpu_fwd_ccm_cfg;
  167. u32 port_cfg;
  168. u32 pol_cfg;
  169. u32 reserved[34];
  170. };
  171. struct vsc9953_ana_pol {
  172. u32 pol_pir_cfg;
  173. u32 pol_cir_cfg;
  174. u32 pol_mode_cfg;
  175. u32 pol_pir_state;
  176. u32 pol_cir_state;
  177. u32 reserved1[3];
  178. };
  179. struct vsc9953_ana_ana_tables {
  180. u32 entry_lim[11];
  181. u32 an_moved;
  182. u32 mach_data;
  183. u32 macl_data;
  184. u32 mac_access;
  185. u32 mact_indx;
  186. u32 vlan_access;
  187. u32 vlan_tidx;
  188. };
  189. struct vsc9953_ana_ana {
  190. u32 adv_learn;
  191. u32 vlan_mask;
  192. u32 reserved;
  193. u32 anag_efil;
  194. u32 an_events;
  195. u32 storm_limit_burst;
  196. u32 storm_limit_cfg[4];
  197. u32 isolated_prts;
  198. u32 community_ports;
  199. u32 auto_age;
  200. u32 mac_options;
  201. u32 learn_disc;
  202. u32 agen_ctrl;
  203. u32 mirror_ports;
  204. u32 emirror_ports;
  205. u32 flooding;
  206. u32 flooding_ipmc;
  207. u32 sflow_cfg[11];
  208. u32 port_mode[12];
  209. };
  210. #define PGID_DST_START 0
  211. #define PGID_AGGR_START 64
  212. #define PGID_SRC_START 80
  213. struct vsc9953_ana_pgid {
  214. u32 port_grp_id[91];
  215. };
  216. struct vsc9953_ana_pfc {
  217. u32 pfc_cfg;
  218. u32 reserved1[15];
  219. };
  220. struct vsc9953_ana_pol_misc {
  221. u32 pol_flowc[10];
  222. u32 reserved1[17];
  223. u32 pol_hyst;
  224. };
  225. struct vsc9953_ana_common {
  226. u32 aggr_cfg;
  227. u32 cpuq_cfg;
  228. u32 cpuq_8021_cfg;
  229. u32 dscp_cfg;
  230. u32 dscp_rewr_cfg;
  231. u32 vcap_rng_type_cfg;
  232. u32 vcap_rng_val_cfg;
  233. u32 discard_cfg;
  234. u32 fid_cfg;
  235. };
  236. struct vsc9953_analyzer {
  237. struct vsc9953_ana_port port[11];
  238. u32 reserved1[9536];
  239. struct vsc9953_ana_pol pol[164];
  240. struct vsc9953_ana_ana_tables ana_tables;
  241. u32 reserved2[14];
  242. struct vsc9953_ana_ana ana;
  243. u32 reserved3[21];
  244. struct vsc9953_ana_pgid port_id_tbl;
  245. u32 reserved4[549];
  246. struct vsc9953_ana_pfc pfc[10];
  247. struct vsc9953_ana_pol_misc pol_misc;
  248. u32 reserved5[196];
  249. struct vsc9953_ana_common common;
  250. };
  251. /* END VSC9953 ANA structure t*/
  252. /* VSC9953 DEV_GMII structure */
  253. struct vsc9953_dev_gmii_port_mode {
  254. u32 clock_cfg;
  255. u32 port_misc;
  256. u32 reserved1;
  257. u32 eee_cfg;
  258. };
  259. struct vsc9953_dev_gmii_mac_cfg_status {
  260. u32 mac_ena_cfg;
  261. u32 mac_mode_cfg;
  262. u32 mac_maxlen_cfg;
  263. u32 mac_tags_cfg;
  264. u32 mac_adv_chk_cfg;
  265. u32 mac_ifg_cfg;
  266. u32 mac_hdx_cfg;
  267. u32 mac_fc_mac_low_cfg;
  268. u32 mac_fc_mac_high_cfg;
  269. u32 mac_sticky;
  270. };
  271. struct vsc9953_dev_gmii {
  272. struct vsc9953_dev_gmii_port_mode port_mode;
  273. struct vsc9953_dev_gmii_mac_cfg_status mac_cfg_status;
  274. };
  275. /* END VSC9953 DEV_GMII structure */
  276. /* VSC9953 QSYS structure */
  277. struct vsc9953_qsys_hsch {
  278. u32 cir_cfg;
  279. u32 reserved1;
  280. u32 se_cfg;
  281. u32 se_dwrr_cfg[8];
  282. u32 cir_state;
  283. u32 reserved2[20];
  284. };
  285. struct vsc9953_qsys_sys {
  286. u32 port_mode[12];
  287. u32 switch_port_mode[11];
  288. u32 stat_cnt_cfg;
  289. u32 eee_cfg[10];
  290. u32 eee_thrs;
  291. u32 igr_no_sharing;
  292. u32 egr_no_sharing;
  293. u32 sw_status[11];
  294. u32 ext_cpu_cfg;
  295. u32 cpu_group_map;
  296. u32 reserved1[23];
  297. };
  298. struct vsc9953_qsys_qos_cfg {
  299. u32 red_profile[16];
  300. u32 res_qos_mode;
  301. };
  302. struct vsc9953_qsys_drop_cfg {
  303. u32 egr_drop_mode;
  304. };
  305. struct vsc9953_qsys_mmgt {
  306. u32 eq_cntrl;
  307. u32 reserved1;
  308. };
  309. struct vsc9953_qsys_hsch_misc {
  310. u32 hsch_misc_cfg;
  311. u32 reserved1[546];
  312. };
  313. struct vsc9953_qsys_res_ctrl {
  314. u32 res_cfg;
  315. u32 res_stat;
  316. };
  317. struct vsc9953_qsys_reg {
  318. struct vsc9953_qsys_hsch hsch[108];
  319. struct vsc9953_qsys_sys sys;
  320. struct vsc9953_qsys_qos_cfg qos_cfg;
  321. struct vsc9953_qsys_drop_cfg drop_cfg;
  322. struct vsc9953_qsys_mmgt mmgt;
  323. struct vsc9953_qsys_hsch_misc hsch_misc;
  324. struct vsc9953_qsys_res_ctrl res_ctrl[1024];
  325. };
  326. /* END VSC9953 QSYS structure */
  327. /* VSC9953 SYS structure */
  328. struct vsc9953_rx_cntrs {
  329. u32 c_rx_oct;
  330. u32 c_rx_uc;
  331. u32 c_rx_mc;
  332. u32 c_rx_bc;
  333. u32 c_rx_short;
  334. u32 c_rx_frag;
  335. u32 c_rx_jabber;
  336. u32 c_rx_crc;
  337. u32 c_rx_symbol_err;
  338. u32 c_rx_sz_64;
  339. u32 c_rx_sz_65_127;
  340. u32 c_rx_sz_128_255;
  341. u32 c_rx_sz_256_511;
  342. u32 c_rx_sz_512_1023;
  343. u32 c_rx_sz_1024_1526;
  344. u32 c_rx_sz_jumbo;
  345. u32 c_rx_pause;
  346. u32 c_rx_control;
  347. u32 c_rx_long;
  348. u32 c_rx_cat_drop;
  349. u32 c_rx_red_prio_0;
  350. u32 c_rx_red_prio_1;
  351. u32 c_rx_red_prio_2;
  352. u32 c_rx_red_prio_3;
  353. u32 c_rx_red_prio_4;
  354. u32 c_rx_red_prio_5;
  355. u32 c_rx_red_prio_6;
  356. u32 c_rx_red_prio_7;
  357. u32 c_rx_yellow_prio_0;
  358. u32 c_rx_yellow_prio_1;
  359. u32 c_rx_yellow_prio_2;
  360. u32 c_rx_yellow_prio_3;
  361. u32 c_rx_yellow_prio_4;
  362. u32 c_rx_yellow_prio_5;
  363. u32 c_rx_yellow_prio_6;
  364. u32 c_rx_yellow_prio_7;
  365. u32 c_rx_green_prio_0;
  366. u32 c_rx_green_prio_1;
  367. u32 c_rx_green_prio_2;
  368. u32 c_rx_green_prio_3;
  369. u32 c_rx_green_prio_4;
  370. u32 c_rx_green_prio_5;
  371. u32 c_rx_green_prio_6;
  372. u32 c_rx_green_prio_7;
  373. u32 reserved[20];
  374. };
  375. struct vsc9953_tx_cntrs {
  376. u32 c_tx_oct;
  377. u32 c_tx_uc;
  378. u32 c_tx_mc;
  379. u32 c_tx_bc;
  380. u32 c_tx_col;
  381. u32 c_tx_drop;
  382. u32 c_tx_pause;
  383. u32 c_tx_sz_64;
  384. u32 c_tx_sz_65_127;
  385. u32 c_tx_sz_128_255;
  386. u32 c_tx_sz_256_511;
  387. u32 c_tx_sz_512_1023;
  388. u32 c_tx_sz_1024_1526;
  389. u32 c_tx_sz_jumbo;
  390. u32 c_tx_yellow_prio_0;
  391. u32 c_tx_yellow_prio_1;
  392. u32 c_tx_yellow_prio_2;
  393. u32 c_tx_yellow_prio_3;
  394. u32 c_tx_yellow_prio_4;
  395. u32 c_tx_yellow_prio_5;
  396. u32 c_tx_yellow_prio_6;
  397. u32 c_tx_yellow_prio_7;
  398. u32 c_tx_green_prio_0;
  399. u32 c_tx_green_prio_1;
  400. u32 c_tx_green_prio_2;
  401. u32 c_tx_green_prio_3;
  402. u32 c_tx_green_prio_4;
  403. u32 c_tx_green_prio_5;
  404. u32 c_tx_green_prio_6;
  405. u32 c_tx_green_prio_7;
  406. u32 c_tx_aged;
  407. u32 reserved[33];
  408. };
  409. struct vsc9953_drop_cntrs {
  410. u32 c_dr_local;
  411. u32 c_dr_tail;
  412. u32 c_dr_yellow_prio_0;
  413. u32 c_dr_yellow_prio_1;
  414. u32 c_dr_yellow_prio_2;
  415. u32 c_dr_yellow_prio_3;
  416. u32 c_dr_yellow_prio_4;
  417. u32 c_dr_yellow_prio_5;
  418. u32 c_dr_yellow_prio_6;
  419. u32 c_dr_yellow_prio_7;
  420. u32 c_dr_green_prio_0;
  421. u32 c_dr_green_prio_1;
  422. u32 c_dr_green_prio_2;
  423. u32 c_dr_green_prio_3;
  424. u32 c_dr_green_prio_4;
  425. u32 c_dr_green_prio_5;
  426. u32 c_dr_green_prio_6;
  427. u32 c_dr_green_prio_7;
  428. u32 reserved[46];
  429. };
  430. struct vsc9953_sys_stat {
  431. struct vsc9953_rx_cntrs rx_cntrs;
  432. struct vsc9953_tx_cntrs tx_cntrs;
  433. struct vsc9953_drop_cntrs drop_cntrs;
  434. u32 reserved1[6];
  435. };
  436. struct vsc9953_sys_sys {
  437. u32 reset_cfg;
  438. u32 reserved1;
  439. u32 vlan_etype_cfg;
  440. u32 port_mode[12];
  441. u32 front_port_mode[10];
  442. u32 frame_aging;
  443. u32 stat_cfg;
  444. u32 reserved2[50];
  445. };
  446. struct vsc9953_sys_pause_cfg {
  447. u32 pause_cfg[11];
  448. u32 pause_tot_cfg;
  449. u32 tail_drop_level[11];
  450. u32 tot_tail_drop_lvl;
  451. u32 mac_fc_cfg[10];
  452. };
  453. struct vsc9953_sys_mmgt {
  454. u16 free_cnt;
  455. };
  456. struct vsc9953_system_reg {
  457. struct vsc9953_sys_stat stat;
  458. struct vsc9953_sys_sys sys;
  459. struct vsc9953_sys_pause_cfg pause_cfg;
  460. struct vsc9953_sys_mmgt mmgt;
  461. };
  462. /* END VSC9953 SYS structure */
  463. /* VSC9953 REW structure */
  464. struct vsc9953_rew_port {
  465. u32 port_vlan_cfg;
  466. u32 port_tag_cfg;
  467. u32 port_port_cfg;
  468. u32 port_dscp_cfg;
  469. u32 port_pcp_dei_qos_map_cfg[16];
  470. u32 reserved[12];
  471. };
  472. struct vsc9953_rew_common {
  473. u32 reserve[4];
  474. u32 dscp_remap_dp1_cfg[64];
  475. u32 dscp_remap_cfg[64];
  476. };
  477. struct vsc9953_rew_reg {
  478. struct vsc9953_rew_port port[12];
  479. struct vsc9953_rew_common common;
  480. };
  481. /* END VSC9953 REW structure */
  482. /* VSC9953 DEVCPU_GCB structure */
  483. struct vsc9953_chip_regs {
  484. u32 chipd_id;
  485. u32 gpr;
  486. u32 soft_rst;
  487. };
  488. struct vsc9953_gpio {
  489. u32 gpio_out_set[10];
  490. u32 gpio_out_clr[10];
  491. u32 gpio_out[10];
  492. u32 gpio_in[10];
  493. };
  494. struct vsc9953_mii_mng {
  495. u32 miimstatus;
  496. u32 reserved1;
  497. u32 miimcmd;
  498. u32 miimdata;
  499. u32 miimcfg;
  500. u32 miimscan_0;
  501. u32 miimscan_1;
  502. u32 miiscan_lst_rslts;
  503. u32 miiscan_lst_rslts_valid;
  504. };
  505. struct vsc9953_mii_read_scan {
  506. u32 mii_scan_results_sticky[2];
  507. };
  508. struct vsc9953_devcpu_gcb {
  509. struct vsc9953_chip_regs chip_regs;
  510. struct vsc9953_gpio gpio;
  511. struct vsc9953_mii_mng mii_mng[2];
  512. struct vsc9953_mii_read_scan mii_read_scan;
  513. };
  514. /* END VSC9953 DEVCPU_GCB structure */
  515. /* VSC9953 IS* structure */
  516. struct vsc9953_vcap_core_cfg {
  517. u32 vcap_update_ctrl;
  518. u32 vcap_mv_cfg;
  519. };
  520. struct vsc9953_vcap {
  521. struct vsc9953_vcap_core_cfg vcap_core_cfg;
  522. };
  523. /* END VSC9953 IS* structure */
  524. #define VSC9953_PORT_INFO_INITIALIZER(idx) \
  525. { \
  526. .enabled = 0, \
  527. .phyaddr = 0, \
  528. .index = idx, \
  529. .phy_regs = NULL, \
  530. .enet_if = PHY_INTERFACE_MODE_NONE, \
  531. .bus = NULL, \
  532. .phydev = NULL, \
  533. }
  534. /* Structure to describe a VSC9953 port */
  535. struct vsc9953_port_info {
  536. u8 enabled;
  537. u8 phyaddr;
  538. int index;
  539. void *phy_regs;
  540. phy_interface_t enet_if;
  541. struct mii_dev *bus;
  542. struct phy_device *phydev;
  543. };
  544. /* Structure to describe a VSC9953 switch */
  545. struct vsc9953_info {
  546. struct vsc9953_port_info port[VSC9953_MAX_PORTS];
  547. };
  548. void vsc9953_init(bd_t *bis);
  549. void vsc9953_port_info_set_mdio(int port_no, struct mii_dev *bus);
  550. void vsc9953_port_info_set_phy_address(int port_no, int address);
  551. void vsc9953_port_enable(int port_no);
  552. void vsc9953_port_disable(int port_no);
  553. void vsc9953_port_info_set_phy_int(int port_no, phy_interface_t phy_int);
  554. #endif /* _VSC9953_H_ */