tsi108.h 5.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*****************************************************************************
  3. * (C) Copyright 2003; Tundra Semiconductor Corp.
  4. * (C) Copyright 2006; Freescale Semiconductor Corp.
  5. *****************************************************************************/
  6. /*
  7. * FILENAME: tsi108.h
  8. *
  9. * Originator: Alex Bounine
  10. *
  11. * DESCRIPTION:
  12. * Common definitions for the Tundra Tsi108 bridge chip
  13. *
  14. */
  15. #ifndef _TSI108_H_
  16. #define _TSI108_H_
  17. #define TSI108_HLP_REG_OFFSET (0x0000)
  18. #define TSI108_PCI_REG_OFFSET (0x1000)
  19. #define TSI108_CLK_REG_OFFSET (0x2000)
  20. #define TSI108_PB_REG_OFFSET (0x3000)
  21. #define TSI108_SD_REG_OFFSET (0x4000)
  22. #define TSI108_MPIC_REG_OFFSET (0x7400)
  23. #define PB_ID (0x000)
  24. #define PB_RSR (0x004)
  25. #define PB_BUS_MS_SELECT (0x008)
  26. #define PB_ISR (0x00C)
  27. #define PB_ARB_CTRL (0x018)
  28. #define PB_PVT_CTRL2 (0x034)
  29. #define PB_SCR (0x400)
  30. #define PB_ERRCS (0x404)
  31. #define PB_AERR (0x408)
  32. #define PB_REG_BAR (0x410)
  33. #define PB_OCN_BAR1 (0x414)
  34. #define PB_OCN_BAR2 (0x418)
  35. #define PB_SDRAM_BAR1 (0x41C)
  36. #define PB_SDRAM_BAR2 (0x420)
  37. #define PB_MCR (0xC00)
  38. #define PB_MCMD (0xC04)
  39. #define HLP_B0_ADDR (0x000)
  40. #define HLP_B1_ADDR (0x010)
  41. #define HLP_B2_ADDR (0x020)
  42. #define HLP_B3_ADDR (0x030)
  43. #define HLP_B0_MASK (0x004)
  44. #define HLP_B1_MASK (0x014)
  45. #define HLP_B2_MASK (0x024)
  46. #define HLP_B3_MASK (0x034)
  47. #define HLP_B0_CTRL0 (0x008)
  48. #define HLP_B1_CTRL0 (0x018)
  49. #define HLP_B2_CTRL0 (0x028)
  50. #define HLP_B3_CTRL0 (0x038)
  51. #define HLP_B0_CTRL1 (0x00C)
  52. #define HLP_B1_CTRL1 (0x01C)
  53. #define HLP_B2_CTRL1 (0x02C)
  54. #define HLP_B3_CTRL1 (0x03C)
  55. #define PCI_CSR (0x004)
  56. #define PCI_P2O_BAR0 (0x010)
  57. #define PCI_P2O_BAR0_UPPER (0x014)
  58. #define PCI_P2O_BAR2 (0x018)
  59. #define PCI_P2O_BAR2_UPPER (0x01C)
  60. #define PCI_P2O_BAR3 (0x020)
  61. #define PCI_P2O_BAR3_UPPER (0x024)
  62. #define PCI_MISC_CSR (0x040)
  63. #define PCI_P2O_PAGE_SIZES (0x04C)
  64. #define PCI_PCIX_STAT (0x0F4)
  65. #define PCI_IRP_STAT (0x184)
  66. #define PCI_PFAB_BAR0 (0x204)
  67. #define PCI_PFAB_BAR0_UPPER (0x208)
  68. #define PCI_PFAB_IO (0x20C)
  69. #define PCI_PFAB_IO_UPPER (0x210)
  70. #define PCI_PFAB_MEM32 (0x214)
  71. #define PCI_PFAB_MEM32_REMAP (0x218)
  72. #define PCI_PFAB_MEM32_MASK (0x21C)
  73. #define CG_PLL0_CTRL0 (0x210)
  74. #define CG_PLL0_CTRL1 (0x214)
  75. #define CG_PLL1_CTRL0 (0x220)
  76. #define CG_PLL1_CTRL1 (0x224)
  77. #define CG_PWRUP_STATUS (0x234)
  78. #define MPIC_CSR(n) (0x30C + (n * 0x40))
  79. #define SD_CTRL (0x000)
  80. #define SD_STATUS (0x004)
  81. #define SD_TIMING (0x008)
  82. #define SD_REFRESH (0x00C)
  83. #define SD_INT_STATUS (0x010)
  84. #define SD_INT_ENABLE (0x014)
  85. #define SD_INT_SET (0x018)
  86. #define SD_D0_CTRL (0x020)
  87. #define SD_D1_CTRL (0x024)
  88. #define SD_D0_BAR (0x028)
  89. #define SD_D1_BAR (0x02C)
  90. #define SD_ECC_CTRL (0x040)
  91. #define SD_DLL_STATUS (0x250)
  92. #define TS_SD_CTRL_ENABLE (1 << 31)
  93. #define PB_ERRCS_ES (1 << 1)
  94. #define PB_ISR_PBS_RD_ERR (1 << 8)
  95. #define PCI_IRP_STAT_P_CSR (1 << 23)
  96. /*
  97. * I2C : Register address offset definitions
  98. */
  99. #define I2C_CNTRL1 (0x00000000)
  100. #define I2C_CNTRL2 (0x00000004)
  101. #define I2C_RD_DATA (0x00000008)
  102. #define I2C_TX_DATA (0x0000000c)
  103. /*
  104. * I2C : Register Bit Masks and Reset Values
  105. * definitions for every register
  106. */
  107. /* I2C_CNTRL1 : Reset Value */
  108. #define I2C_CNTRL1_RESET_VALUE (0x0000000a)
  109. /* I2C_CNTRL1 : Register Bits Masks Definitions */
  110. #define I2C_CNTRL1_DEVCODE (0x0000000f)
  111. #define I2C_CNTRL1_PAGE (0x00000700)
  112. #define I2C_CNTRL1_BYTADDR (0x00ff0000)
  113. #define I2C_CNTRL1_I2CWRITE (0x01000000)
  114. /* I2C_CNTRL1 : Read/Write Bit Mask Definition */
  115. #define I2C_CNTRL1_RWMASK (0x01ff070f)
  116. /* I2C_CNTRL1 : Unused/Reserved bits Definition */
  117. #define I2C_CNTRL1_RESERVED (0xfe00f8f0)
  118. /* I2C_CNTRL2 : Reset Value */
  119. #define I2C_CNTRL2_RESET_VALUE (0x00000000)
  120. /* I2C_CNTRL2 : Register Bits Masks Definitions */
  121. #define I2C_CNTRL2_SIZE (0x00000003)
  122. #define I2C_CNTRL2_LANE (0x0000000c)
  123. #define I2C_CNTRL2_MULTIBYTE (0x00000010)
  124. #define I2C_CNTRL2_START (0x00000100)
  125. #define I2C_CNTRL2_WR_STATUS (0x00010000)
  126. #define I2C_CNTRL2_RD_STATUS (0x00020000)
  127. #define I2C_CNTRL2_I2C_TO_ERR (0x04000000)
  128. #define I2C_CNTRL2_I2C_CFGERR (0x08000000)
  129. #define I2C_CNTRL2_I2C_CMPLT (0x10000000)
  130. /* I2C_CNTRL2 : Read/Write Bit Mask Definition */
  131. #define I2C_CNTRL2_RWMASK (0x0000011f)
  132. /* I2C_CNTRL2 : Unused/Reserved bits Definition */
  133. #define I2C_CNTRL2_RESERVED (0xe3fcfee0)
  134. /* I2C_RD_DATA : Reset Value */
  135. #define I2C_RD_DATA_RESET_VALUE (0x00000000)
  136. /* I2C_RD_DATA : Register Bits Masks Definitions */
  137. #define I2C_RD_DATA_RBYTE0 (0x000000ff)
  138. #define I2C_RD_DATA_RBYTE1 (0x0000ff00)
  139. #define I2C_RD_DATA_RBYTE2 (0x00ff0000)
  140. #define I2C_RD_DATA_RBYTE3 (0xff000000)
  141. /* I2C_RD_DATA : Read/Write Bit Mask Definition */
  142. #define I2C_RD_DATA_RWMASK (0x00000000)
  143. /* I2C_RD_DATA : Unused/Reserved bits Definition */
  144. #define I2C_RD_DATA_RESERVED (0x00000000)
  145. /* I2C_TX_DATA : Reset Value */
  146. #define I2C_TX_DATA_RESET_VALUE (0x00000000)
  147. /* I2C_TX_DATA : Register Bits Masks Definitions */
  148. #define I2C_TX_DATA_TBYTE0 (0x000000ff)
  149. #define I2C_TX_DATA_TBYTE1 (0x0000ff00)
  150. #define I2C_TX_DATA_TBYTE2 (0x00ff0000)
  151. #define I2C_TX_DATA_TBYTE3 (0xff000000)
  152. /* I2C_TX_DATA : Read/Write Bit Mask Definition */
  153. #define I2C_TX_DATA_RWMASK (0xffffffff)
  154. /* I2C_TX_DATA : Unused/Reserved bits Definition */
  155. #define I2C_TX_DATA_RESERVED (0x00000000)
  156. #define TSI108_I2C_OFFSET 0x7000 /* offset for general use I2C channel */
  157. #define TSI108_I2C_SDRAM_OFFSET 0x4400 /* offset for SPD I2C channel */
  158. #define I2C_EEPROM_DEVCODE 0xA /* standard I2C EEPROM device code */
  159. /* I2C status codes */
  160. #define TSI108_I2C_SUCCESS 0
  161. #define TSI108_I2C_PARAM_ERR 1
  162. #define TSI108_I2C_TIMEOUT_ERR 2
  163. #define TSI108_I2C_IF_BUSY 3
  164. #define TSI108_I2C_IF_ERROR 4
  165. #endif /* _TSI108_H_ */