pci.h 57 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  4. * Andreas Heppel <aheppel@sysgo.de>
  5. *
  6. * (C) Copyright 2002
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. */
  9. #ifndef _PCI_H
  10. #define _PCI_H
  11. #define PCI_CFG_SPACE_SIZE 256
  12. #define PCI_CFG_SPACE_EXP_SIZE 4096
  13. /*
  14. * Under PCI, each device has 256 bytes of configuration address space,
  15. * of which the first 64 bytes are standardized as follows:
  16. */
  17. #define PCI_VENDOR_ID 0x00 /* 16 bits */
  18. #define PCI_DEVICE_ID 0x02 /* 16 bits */
  19. #define PCI_COMMAND 0x04 /* 16 bits */
  20. #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
  21. #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
  22. #define PCI_COMMAND_MASTER 0x4 /* Enable bus mastering */
  23. #define PCI_COMMAND_SPECIAL 0x8 /* Enable response to special cycles */
  24. #define PCI_COMMAND_INVALIDATE 0x10 /* Use memory write and invalidate */
  25. #define PCI_COMMAND_VGA_PALETTE 0x20 /* Enable palette snooping */
  26. #define PCI_COMMAND_PARITY 0x40 /* Enable parity checking */
  27. #define PCI_COMMAND_WAIT 0x80 /* Enable address/data stepping */
  28. #define PCI_COMMAND_SERR 0x100 /* Enable SERR */
  29. #define PCI_COMMAND_FAST_BACK 0x200 /* Enable back-to-back writes */
  30. #define PCI_STATUS 0x06 /* 16 bits */
  31. #define PCI_STATUS_CAP_LIST 0x10 /* Support Capability List */
  32. #define PCI_STATUS_66MHZ 0x20 /* Support 66 Mhz PCI 2.1 bus */
  33. #define PCI_STATUS_UDF 0x40 /* Support User Definable Features [obsolete] */
  34. #define PCI_STATUS_FAST_BACK 0x80 /* Accept fast-back to back */
  35. #define PCI_STATUS_PARITY 0x100 /* Detected parity error */
  36. #define PCI_STATUS_DEVSEL_MASK 0x600 /* DEVSEL timing */
  37. #define PCI_STATUS_DEVSEL_FAST 0x000
  38. #define PCI_STATUS_DEVSEL_MEDIUM 0x200
  39. #define PCI_STATUS_DEVSEL_SLOW 0x400
  40. #define PCI_STATUS_SIG_TARGET_ABORT 0x800 /* Set on target abort */
  41. #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /* Master ack of " */
  42. #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /* Set on master abort */
  43. #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /* Set when we drive SERR */
  44. #define PCI_STATUS_DETECTED_PARITY 0x8000 /* Set on parity error */
  45. #define PCI_CLASS_REVISION 0x08 /* High 24 bits are class, low 8
  46. revision */
  47. #define PCI_REVISION_ID 0x08 /* Revision ID */
  48. #define PCI_CLASS_PROG 0x09 /* Reg. Level Programming Interface */
  49. #define PCI_CLASS_DEVICE 0x0a /* Device class */
  50. #define PCI_CLASS_CODE 0x0b /* Device class code */
  51. #define PCI_CLASS_CODE_TOO_OLD 0x00
  52. #define PCI_CLASS_CODE_STORAGE 0x01
  53. #define PCI_CLASS_CODE_NETWORK 0x02
  54. #define PCI_CLASS_CODE_DISPLAY 0x03
  55. #define PCI_CLASS_CODE_MULTIMEDIA 0x04
  56. #define PCI_CLASS_CODE_MEMORY 0x05
  57. #define PCI_CLASS_CODE_BRIDGE 0x06
  58. #define PCI_CLASS_CODE_COMM 0x07
  59. #define PCI_CLASS_CODE_PERIPHERAL 0x08
  60. #define PCI_CLASS_CODE_INPUT 0x09
  61. #define PCI_CLASS_CODE_DOCKING 0x0A
  62. #define PCI_CLASS_CODE_PROCESSOR 0x0B
  63. #define PCI_CLASS_CODE_SERIAL 0x0C
  64. #define PCI_CLASS_CODE_WIRELESS 0x0D
  65. #define PCI_CLASS_CODE_I2O 0x0E
  66. #define PCI_CLASS_CODE_SATELLITE 0x0F
  67. #define PCI_CLASS_CODE_CRYPTO 0x10
  68. #define PCI_CLASS_CODE_DATA 0x11
  69. /* Base Class 0x12 - 0xFE is reserved */
  70. #define PCI_CLASS_CODE_OTHER 0xFF
  71. #define PCI_CLASS_SUB_CODE 0x0a /* Device sub-class code */
  72. #define PCI_CLASS_SUB_CODE_TOO_OLD_NOTVGA 0x00
  73. #define PCI_CLASS_SUB_CODE_TOO_OLD_VGA 0x01
  74. #define PCI_CLASS_SUB_CODE_STORAGE_SCSI 0x00
  75. #define PCI_CLASS_SUB_CODE_STORAGE_IDE 0x01
  76. #define PCI_CLASS_SUB_CODE_STORAGE_FLOPPY 0x02
  77. #define PCI_CLASS_SUB_CODE_STORAGE_IPIBUS 0x03
  78. #define PCI_CLASS_SUB_CODE_STORAGE_RAID 0x04
  79. #define PCI_CLASS_SUB_CODE_STORAGE_ATA 0x05
  80. #define PCI_CLASS_SUB_CODE_STORAGE_SATA 0x06
  81. #define PCI_CLASS_SUB_CODE_STORAGE_SAS 0x07
  82. #define PCI_CLASS_SUB_CODE_STORAGE_OTHER 0x80
  83. #define PCI_CLASS_SUB_CODE_NETWORK_ETHERNET 0x00
  84. #define PCI_CLASS_SUB_CODE_NETWORK_TOKENRING 0x01
  85. #define PCI_CLASS_SUB_CODE_NETWORK_FDDI 0x02
  86. #define PCI_CLASS_SUB_CODE_NETWORK_ATM 0x03
  87. #define PCI_CLASS_SUB_CODE_NETWORK_ISDN 0x04
  88. #define PCI_CLASS_SUB_CODE_NETWORK_WORLDFIP 0x05
  89. #define PCI_CLASS_SUB_CODE_NETWORK_PICMG 0x06
  90. #define PCI_CLASS_SUB_CODE_NETWORK_OTHER 0x80
  91. #define PCI_CLASS_SUB_CODE_DISPLAY_VGA 0x00
  92. #define PCI_CLASS_SUB_CODE_DISPLAY_XGA 0x01
  93. #define PCI_CLASS_SUB_CODE_DISPLAY_3D 0x02
  94. #define PCI_CLASS_SUB_CODE_DISPLAY_OTHER 0x80
  95. #define PCI_CLASS_SUB_CODE_MULTIMEDIA_VIDEO 0x00
  96. #define PCI_CLASS_SUB_CODE_MULTIMEDIA_AUDIO 0x01
  97. #define PCI_CLASS_SUB_CODE_MULTIMEDIA_PHONE 0x02
  98. #define PCI_CLASS_SUB_CODE_MULTIMEDIA_OTHER 0x80
  99. #define PCI_CLASS_SUB_CODE_MEMORY_RAM 0x00
  100. #define PCI_CLASS_SUB_CODE_MEMORY_FLASH 0x01
  101. #define PCI_CLASS_SUB_CODE_MEMORY_OTHER 0x80
  102. #define PCI_CLASS_SUB_CODE_BRIDGE_HOST 0x00
  103. #define PCI_CLASS_SUB_CODE_BRIDGE_ISA 0x01
  104. #define PCI_CLASS_SUB_CODE_BRIDGE_EISA 0x02
  105. #define PCI_CLASS_SUB_CODE_BRIDGE_MCA 0x03
  106. #define PCI_CLASS_SUB_CODE_BRIDGE_PCI 0x04
  107. #define PCI_CLASS_SUB_CODE_BRIDGE_PCMCIA 0x05
  108. #define PCI_CLASS_SUB_CODE_BRIDGE_NUBUS 0x06
  109. #define PCI_CLASS_SUB_CODE_BRIDGE_CARDBUS 0x07
  110. #define PCI_CLASS_SUB_CODE_BRIDGE_RACEWAY 0x08
  111. #define PCI_CLASS_SUB_CODE_BRIDGE_SEMI_PCI 0x09
  112. #define PCI_CLASS_SUB_CODE_BRIDGE_INFINIBAND 0x0A
  113. #define PCI_CLASS_SUB_CODE_BRIDGE_OTHER 0x80
  114. #define PCI_CLASS_SUB_CODE_COMM_SERIAL 0x00
  115. #define PCI_CLASS_SUB_CODE_COMM_PARALLEL 0x01
  116. #define PCI_CLASS_SUB_CODE_COMM_MULTIPORT 0x02
  117. #define PCI_CLASS_SUB_CODE_COMM_MODEM 0x03
  118. #define PCI_CLASS_SUB_CODE_COMM_GPIB 0x04
  119. #define PCI_CLASS_SUB_CODE_COMM_SMARTCARD 0x05
  120. #define PCI_CLASS_SUB_CODE_COMM_OTHER 0x80
  121. #define PCI_CLASS_SUB_CODE_PERIPHERAL_PIC 0x00
  122. #define PCI_CLASS_SUB_CODE_PERIPHERAL_DMA 0x01
  123. #define PCI_CLASS_SUB_CODE_PERIPHERAL_TIMER 0x02
  124. #define PCI_CLASS_SUB_CODE_PERIPHERAL_RTC 0x03
  125. #define PCI_CLASS_SUB_CODE_PERIPHERAL_HOTPLUG 0x04
  126. #define PCI_CLASS_SUB_CODE_PERIPHERAL_SD 0x05
  127. #define PCI_CLASS_SUB_CODE_PERIPHERAL_OTHER 0x80
  128. #define PCI_CLASS_SUB_CODE_INPUT_KEYBOARD 0x00
  129. #define PCI_CLASS_SUB_CODE_INPUT_DIGITIZER 0x01
  130. #define PCI_CLASS_SUB_CODE_INPUT_MOUSE 0x02
  131. #define PCI_CLASS_SUB_CODE_INPUT_SCANNER 0x03
  132. #define PCI_CLASS_SUB_CODE_INPUT_GAMEPORT 0x04
  133. #define PCI_CLASS_SUB_CODE_INPUT_OTHER 0x80
  134. #define PCI_CLASS_SUB_CODE_DOCKING_GENERIC 0x00
  135. #define PCI_CLASS_SUB_CODE_DOCKING_OTHER 0x80
  136. #define PCI_CLASS_SUB_CODE_PROCESSOR_386 0x00
  137. #define PCI_CLASS_SUB_CODE_PROCESSOR_486 0x01
  138. #define PCI_CLASS_SUB_CODE_PROCESSOR_PENTIUM 0x02
  139. #define PCI_CLASS_SUB_CODE_PROCESSOR_ALPHA 0x10
  140. #define PCI_CLASS_SUB_CODE_PROCESSOR_POWERPC 0x20
  141. #define PCI_CLASS_SUB_CODE_PROCESSOR_MIPS 0x30
  142. #define PCI_CLASS_SUB_CODE_PROCESSOR_COPROC 0x40
  143. #define PCI_CLASS_SUB_CODE_SERIAL_1394 0x00
  144. #define PCI_CLASS_SUB_CODE_SERIAL_ACCESSBUS 0x01
  145. #define PCI_CLASS_SUB_CODE_SERIAL_SSA 0x02
  146. #define PCI_CLASS_SUB_CODE_SERIAL_USB 0x03
  147. #define PCI_CLASS_SUB_CODE_SERIAL_FIBRECHAN 0x04
  148. #define PCI_CLASS_SUB_CODE_SERIAL_SMBUS 0x05
  149. #define PCI_CLASS_SUB_CODE_SERIAL_INFINIBAND 0x06
  150. #define PCI_CLASS_SUB_CODE_SERIAL_IPMI 0x07
  151. #define PCI_CLASS_SUB_CODE_SERIAL_SERCOS 0x08
  152. #define PCI_CLASS_SUB_CODE_SERIAL_CANBUS 0x09
  153. #define PCI_CLASS_SUB_CODE_WIRELESS_IRDA 0x00
  154. #define PCI_CLASS_SUB_CODE_WIRELESS_IR 0x01
  155. #define PCI_CLASS_SUB_CODE_WIRELESS_RF 0x10
  156. #define PCI_CLASS_SUB_CODE_WIRELESS_BLUETOOTH 0x11
  157. #define PCI_CLASS_SUB_CODE_WIRELESS_BROADBAND 0x12
  158. #define PCI_CLASS_SUB_CODE_WIRELESS_80211A 0x20
  159. #define PCI_CLASS_SUB_CODE_WIRELESS_80211B 0x21
  160. #define PCI_CLASS_SUB_CODE_WIRELESS_OTHER 0x80
  161. #define PCI_CLASS_SUB_CODE_I2O_V1_0 0x00
  162. #define PCI_CLASS_SUB_CODE_SATELLITE_TV 0x01
  163. #define PCI_CLASS_SUB_CODE_SATELLITE_AUDIO 0x02
  164. #define PCI_CLASS_SUB_CODE_SATELLITE_VOICE 0x03
  165. #define PCI_CLASS_SUB_CODE_SATELLITE_DATA 0x04
  166. #define PCI_CLASS_SUB_CODE_CRYPTO_NETWORK 0x00
  167. #define PCI_CLASS_SUB_CODE_CRYPTO_ENTERTAINMENT 0x10
  168. #define PCI_CLASS_SUB_CODE_CRYPTO_OTHER 0x80
  169. #define PCI_CLASS_SUB_CODE_DATA_DPIO 0x00
  170. #define PCI_CLASS_SUB_CODE_DATA_PERFCNTR 0x01
  171. #define PCI_CLASS_SUB_CODE_DATA_COMMSYNC 0x10
  172. #define PCI_CLASS_SUB_CODE_DATA_MGMT 0x20
  173. #define PCI_CLASS_SUB_CODE_DATA_OTHER 0x80
  174. #define PCI_CACHE_LINE_SIZE 0x0c /* 8 bits */
  175. #define PCI_LATENCY_TIMER 0x0d /* 8 bits */
  176. #define PCI_HEADER_TYPE 0x0e /* 8 bits */
  177. #define PCI_HEADER_TYPE_NORMAL 0
  178. #define PCI_HEADER_TYPE_BRIDGE 1
  179. #define PCI_HEADER_TYPE_CARDBUS 2
  180. #define PCI_BIST 0x0f /* 8 bits */
  181. #define PCI_BIST_CODE_MASK 0x0f /* Return result */
  182. #define PCI_BIST_START 0x40 /* 1 to start BIST, 2 secs or less */
  183. #define PCI_BIST_CAPABLE 0x80 /* 1 if BIST capable */
  184. /*
  185. * Base addresses specify locations in memory or I/O space.
  186. * Decoded size can be determined by writing a value of
  187. * 0xffffffff to the register, and reading it back. Only
  188. * 1 bits are decoded.
  189. */
  190. #define PCI_BASE_ADDRESS_0 0x10 /* 32 bits */
  191. #define PCI_BASE_ADDRESS_1 0x14 /* 32 bits [htype 0,1 only] */
  192. #define PCI_BASE_ADDRESS_2 0x18 /* 32 bits [htype 0 only] */
  193. #define PCI_BASE_ADDRESS_3 0x1c /* 32 bits */
  194. #define PCI_BASE_ADDRESS_4 0x20 /* 32 bits */
  195. #define PCI_BASE_ADDRESS_5 0x24 /* 32 bits */
  196. #define PCI_BASE_ADDRESS_SPACE 0x01 /* 0 = memory, 1 = I/O */
  197. #define PCI_BASE_ADDRESS_SPACE_IO 0x01
  198. #define PCI_BASE_ADDRESS_SPACE_MEMORY 0x00
  199. #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x06
  200. #define PCI_BASE_ADDRESS_MEM_TYPE_32 0x00 /* 32 bit address */
  201. #define PCI_BASE_ADDRESS_MEM_TYPE_1M 0x02 /* Below 1M [obsolete] */
  202. #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x04 /* 64 bit address */
  203. #define PCI_BASE_ADDRESS_MEM_PREFETCH 0x08 /* prefetchable? */
  204. #define PCI_BASE_ADDRESS_MEM_MASK (~0x0fULL)
  205. #define PCI_BASE_ADDRESS_IO_MASK (~0x03ULL)
  206. /* bit 1 is reserved if address_space = 1 */
  207. /* Header type 0 (normal devices) */
  208. #define PCI_CARDBUS_CIS 0x28
  209. #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
  210. #define PCI_SUBSYSTEM_ID 0x2e
  211. #define PCI_ROM_ADDRESS 0x30 /* Bits 31..11 are address, 10..1 reserved */
  212. #define PCI_ROM_ADDRESS_ENABLE 0x01
  213. #define PCI_ROM_ADDRESS_MASK (~0x7ffULL)
  214. #define PCI_CAPABILITY_LIST 0x34 /* Offset of first capability list entry */
  215. /* 0x35-0x3b are reserved */
  216. #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
  217. #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
  218. #define PCI_MIN_GNT 0x3e /* 8 bits */
  219. #define PCI_MAX_LAT 0x3f /* 8 bits */
  220. #define PCI_INTERRUPT_LINE_DISABLE 0xff
  221. /* Header type 1 (PCI-to-PCI bridges) */
  222. #define PCI_PRIMARY_BUS 0x18 /* Primary bus number */
  223. #define PCI_SECONDARY_BUS 0x19 /* Secondary bus number */
  224. #define PCI_SUBORDINATE_BUS 0x1a /* Highest bus number behind the bridge */
  225. #define PCI_SEC_LATENCY_TIMER 0x1b /* Latency timer for secondary interface */
  226. #define PCI_IO_BASE 0x1c /* I/O range behind the bridge */
  227. #define PCI_IO_LIMIT 0x1d
  228. #define PCI_IO_RANGE_TYPE_MASK 0x0f /* I/O bridging type */
  229. #define PCI_IO_RANGE_TYPE_16 0x00
  230. #define PCI_IO_RANGE_TYPE_32 0x01
  231. #define PCI_IO_RANGE_MASK ~0x0f
  232. #define PCI_SEC_STATUS 0x1e /* Secondary status register, only bit 14 used */
  233. #define PCI_MEMORY_BASE 0x20 /* Memory range behind */
  234. #define PCI_MEMORY_LIMIT 0x22
  235. #define PCI_MEMORY_RANGE_TYPE_MASK 0x0f
  236. #define PCI_MEMORY_RANGE_MASK ~0x0f
  237. #define PCI_PREF_MEMORY_BASE 0x24 /* Prefetchable memory range behind */
  238. #define PCI_PREF_MEMORY_LIMIT 0x26
  239. #define PCI_PREF_RANGE_TYPE_MASK 0x0f
  240. #define PCI_PREF_RANGE_TYPE_32 0x00
  241. #define PCI_PREF_RANGE_TYPE_64 0x01
  242. #define PCI_PREF_RANGE_MASK ~0x0f
  243. #define PCI_PREF_BASE_UPPER32 0x28 /* Upper half of prefetchable memory range */
  244. #define PCI_PREF_LIMIT_UPPER32 0x2c
  245. #define PCI_IO_BASE_UPPER16 0x30 /* Upper half of I/O addresses */
  246. #define PCI_IO_LIMIT_UPPER16 0x32
  247. /* 0x34 same as for htype 0 */
  248. /* 0x35-0x3b is reserved */
  249. #define PCI_ROM_ADDRESS1 0x38 /* Same as PCI_ROM_ADDRESS, but for htype 1 */
  250. /* 0x3c-0x3d are same as for htype 0 */
  251. #define PCI_BRIDGE_CONTROL 0x3e
  252. #define PCI_BRIDGE_CTL_PARITY 0x01 /* Enable parity detection on secondary interface */
  253. #define PCI_BRIDGE_CTL_SERR 0x02 /* The same for SERR forwarding */
  254. #define PCI_BRIDGE_CTL_NO_ISA 0x04 /* Disable bridging of ISA ports */
  255. #define PCI_BRIDGE_CTL_VGA 0x08 /* Forward VGA addresses */
  256. #define PCI_BRIDGE_CTL_MASTER_ABORT 0x20 /* Report master aborts */
  257. #define PCI_BRIDGE_CTL_BUS_RESET 0x40 /* Secondary bus reset */
  258. #define PCI_BRIDGE_CTL_FAST_BACK 0x80 /* Fast Back2Back enabled on secondary interface */
  259. /* From 440ep */
  260. #define PCI_ERREN 0x48 /* Error Enable */
  261. #define PCI_ERRSTS 0x49 /* Error Status */
  262. #define PCI_BRDGOPT1 0x4A /* PCI Bridge Options 1 */
  263. #define PCI_PLBSESR0 0x4C /* PCI PLB Slave Error Syndrome 0 */
  264. #define PCI_PLBSESR1 0x50 /* PCI PLB Slave Error Syndrome 1 */
  265. #define PCI_PLBSEAR 0x54 /* PCI PLB Slave Error Address */
  266. #define PCI_CAPID 0x58 /* Capability Identifier */
  267. #define PCI_NEXTITEMPTR 0x59 /* Next Item Pointer */
  268. #define PCI_PMC 0x5A /* Power Management Capabilities */
  269. #define PCI_PMCSR 0x5C /* Power Management Control Status */
  270. #define PCI_PMCSRBSE 0x5E /* PMCSR PCI to PCI Bridge Support Extensions */
  271. #define PCI_BRDGOPT2 0x60 /* PCI Bridge Options 2 */
  272. #define PCI_PMSCRR 0x64 /* Power Management State Change Request Re. */
  273. /* Header type 2 (CardBus bridges) */
  274. #define PCI_CB_CAPABILITY_LIST 0x14
  275. /* 0x15 reserved */
  276. #define PCI_CB_SEC_STATUS 0x16 /* Secondary status */
  277. #define PCI_CB_PRIMARY_BUS 0x18 /* PCI bus number */
  278. #define PCI_CB_CARD_BUS 0x19 /* CardBus bus number */
  279. #define PCI_CB_SUBORDINATE_BUS 0x1a /* Subordinate bus number */
  280. #define PCI_CB_LATENCY_TIMER 0x1b /* CardBus latency timer */
  281. #define PCI_CB_MEMORY_BASE_0 0x1c
  282. #define PCI_CB_MEMORY_LIMIT_0 0x20
  283. #define PCI_CB_MEMORY_BASE_1 0x24
  284. #define PCI_CB_MEMORY_LIMIT_1 0x28
  285. #define PCI_CB_IO_BASE_0 0x2c
  286. #define PCI_CB_IO_BASE_0_HI 0x2e
  287. #define PCI_CB_IO_LIMIT_0 0x30
  288. #define PCI_CB_IO_LIMIT_0_HI 0x32
  289. #define PCI_CB_IO_BASE_1 0x34
  290. #define PCI_CB_IO_BASE_1_HI 0x36
  291. #define PCI_CB_IO_LIMIT_1 0x38
  292. #define PCI_CB_IO_LIMIT_1_HI 0x3a
  293. #define PCI_CB_IO_RANGE_MASK ~0x03
  294. /* 0x3c-0x3d are same as for htype 0 */
  295. #define PCI_CB_BRIDGE_CONTROL 0x3e
  296. #define PCI_CB_BRIDGE_CTL_PARITY 0x01 /* Similar to standard bridge control register */
  297. #define PCI_CB_BRIDGE_CTL_SERR 0x02
  298. #define PCI_CB_BRIDGE_CTL_ISA 0x04
  299. #define PCI_CB_BRIDGE_CTL_VGA 0x08
  300. #define PCI_CB_BRIDGE_CTL_MASTER_ABORT 0x20
  301. #define PCI_CB_BRIDGE_CTL_CB_RESET 0x40 /* CardBus reset */
  302. #define PCI_CB_BRIDGE_CTL_16BIT_INT 0x80 /* Enable interrupt for 16-bit cards */
  303. #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM0 0x100 /* Prefetch enable for both memory regions */
  304. #define PCI_CB_BRIDGE_CTL_PREFETCH_MEM1 0x200
  305. #define PCI_CB_BRIDGE_CTL_POST_WRITES 0x400
  306. #define PCI_CB_SUBSYSTEM_VENDOR_ID 0x40
  307. #define PCI_CB_SUBSYSTEM_ID 0x42
  308. #define PCI_CB_LEGACY_MODE_BASE 0x44 /* 16-bit PC Card legacy mode base address (ExCa) */
  309. /* 0x48-0x7f reserved */
  310. /* Capability lists */
  311. #define PCI_CAP_LIST_ID 0 /* Capability ID */
  312. #define PCI_CAP_ID_PM 0x01 /* Power Management */
  313. #define PCI_CAP_ID_AGP 0x02 /* Accelerated Graphics Port */
  314. #define PCI_CAP_ID_VPD 0x03 /* Vital Product Data */
  315. #define PCI_CAP_ID_SLOTID 0x04 /* Slot Identification */
  316. #define PCI_CAP_ID_MSI 0x05 /* Message Signalled Interrupts */
  317. #define PCI_CAP_ID_CHSWP 0x06 /* CompactPCI HotSwap */
  318. #define PCI_CAP_ID_EXP 0x10 /* PCI Express */
  319. #define PCI_CAP_LIST_NEXT 1 /* Next capability in the list */
  320. #define PCI_CAP_FLAGS 2 /* Capability defined flags (16 bits) */
  321. #define PCI_CAP_SIZEOF 4
  322. /* Power Management Registers */
  323. #define PCI_PM_CAP_VER_MASK 0x0007 /* Version */
  324. #define PCI_PM_CAP_PME_CLOCK 0x0008 /* PME clock required */
  325. #define PCI_PM_CAP_AUX_POWER 0x0010 /* Auxilliary power support */
  326. #define PCI_PM_CAP_DSI 0x0020 /* Device specific initialization */
  327. #define PCI_PM_CAP_D1 0x0200 /* D1 power state support */
  328. #define PCI_PM_CAP_D2 0x0400 /* D2 power state support */
  329. #define PCI_PM_CAP_PME 0x0800 /* PME pin supported */
  330. #define PCI_PM_CTRL 4 /* PM control and status register */
  331. #define PCI_PM_CTRL_STATE_MASK 0x0003 /* Current power state (D0 to D3) */
  332. #define PCI_PM_CTRL_PME_ENABLE 0x0100 /* PME pin enable */
  333. #define PCI_PM_CTRL_DATA_SEL_MASK 0x1e00 /* Data select (??) */
  334. #define PCI_PM_CTRL_DATA_SCALE_MASK 0x6000 /* Data scale (??) */
  335. #define PCI_PM_CTRL_PME_STATUS 0x8000 /* PME pin status */
  336. #define PCI_PM_PPB_EXTENSIONS 6 /* PPB support extensions (??) */
  337. #define PCI_PM_PPB_B2_B3 0x40 /* Stop clock when in D3hot (??) */
  338. #define PCI_PM_BPCC_ENABLE 0x80 /* Bus power/clock control enable (??) */
  339. #define PCI_PM_DATA_REGISTER 7 /* (??) */
  340. #define PCI_PM_SIZEOF 8
  341. /* AGP registers */
  342. #define PCI_AGP_VERSION 2 /* BCD version number */
  343. #define PCI_AGP_RFU 3 /* Rest of capability flags */
  344. #define PCI_AGP_STATUS 4 /* Status register */
  345. #define PCI_AGP_STATUS_RQ_MASK 0xff000000 /* Maximum number of requests - 1 */
  346. #define PCI_AGP_STATUS_SBA 0x0200 /* Sideband addressing supported */
  347. #define PCI_AGP_STATUS_64BIT 0x0020 /* 64-bit addressing supported */
  348. #define PCI_AGP_STATUS_FW 0x0010 /* FW transfers supported */
  349. #define PCI_AGP_STATUS_RATE4 0x0004 /* 4x transfer rate supported */
  350. #define PCI_AGP_STATUS_RATE2 0x0002 /* 2x transfer rate supported */
  351. #define PCI_AGP_STATUS_RATE1 0x0001 /* 1x transfer rate supported */
  352. #define PCI_AGP_COMMAND 8 /* Control register */
  353. #define PCI_AGP_COMMAND_RQ_MASK 0xff000000 /* Master: Maximum number of requests */
  354. #define PCI_AGP_COMMAND_SBA 0x0200 /* Sideband addressing enabled */
  355. #define PCI_AGP_COMMAND_AGP 0x0100 /* Allow processing of AGP transactions */
  356. #define PCI_AGP_COMMAND_64BIT 0x0020 /* Allow processing of 64-bit addresses */
  357. #define PCI_AGP_COMMAND_FW 0x0010 /* Force FW transfers */
  358. #define PCI_AGP_COMMAND_RATE4 0x0004 /* Use 4x rate */
  359. #define PCI_AGP_COMMAND_RATE2 0x0002 /* Use 4x rate */
  360. #define PCI_AGP_COMMAND_RATE1 0x0001 /* Use 4x rate */
  361. #define PCI_AGP_SIZEOF 12
  362. /* PCI-X registers */
  363. #define PCI_X_CMD_DPERR_E 0x0001 /* Data Parity Error Recovery Enable */
  364. #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
  365. #define PCI_X_CMD_MAX_READ 0x0000 /* Max Memory Read Byte Count */
  366. #define PCI_X_CMD_MAX_SPLIT 0x0030 /* Max Outstanding Split Transactions */
  367. #define PCI_X_CMD_VERSION(x) (((x) >> 12) & 3) /* Version */
  368. /* Slot Identification */
  369. #define PCI_SID_ESR 2 /* Expansion Slot Register */
  370. #define PCI_SID_ESR_NSLOTS 0x1f /* Number of expansion slots available */
  371. #define PCI_SID_ESR_FIC 0x20 /* First In Chassis Flag */
  372. #define PCI_SID_CHASSIS_NR 3 /* Chassis Number */
  373. /* Message Signalled Interrupts registers */
  374. #define PCI_MSI_FLAGS 2 /* Various flags */
  375. #define PCI_MSI_FLAGS_64BIT 0x80 /* 64-bit addresses allowed */
  376. #define PCI_MSI_FLAGS_QSIZE 0x70 /* Message queue size configured */
  377. #define PCI_MSI_FLAGS_QMASK 0x0e /* Maximum queue size available */
  378. #define PCI_MSI_FLAGS_ENABLE 0x01 /* MSI feature enabled */
  379. #define PCI_MSI_RFU 3 /* Rest of capability flags */
  380. #define PCI_MSI_ADDRESS_LO 4 /* Lower 32 bits */
  381. #define PCI_MSI_ADDRESS_HI 8 /* Upper 32 bits (if PCI_MSI_FLAGS_64BIT set) */
  382. #define PCI_MSI_DATA_32 8 /* 16 bits of data for 32-bit devices */
  383. #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
  384. #define PCI_MAX_PCI_DEVICES 32
  385. #define PCI_MAX_PCI_FUNCTIONS 8
  386. #define PCI_FIND_CAP_TTL 0x48
  387. #define CAP_START_POS 0x40
  388. /* Extended Capabilities (PCI-X 2.0 and Express) */
  389. #define PCI_EXT_CAP_ID(header) (header & 0x0000ffff)
  390. #define PCI_EXT_CAP_VER(header) ((header >> 16) & 0xf)
  391. #define PCI_EXT_CAP_NEXT(header) ((header >> 20) & 0xffc)
  392. #define PCI_EXT_CAP_ID_ERR 0x01 /* Advanced Error Reporting */
  393. #define PCI_EXT_CAP_ID_VC 0x02 /* Virtual Channel Capability */
  394. #define PCI_EXT_CAP_ID_DSN 0x03 /* Device Serial Number */
  395. #define PCI_EXT_CAP_ID_PWR 0x04 /* Power Budgeting */
  396. #define PCI_EXT_CAP_ID_RCLD 0x05 /* Root Complex Link Declaration */
  397. #define PCI_EXT_CAP_ID_RCILC 0x06 /* Root Complex Internal Link Control */
  398. #define PCI_EXT_CAP_ID_RCEC 0x07 /* Root Complex Event Collector */
  399. #define PCI_EXT_CAP_ID_MFVC 0x08 /* Multi-Function VC Capability */
  400. #define PCI_EXT_CAP_ID_VC9 0x09 /* same as _VC */
  401. #define PCI_EXT_CAP_ID_RCRB 0x0A /* Root Complex RB? */
  402. #define PCI_EXT_CAP_ID_VNDR 0x0B /* Vendor-Specific */
  403. #define PCI_EXT_CAP_ID_CAC 0x0C /* Config Access - obsolete */
  404. #define PCI_EXT_CAP_ID_ACS 0x0D /* Access Control Services */
  405. #define PCI_EXT_CAP_ID_ARI 0x0E /* Alternate Routing ID */
  406. #define PCI_EXT_CAP_ID_ATS 0x0F /* Address Translation Services */
  407. #define PCI_EXT_CAP_ID_SRIOV 0x10 /* Single Root I/O Virtualization */
  408. #define PCI_EXT_CAP_ID_MRIOV 0x11 /* Multi Root I/O Virtualization */
  409. #define PCI_EXT_CAP_ID_MCAST 0x12 /* Multicast */
  410. #define PCI_EXT_CAP_ID_PRI 0x13 /* Page Request Interface */
  411. #define PCI_EXT_CAP_ID_AMD_XXX 0x14 /* Reserved for AMD */
  412. #define PCI_EXT_CAP_ID_REBAR 0x15 /* Resizable BAR */
  413. #define PCI_EXT_CAP_ID_DPA 0x16 /* Dynamic Power Allocation */
  414. #define PCI_EXT_CAP_ID_TPH 0x17 /* TPH Requester */
  415. #define PCI_EXT_CAP_ID_LTR 0x18 /* Latency Tolerance Reporting */
  416. #define PCI_EXT_CAP_ID_SECPCI 0x19 /* Secondary PCIe Capability */
  417. #define PCI_EXT_CAP_ID_PMUX 0x1A /* Protocol Multiplexing */
  418. #define PCI_EXT_CAP_ID_PASID 0x1B /* Process Address Space ID */
  419. /* Include the ID list */
  420. #include <pci_ids.h>
  421. #ifndef __ASSEMBLY__
  422. #ifdef CONFIG_SYS_PCI_64BIT
  423. typedef u64 pci_addr_t;
  424. typedef u64 pci_size_t;
  425. #else
  426. typedef u32 pci_addr_t;
  427. typedef u32 pci_size_t;
  428. #endif
  429. struct pci_region {
  430. pci_addr_t bus_start; /* Start on the bus */
  431. phys_addr_t phys_start; /* Start in physical address space */
  432. pci_size_t size; /* Size */
  433. unsigned long flags; /* Resource flags */
  434. pci_addr_t bus_lower;
  435. };
  436. #define PCI_REGION_MEM 0x00000000 /* PCI memory space */
  437. #define PCI_REGION_IO 0x00000001 /* PCI IO space */
  438. #define PCI_REGION_TYPE 0x00000001
  439. #define PCI_REGION_PREFETCH 0x00000008 /* prefetchable PCI memory */
  440. #define PCI_REGION_SYS_MEMORY 0x00000100 /* System memory */
  441. #define PCI_REGION_RO 0x00000200 /* Read-only memory */
  442. static inline void pci_set_region(struct pci_region *reg,
  443. pci_addr_t bus_start,
  444. phys_addr_t phys_start,
  445. pci_size_t size,
  446. unsigned long flags) {
  447. reg->bus_start = bus_start;
  448. reg->phys_start = phys_start;
  449. reg->size = size;
  450. reg->flags = flags;
  451. }
  452. typedef int pci_dev_t;
  453. #define PCI_BUS(d) (((d) >> 16) & 0xff)
  454. #define PCI_DEV(d) (((d) >> 11) & 0x1f)
  455. #define PCI_FUNC(d) (((d) >> 8) & 0x7)
  456. #define PCI_DEVFN(d, f) ((d) << 11 | (f) << 8)
  457. #define PCI_MASK_BUS(bdf) ((bdf) & 0xffff)
  458. #define PCI_ADD_BUS(bus, devfn) (((bus) << 16) | (devfn))
  459. #define PCI_BDF(b, d, f) ((b) << 16 | PCI_DEVFN(d, f))
  460. #define PCI_VENDEV(v, d) (((v) << 16) | (d))
  461. #define PCI_ANY_ID (~0)
  462. struct pci_device_id {
  463. unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
  464. unsigned int subvendor, subdevice; /* Subsystem ID's or PCI_ANY_ID */
  465. unsigned int class, class_mask; /* (class,subclass,prog-if) triplet */
  466. unsigned long driver_data; /* Data private to the driver */
  467. };
  468. struct pci_controller;
  469. struct pci_config_table {
  470. unsigned int vendor, device; /* Vendor and device ID or PCI_ANY_ID */
  471. unsigned int class; /* Class ID, or PCI_ANY_ID */
  472. unsigned int bus; /* Bus number, or PCI_ANY_ID */
  473. unsigned int dev; /* Device number, or PCI_ANY_ID */
  474. unsigned int func; /* Function number, or PCI_ANY_ID */
  475. void (*config_device)(struct pci_controller* hose, pci_dev_t dev,
  476. struct pci_config_table *);
  477. unsigned long priv[3];
  478. };
  479. extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
  480. struct pci_config_table *);
  481. extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
  482. struct pci_config_table *);
  483. #define MAX_PCI_REGIONS 7
  484. #define INDIRECT_TYPE_NO_PCIE_LINK 1
  485. /*
  486. * Structure of a PCI controller (host bridge)
  487. *
  488. * With driver model this is dev_get_uclass_priv(bus)
  489. */
  490. struct pci_controller {
  491. #ifdef CONFIG_DM_PCI
  492. struct udevice *bus;
  493. struct udevice *ctlr;
  494. #else
  495. struct pci_controller *next;
  496. #endif
  497. int first_busno;
  498. int last_busno;
  499. volatile unsigned int *cfg_addr;
  500. volatile unsigned char *cfg_data;
  501. int indirect_type;
  502. /*
  503. * TODO(sjg@chromium.org): With driver model we use struct
  504. * pci_controller for both the controller and any bridge devices
  505. * attached to it. But there is only one region list and it is in the
  506. * top-level controller.
  507. *
  508. * This could be changed so that struct pci_controller is only used
  509. * for PCI controllers and a separate UCLASS (or perhaps
  510. * UCLASS_PCI_GENERIC) is used for bridges.
  511. */
  512. struct pci_region regions[MAX_PCI_REGIONS];
  513. int region_count;
  514. struct pci_config_table *config_table;
  515. void (*fixup_irq)(struct pci_controller *, pci_dev_t);
  516. #ifndef CONFIG_DM_PCI
  517. /* Low-level architecture-dependent routines */
  518. int (*read_byte)(struct pci_controller*, pci_dev_t, int where, u8 *);
  519. int (*read_word)(struct pci_controller*, pci_dev_t, int where, u16 *);
  520. int (*read_dword)(struct pci_controller*, pci_dev_t, int where, u32 *);
  521. int (*write_byte)(struct pci_controller*, pci_dev_t, int where, u8);
  522. int (*write_word)(struct pci_controller*, pci_dev_t, int where, u16);
  523. int (*write_dword)(struct pci_controller*, pci_dev_t, int where, u32);
  524. #endif
  525. /* Used by auto config */
  526. struct pci_region *pci_mem, *pci_io, *pci_prefetch;
  527. #ifndef CONFIG_DM_PCI
  528. int current_busno;
  529. void *priv_data;
  530. #endif
  531. };
  532. #ifndef CONFIG_DM_PCI
  533. static inline void pci_set_ops(struct pci_controller *hose,
  534. int (*read_byte)(struct pci_controller*,
  535. pci_dev_t, int where, u8 *),
  536. int (*read_word)(struct pci_controller*,
  537. pci_dev_t, int where, u16 *),
  538. int (*read_dword)(struct pci_controller*,
  539. pci_dev_t, int where, u32 *),
  540. int (*write_byte)(struct pci_controller*,
  541. pci_dev_t, int where, u8),
  542. int (*write_word)(struct pci_controller*,
  543. pci_dev_t, int where, u16),
  544. int (*write_dword)(struct pci_controller*,
  545. pci_dev_t, int where, u32)) {
  546. hose->read_byte = read_byte;
  547. hose->read_word = read_word;
  548. hose->read_dword = read_dword;
  549. hose->write_byte = write_byte;
  550. hose->write_word = write_word;
  551. hose->write_dword = write_dword;
  552. }
  553. #endif
  554. #ifdef CONFIG_PCI_INDIRECT_BRIDGE
  555. extern void pci_setup_indirect(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data);
  556. #endif
  557. #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
  558. extern phys_addr_t pci_hose_bus_to_phys(struct pci_controller* hose,
  559. pci_addr_t addr, unsigned long flags);
  560. extern pci_addr_t pci_hose_phys_to_bus(struct pci_controller* hose,
  561. phys_addr_t addr, unsigned long flags);
  562. #define pci_phys_to_bus(dev, addr, flags) \
  563. pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
  564. #define pci_bus_to_phys(dev, addr, flags) \
  565. pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), (addr), (flags))
  566. #define pci_virt_to_bus(dev, addr, flags) \
  567. pci_hose_phys_to_bus(pci_bus_to_hose(PCI_BUS(dev)), \
  568. (virt_to_phys(addr)), (flags))
  569. #define pci_bus_to_virt(dev, addr, flags, len, map_flags) \
  570. map_physmem(pci_hose_bus_to_phys(pci_bus_to_hose(PCI_BUS(dev)), \
  571. (addr), (flags)), \
  572. (len), (map_flags))
  573. #define pci_phys_to_mem(dev, addr) \
  574. pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
  575. #define pci_mem_to_phys(dev, addr) \
  576. pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
  577. #define pci_phys_to_io(dev, addr) pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
  578. #define pci_io_to_phys(dev, addr) pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
  579. #define pci_virt_to_mem(dev, addr) \
  580. pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
  581. #define pci_mem_to_virt(dev, addr, len, map_flags) \
  582. pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
  583. #define pci_virt_to_io(dev, addr) \
  584. pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
  585. #define pci_io_to_virt(dev, addr, len, map_flags) \
  586. pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
  587. /* For driver model these are defined in macros in pci_compat.c */
  588. extern int pci_hose_read_config_byte(struct pci_controller *hose,
  589. pci_dev_t dev, int where, u8 *val);
  590. extern int pci_hose_read_config_word(struct pci_controller *hose,
  591. pci_dev_t dev, int where, u16 *val);
  592. extern int pci_hose_read_config_dword(struct pci_controller *hose,
  593. pci_dev_t dev, int where, u32 *val);
  594. extern int pci_hose_write_config_byte(struct pci_controller *hose,
  595. pci_dev_t dev, int where, u8 val);
  596. extern int pci_hose_write_config_word(struct pci_controller *hose,
  597. pci_dev_t dev, int where, u16 val);
  598. extern int pci_hose_write_config_dword(struct pci_controller *hose,
  599. pci_dev_t dev, int where, u32 val);
  600. #endif
  601. #ifndef CONFIG_DM_PCI
  602. extern int pci_read_config_byte(pci_dev_t dev, int where, u8 *val);
  603. extern int pci_read_config_word(pci_dev_t dev, int where, u16 *val);
  604. extern int pci_read_config_dword(pci_dev_t dev, int where, u32 *val);
  605. extern int pci_write_config_byte(pci_dev_t dev, int where, u8 val);
  606. extern int pci_write_config_word(pci_dev_t dev, int where, u16 val);
  607. extern int pci_write_config_dword(pci_dev_t dev, int where, u32 val);
  608. #endif
  609. void pciauto_region_init(struct pci_region *res);
  610. void pciauto_region_align(struct pci_region *res, pci_size_t size);
  611. void pciauto_config_init(struct pci_controller *hose);
  612. int pciauto_region_allocate(struct pci_region *res, pci_size_t size,
  613. pci_addr_t *bar);
  614. #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
  615. extern int pci_hose_read_config_byte_via_dword(struct pci_controller *hose,
  616. pci_dev_t dev, int where, u8 *val);
  617. extern int pci_hose_read_config_word_via_dword(struct pci_controller *hose,
  618. pci_dev_t dev, int where, u16 *val);
  619. extern int pci_hose_write_config_byte_via_dword(struct pci_controller *hose,
  620. pci_dev_t dev, int where, u8 val);
  621. extern int pci_hose_write_config_word_via_dword(struct pci_controller *hose,
  622. pci_dev_t dev, int where, u16 val);
  623. extern void *pci_map_bar(pci_dev_t pdev, int bar, int flags);
  624. extern void pci_register_hose(struct pci_controller* hose);
  625. extern struct pci_controller* pci_bus_to_hose(int bus);
  626. extern struct pci_controller *find_hose_by_cfg_addr(void *cfg_addr);
  627. extern struct pci_controller *pci_get_hose_head(void);
  628. extern int pci_skip_dev(struct pci_controller *hose, pci_dev_t dev);
  629. extern int pci_hose_scan(struct pci_controller *hose);
  630. extern int pci_hose_scan_bus(struct pci_controller *hose, int bus);
  631. extern void pciauto_setup_device(struct pci_controller *hose,
  632. pci_dev_t dev, int bars_num,
  633. struct pci_region *mem,
  634. struct pci_region *prefetch,
  635. struct pci_region *io);
  636. extern void pciauto_prescan_setup_bridge(struct pci_controller *hose,
  637. pci_dev_t dev, int sub_bus);
  638. extern void pciauto_postscan_setup_bridge(struct pci_controller *hose,
  639. pci_dev_t dev, int sub_bus);
  640. extern int pciauto_config_device(struct pci_controller *hose, pci_dev_t dev);
  641. extern pci_dev_t pci_find_device (unsigned int vendor, unsigned int device, int index);
  642. extern pci_dev_t pci_find_devices (struct pci_device_id *ids, int index);
  643. pci_dev_t pci_find_class(unsigned int find_class, int index);
  644. extern int pci_hose_config_device(struct pci_controller *hose,
  645. pci_dev_t dev,
  646. unsigned long io,
  647. pci_addr_t mem,
  648. unsigned long command);
  649. extern int pci_hose_find_capability(struct pci_controller *hose, pci_dev_t dev,
  650. int cap);
  651. extern int pci_hose_find_cap_start(struct pci_controller *hose, pci_dev_t dev,
  652. u8 hdr_type);
  653. extern int pci_find_cap(struct pci_controller *hose, pci_dev_t dev, int pos,
  654. int cap);
  655. int pci_find_next_ext_capability(struct pci_controller *hose,
  656. pci_dev_t dev, int start, int cap);
  657. int pci_hose_find_ext_capability(struct pci_controller *hose,
  658. pci_dev_t dev, int cap);
  659. #ifdef CONFIG_PCI_FIXUP_DEV
  660. extern void board_pci_fixup_dev(struct pci_controller *hose, pci_dev_t dev,
  661. unsigned short vendor,
  662. unsigned short device,
  663. unsigned short class);
  664. #endif
  665. #endif /* !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT) */
  666. const char * pci_class_str(u8 class);
  667. int pci_last_busno(void);
  668. #ifdef CONFIG_MPC85xx
  669. extern void pci_mpc85xx_init (struct pci_controller *hose);
  670. #endif
  671. #ifdef CONFIG_PCIE_IMX
  672. extern void imx_pcie_remove(void);
  673. #endif
  674. #if !defined(CONFIG_DM_PCI) || defined(CONFIG_DM_PCI_COMPAT)
  675. /**
  676. * pci_write_bar32() - Write the address of a BAR including control bits
  677. *
  678. * This writes a raw address (with control bits) to a bar. This can be used
  679. * with devices which require hard-coded addresses, not part of the normal
  680. * PCI enumeration process.
  681. *
  682. * @hose: PCI hose to use
  683. * @dev: PCI device to update
  684. * @barnum: BAR number (0-5)
  685. * @addr: BAR address with control bits
  686. */
  687. void pci_write_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum,
  688. u32 addr);
  689. /**
  690. * pci_read_bar32() - read the address of a bar
  691. *
  692. * @hose: PCI hose to use
  693. * @dev: PCI device to inspect
  694. * @barnum: BAR number (0-5)
  695. * @return address of the bar, masking out any control bits
  696. * */
  697. u32 pci_read_bar32(struct pci_controller *hose, pci_dev_t dev, int barnum);
  698. /**
  699. * pci_hose_find_devices() - Find devices by vendor/device ID
  700. *
  701. * @hose: PCI hose to search
  702. * @busnum: Bus number to search
  703. * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
  704. * @indexp: Pointer to device index to find. To find the first matching
  705. * device, pass 0; to find the second, pass 1, etc. This
  706. * parameter is decremented for each non-matching device so
  707. * can be called repeatedly.
  708. */
  709. pci_dev_t pci_hose_find_devices(struct pci_controller *hose, int busnum,
  710. struct pci_device_id *ids, int *indexp);
  711. #endif /* !CONFIG_DM_PCI || CONFIG_DM_PCI_COMPAT */
  712. /* Access sizes for PCI reads and writes */
  713. enum pci_size_t {
  714. PCI_SIZE_8,
  715. PCI_SIZE_16,
  716. PCI_SIZE_32,
  717. };
  718. struct udevice;
  719. #ifdef CONFIG_DM_PCI
  720. /**
  721. * struct pci_child_platdata - information stored about each PCI device
  722. *
  723. * Every device on a PCI bus has this per-child data.
  724. *
  725. * It can be accessed using dev_get_parent_priv(dev) if dev->parent is a
  726. * PCI bus (i.e. UCLASS_PCI)
  727. *
  728. * @devfn: Encoded device and function index - see PCI_DEVFN()
  729. * @vendor: PCI vendor ID (see pci_ids.h)
  730. * @device: PCI device ID (see pci_ids.h)
  731. * @class: PCI class, 3 bytes: (base, sub, prog-if)
  732. */
  733. struct pci_child_platdata {
  734. int devfn;
  735. unsigned short vendor;
  736. unsigned short device;
  737. unsigned int class;
  738. };
  739. /* PCI bus operations */
  740. struct dm_pci_ops {
  741. /**
  742. * read_config() - Read a PCI configuration value
  743. *
  744. * PCI buses must support reading and writing configuration values
  745. * so that the bus can be scanned and its devices configured.
  746. *
  747. * Normally PCI_BUS(@bdf) is the same as @bus->seq, but not always.
  748. * If bridges exist it is possible to use the top-level bus to
  749. * access a sub-bus. In that case @bus will be the top-level bus
  750. * and PCI_BUS(bdf) will be a different (higher) value
  751. *
  752. * @bus: Bus to read from
  753. * @bdf: Bus, device and function to read
  754. * @offset: Byte offset within the device's configuration space
  755. * @valuep: Place to put the returned value
  756. * @size: Access size
  757. * @return 0 if OK, -ve on error
  758. */
  759. int (*read_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
  760. ulong *valuep, enum pci_size_t size);
  761. /**
  762. * write_config() - Write a PCI configuration value
  763. *
  764. * @bus: Bus to write to
  765. * @bdf: Bus, device and function to write
  766. * @offset: Byte offset within the device's configuration space
  767. * @value: Value to write
  768. * @size: Access size
  769. * @return 0 if OK, -ve on error
  770. */
  771. int (*write_config)(struct udevice *bus, pci_dev_t bdf, uint offset,
  772. ulong value, enum pci_size_t size);
  773. };
  774. /* Get access to a PCI bus' operations */
  775. #define pci_get_ops(dev) ((struct dm_pci_ops *)(dev)->driver->ops)
  776. /**
  777. * dm_pci_get_bdf() - Get the BDF value for a device
  778. *
  779. * @dev: Device to check
  780. * @return bus/device/function value (see PCI_BDF())
  781. */
  782. pci_dev_t dm_pci_get_bdf(struct udevice *dev);
  783. /**
  784. * pci_bind_bus_devices() - scan a PCI bus and bind devices
  785. *
  786. * Scan a PCI bus looking for devices. Bind each one that is found. If
  787. * devices are already bound that match the scanned devices, just update the
  788. * child data so that the device can be used correctly (this happens when
  789. * the device tree describes devices we expect to see on the bus).
  790. *
  791. * Devices that are bound in this way will use a generic PCI driver which
  792. * does nothing. The device can still be accessed but will not provide any
  793. * driver interface.
  794. *
  795. * @bus: Bus containing devices to bind
  796. * @return 0 if OK, -ve on error
  797. */
  798. int pci_bind_bus_devices(struct udevice *bus);
  799. /**
  800. * pci_auto_config_devices() - configure bus devices ready for use
  801. *
  802. * This works through all devices on a bus by scanning the driver model
  803. * data structures (normally these have been set up by pci_bind_bus_devices()
  804. * earlier).
  805. *
  806. * Space is allocated for each PCI base address register (BAR) so that the
  807. * devices are mapped into memory and I/O space ready for use.
  808. *
  809. * @bus: Bus containing devices to bind
  810. * @return 0 if OK, -ve on error
  811. */
  812. int pci_auto_config_devices(struct udevice *bus);
  813. /**
  814. * dm_pci_bus_find_bdf() - Find a device given its PCI bus address
  815. *
  816. * @bdf: PCI device address: bus, device and function -see PCI_BDF()
  817. * @devp: Returns the device for this address, if found
  818. * @return 0 if OK, -ENODEV if not found
  819. */
  820. int dm_pci_bus_find_bdf(pci_dev_t bdf, struct udevice **devp);
  821. /**
  822. * pci_bus_find_devfn() - Find a device on a bus
  823. *
  824. * @find_devfn: PCI device address (device and function only)
  825. * @devp: Returns the device for this address, if found
  826. * @return 0 if OK, -ENODEV if not found
  827. */
  828. int pci_bus_find_devfn(struct udevice *bus, pci_dev_t find_devfn,
  829. struct udevice **devp);
  830. /**
  831. * pci_find_first_device() - return the first available PCI device
  832. *
  833. * This function and pci_find_first_device() allow iteration through all
  834. * available PCI devices on all buses. Assuming there are any, this will
  835. * return the first one.
  836. *
  837. * @devp: Set to the first available device, or NULL if no more are left
  838. * or we got an error
  839. * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
  840. */
  841. int pci_find_first_device(struct udevice **devp);
  842. /**
  843. * pci_find_next_device() - return the next available PCI device
  844. *
  845. * Finds the next available PCI device after the one supplied, or sets @devp
  846. * to NULL if there are no more.
  847. *
  848. * @devp: On entry, the last device returned. Set to the next available
  849. * device, or NULL if no more are left or we got an error
  850. * @return 0 if all is OK, -ve on error (e.g. a bus/bridge failed to probe)
  851. */
  852. int pci_find_next_device(struct udevice **devp);
  853. /**
  854. * pci_get_ff() - Returns a mask for the given access size
  855. *
  856. * @size: Access size
  857. * @return 0xff for PCI_SIZE_8, 0xffff for PCI_SIZE_16, 0xffffffff for
  858. * PCI_SIZE_32
  859. */
  860. int pci_get_ff(enum pci_size_t size);
  861. /**
  862. * pci_bus_find_devices () - Find devices on a bus
  863. *
  864. * @bus: Bus to search
  865. * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
  866. * @indexp: Pointer to device index to find. To find the first matching
  867. * device, pass 0; to find the second, pass 1, etc. This
  868. * parameter is decremented for each non-matching device so
  869. * can be called repeatedly.
  870. * @devp: Returns matching device if found
  871. * @return 0 if found, -ENODEV if not
  872. */
  873. int pci_bus_find_devices(struct udevice *bus, struct pci_device_id *ids,
  874. int *indexp, struct udevice **devp);
  875. /**
  876. * pci_find_device_id() - Find a device on any bus
  877. *
  878. * @ids: PCI vendor/device IDs to look for, terminated by 0, 0 record
  879. * @index: Index number of device to find, 0 for the first match, 1 for
  880. * the second, etc.
  881. * @devp: Returns matching device if found
  882. * @return 0 if found, -ENODEV if not
  883. */
  884. int pci_find_device_id(struct pci_device_id *ids, int index,
  885. struct udevice **devp);
  886. /**
  887. * dm_pci_hose_probe_bus() - probe a subordinate bus, scanning it for devices
  888. *
  889. * This probes the given bus which causes it to be scanned for devices. The
  890. * devices will be bound but not probed.
  891. *
  892. * @hose specifies the PCI hose that will be used for the scan. This is
  893. * always a top-level bus with uclass UCLASS_PCI. The bus to scan is
  894. * in @bdf, and is a subordinate bus reachable from @hose.
  895. *
  896. * @hose: PCI hose to scan
  897. * @bdf: PCI bus address to scan (PCI_BUS(bdf) is the bus number)
  898. * @return 0 if OK, -ve on error
  899. */
  900. int dm_pci_hose_probe_bus(struct udevice *bus);
  901. /**
  902. * pci_bus_read_config() - Read a configuration value from a device
  903. *
  904. * TODO(sjg@chromium.org): We should be able to pass just a device and have
  905. * it do the right thing. It would be good to have that function also.
  906. *
  907. * @bus: Bus to read from
  908. * @bdf: PCI device address: bus, device and function -see PCI_BDF()
  909. * @offset: Register offset to read
  910. * @valuep: Place to put the returned value
  911. * @size: Access size
  912. * @return 0 if OK, -ve on error
  913. */
  914. int pci_bus_read_config(struct udevice *bus, pci_dev_t bdf, int offset,
  915. unsigned long *valuep, enum pci_size_t size);
  916. /**
  917. * pci_bus_write_config() - Write a configuration value to a device
  918. *
  919. * @bus: Bus to write from
  920. * @bdf: PCI device address: bus, device and function -see PCI_BDF()
  921. * @offset: Register offset to write
  922. * @value: Value to write
  923. * @size: Access size
  924. * @return 0 if OK, -ve on error
  925. */
  926. int pci_bus_write_config(struct udevice *bus, pci_dev_t bdf, int offset,
  927. unsigned long value, enum pci_size_t size);
  928. /**
  929. * pci_bus_clrset_config32() - Update a configuration value for a device
  930. *
  931. * The register at @offset is updated to (oldvalue & ~clr) | set.
  932. *
  933. * @bus: Bus to access
  934. * @bdf: PCI device address: bus, device and function -see PCI_BDF()
  935. * @offset: Register offset to update
  936. * @clr: Bits to clear
  937. * @set: Bits to set
  938. * @return 0 if OK, -ve on error
  939. */
  940. int pci_bus_clrset_config32(struct udevice *bus, pci_dev_t bdf, int offset,
  941. u32 clr, u32 set);
  942. /**
  943. * Driver model PCI config access functions. Use these in preference to others
  944. * when you have a valid device
  945. */
  946. int dm_pci_read_config(struct udevice *dev, int offset, unsigned long *valuep,
  947. enum pci_size_t size);
  948. int dm_pci_read_config8(struct udevice *dev, int offset, u8 *valuep);
  949. int dm_pci_read_config16(struct udevice *dev, int offset, u16 *valuep);
  950. int dm_pci_read_config32(struct udevice *dev, int offset, u32 *valuep);
  951. int dm_pci_write_config(struct udevice *dev, int offset, unsigned long value,
  952. enum pci_size_t size);
  953. int dm_pci_write_config8(struct udevice *dev, int offset, u8 value);
  954. int dm_pci_write_config16(struct udevice *dev, int offset, u16 value);
  955. int dm_pci_write_config32(struct udevice *dev, int offset, u32 value);
  956. /**
  957. * These permit convenient read/modify/write on PCI configuration. The
  958. * register is updated to (oldvalue & ~clr) | set.
  959. */
  960. int dm_pci_clrset_config8(struct udevice *dev, int offset, u32 clr, u32 set);
  961. int dm_pci_clrset_config16(struct udevice *dev, int offset, u32 clr, u32 set);
  962. int dm_pci_clrset_config32(struct udevice *dev, int offset, u32 clr, u32 set);
  963. /*
  964. * The following functions provide access to the above without needing the
  965. * size parameter. We are trying to encourage the use of the 8/16/32-style
  966. * functions, rather than byte/word/dword. But both are supported.
  967. */
  968. int pci_write_config32(pci_dev_t pcidev, int offset, u32 value);
  969. int pci_write_config16(pci_dev_t pcidev, int offset, u16 value);
  970. int pci_write_config8(pci_dev_t pcidev, int offset, u8 value);
  971. int pci_read_config32(pci_dev_t pcidev, int offset, u32 *valuep);
  972. int pci_read_config16(pci_dev_t pcidev, int offset, u16 *valuep);
  973. int pci_read_config8(pci_dev_t pcidev, int offset, u8 *valuep);
  974. /**
  975. * pci_generic_mmap_write_config() - Generic helper for writing to
  976. * memory-mapped PCI configuration space.
  977. * @bus: Pointer to the PCI bus
  978. * @addr_f: Callback for calculating the config space address
  979. * @bdf: Identifies the PCI device to access
  980. * @offset: The offset into the device's configuration space
  981. * @value: The value to write
  982. * @size: Indicates the size of access to perform
  983. *
  984. * Write the value @value of size @size from offset @offset within the
  985. * configuration space of the device identified by the bus, device & function
  986. * numbers in @bdf on the PCI bus @bus. The callback function @addr_f is
  987. * responsible for calculating the CPU address of the respective configuration
  988. * space offset.
  989. *
  990. * Return: 0 on success, else -EINVAL
  991. */
  992. int pci_generic_mmap_write_config(
  993. struct udevice *bus,
  994. int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
  995. pci_dev_t bdf,
  996. uint offset,
  997. ulong value,
  998. enum pci_size_t size);
  999. /**
  1000. * pci_generic_mmap_read_config() - Generic helper for reading from
  1001. * memory-mapped PCI configuration space.
  1002. * @bus: Pointer to the PCI bus
  1003. * @addr_f: Callback for calculating the config space address
  1004. * @bdf: Identifies the PCI device to access
  1005. * @offset: The offset into the device's configuration space
  1006. * @valuep: A pointer at which to store the read value
  1007. * @size: Indicates the size of access to perform
  1008. *
  1009. * Read a value of size @size from offset @offset within the configuration
  1010. * space of the device identified by the bus, device & function numbers in @bdf
  1011. * on the PCI bus @bus. The callback function @addr_f is responsible for
  1012. * calculating the CPU address of the respective configuration space offset.
  1013. *
  1014. * Return: 0 on success, else -EINVAL
  1015. */
  1016. int pci_generic_mmap_read_config(
  1017. struct udevice *bus,
  1018. int (*addr_f)(struct udevice *bus, pci_dev_t bdf, uint offset, void **addrp),
  1019. pci_dev_t bdf,
  1020. uint offset,
  1021. ulong *valuep,
  1022. enum pci_size_t size);
  1023. #ifdef CONFIG_DM_PCI_COMPAT
  1024. /* Compatibility with old naming */
  1025. static inline int pci_write_config_dword(pci_dev_t pcidev, int offset,
  1026. u32 value)
  1027. {
  1028. return pci_write_config32(pcidev, offset, value);
  1029. }
  1030. /* Compatibility with old naming */
  1031. static inline int pci_write_config_word(pci_dev_t pcidev, int offset,
  1032. u16 value)
  1033. {
  1034. return pci_write_config16(pcidev, offset, value);
  1035. }
  1036. /* Compatibility with old naming */
  1037. static inline int pci_write_config_byte(pci_dev_t pcidev, int offset,
  1038. u8 value)
  1039. {
  1040. return pci_write_config8(pcidev, offset, value);
  1041. }
  1042. /* Compatibility with old naming */
  1043. static inline int pci_read_config_dword(pci_dev_t pcidev, int offset,
  1044. u32 *valuep)
  1045. {
  1046. return pci_read_config32(pcidev, offset, valuep);
  1047. }
  1048. /* Compatibility with old naming */
  1049. static inline int pci_read_config_word(pci_dev_t pcidev, int offset,
  1050. u16 *valuep)
  1051. {
  1052. return pci_read_config16(pcidev, offset, valuep);
  1053. }
  1054. /* Compatibility with old naming */
  1055. static inline int pci_read_config_byte(pci_dev_t pcidev, int offset,
  1056. u8 *valuep)
  1057. {
  1058. return pci_read_config8(pcidev, offset, valuep);
  1059. }
  1060. #endif /* CONFIG_DM_PCI_COMPAT */
  1061. /**
  1062. * dm_pciauto_config_device() - configure a device ready for use
  1063. *
  1064. * Space is allocated for each PCI base address register (BAR) so that the
  1065. * devices are mapped into memory and I/O space ready for use.
  1066. *
  1067. * @dev: Device to configure
  1068. * @return 0 if OK, -ve on error
  1069. */
  1070. int dm_pciauto_config_device(struct udevice *dev);
  1071. /**
  1072. * pci_conv_32_to_size() - convert a 32-bit read value to the given size
  1073. *
  1074. * Some PCI buses must always perform 32-bit reads. The data must then be
  1075. * shifted and masked to reflect the required access size and offset. This
  1076. * function performs this transformation.
  1077. *
  1078. * @value: Value to transform (32-bit value read from @offset & ~3)
  1079. * @offset: Register offset that was read
  1080. * @size: Required size of the result
  1081. * @return the value that would have been obtained if the read had been
  1082. * performed at the given offset with the correct size
  1083. */
  1084. ulong pci_conv_32_to_size(ulong value, uint offset, enum pci_size_t size);
  1085. /**
  1086. * pci_conv_size_to_32() - update a 32-bit value to prepare for a write
  1087. *
  1088. * Some PCI buses must always perform 32-bit writes. To emulate a smaller
  1089. * write the old 32-bit data must be read, updated with the required new data
  1090. * and written back as a 32-bit value. This function performs the
  1091. * transformation from the old value to the new value.
  1092. *
  1093. * @value: Value to transform (32-bit value read from @offset & ~3)
  1094. * @offset: Register offset that should be written
  1095. * @size: Required size of the write
  1096. * @return the value that should be written as a 32-bit access to @offset & ~3.
  1097. */
  1098. ulong pci_conv_size_to_32(ulong old, ulong value, uint offset,
  1099. enum pci_size_t size);
  1100. /**
  1101. * pci_get_controller() - obtain the controller to use for a bus
  1102. *
  1103. * @dev: Device to check
  1104. * @return pointer to the controller device for this bus
  1105. */
  1106. struct udevice *pci_get_controller(struct udevice *dev);
  1107. /**
  1108. * pci_get_regions() - obtain pointers to all the region types
  1109. *
  1110. * @dev: Device to check
  1111. * @iop: Returns a pointer to the I/O region, or NULL if none
  1112. * @memp: Returns a pointer to the memory region, or NULL if none
  1113. * @prefp: Returns a pointer to the pre-fetch region, or NULL if none
  1114. * @return the number of non-NULL regions returned, normally 3
  1115. */
  1116. int pci_get_regions(struct udevice *dev, struct pci_region **iop,
  1117. struct pci_region **memp, struct pci_region **prefp);
  1118. /**
  1119. * dm_pci_write_bar32() - Write the address of a BAR
  1120. *
  1121. * This writes a raw address to a bar
  1122. *
  1123. * @dev: PCI device to update
  1124. * @barnum: BAR number (0-5)
  1125. * @addr: BAR address
  1126. */
  1127. void dm_pci_write_bar32(struct udevice *dev, int barnum, u32 addr);
  1128. /**
  1129. * dm_pci_read_bar32() - read a base address register from a device
  1130. *
  1131. * @dev: Device to check
  1132. * @barnum: Bar number to read (numbered from 0)
  1133. * @return: value of BAR
  1134. */
  1135. u32 dm_pci_read_bar32(struct udevice *dev, int barnum);
  1136. /**
  1137. * dm_pci_bus_to_phys() - convert a PCI bus address to a physical address
  1138. *
  1139. * @dev: Device containing the PCI address
  1140. * @addr: PCI address to convert
  1141. * @flags: Flags for the region type (PCI_REGION_...)
  1142. * @return physical address corresponding to that PCI bus address
  1143. */
  1144. phys_addr_t dm_pci_bus_to_phys(struct udevice *dev, pci_addr_t addr,
  1145. unsigned long flags);
  1146. /**
  1147. * dm_pci_phys_to_bus() - convert a physical address to a PCI bus address
  1148. *
  1149. * @dev: Device containing the bus address
  1150. * @addr: Physical address to convert
  1151. * @flags: Flags for the region type (PCI_REGION_...)
  1152. * @return PCI bus address corresponding to that physical address
  1153. */
  1154. pci_addr_t dm_pci_phys_to_bus(struct udevice *dev, phys_addr_t addr,
  1155. unsigned long flags);
  1156. /**
  1157. * dm_pci_map_bar() - get a virtual address associated with a BAR region
  1158. *
  1159. * Looks up a base address register and finds the physical memory address
  1160. * that corresponds to it
  1161. *
  1162. * @dev: Device to check
  1163. * @bar: Bar number to read (numbered from 0)
  1164. * @flags: Flags for the region type (PCI_REGION_...)
  1165. * @return: pointer to the virtual address to use
  1166. */
  1167. void *dm_pci_map_bar(struct udevice *dev, int bar, int flags);
  1168. #define dm_pci_virt_to_bus(dev, addr, flags) \
  1169. dm_pci_phys_to_bus(dev, (virt_to_phys(addr)), (flags))
  1170. #define dm_pci_bus_to_virt(dev, addr, flags, len, map_flags) \
  1171. map_physmem(dm_pci_bus_to_phys(dev, (addr), (flags)), \
  1172. (len), (map_flags))
  1173. #define dm_pci_phys_to_mem(dev, addr) \
  1174. dm_pci_phys_to_bus((dev), (addr), PCI_REGION_MEM)
  1175. #define dm_pci_mem_to_phys(dev, addr) \
  1176. dm_pci_bus_to_phys((dev), (addr), PCI_REGION_MEM)
  1177. #define dm_pci_phys_to_io(dev, addr) \
  1178. dm_pci_phys_to_bus((dev), (addr), PCI_REGION_IO)
  1179. #define dm_pci_io_to_phys(dev, addr) \
  1180. dm_pci_bus_to_phys((dev), (addr), PCI_REGION_IO)
  1181. #define dm_pci_virt_to_mem(dev, addr) \
  1182. dm_pci_virt_to_bus((dev), (addr), PCI_REGION_MEM)
  1183. #define dm_pci_mem_to_virt(dev, addr, len, map_flags) \
  1184. dm_pci_bus_to_virt((dev), (addr), PCI_REGION_MEM, (len), (map_flags))
  1185. #define dm_pci_virt_to_io(dev, addr) \
  1186. dm_pci_virt_to_bus((dev), (addr), PCI_REGION_IO)
  1187. #define dm_pci_io_to_virt(dev, addr, len, map_flags) \
  1188. dm_pci_bus_to_virt((dev), (addr), PCI_REGION_IO, (len), (map_flags))
  1189. /**
  1190. * dm_pci_find_device() - find a device by vendor/device ID
  1191. *
  1192. * @vendor: Vendor ID
  1193. * @device: Device ID
  1194. * @index: 0 to find the first match, 1 for second, etc.
  1195. * @devp: Returns pointer to the device, if found
  1196. * @return 0 if found, -ve on error
  1197. */
  1198. int dm_pci_find_device(unsigned int vendor, unsigned int device, int index,
  1199. struct udevice **devp);
  1200. /**
  1201. * dm_pci_find_class() - find a device by class
  1202. *
  1203. * @find_class: 3-byte (24-bit) class value to find
  1204. * @index: 0 to find the first match, 1 for second, etc.
  1205. * @devp: Returns pointer to the device, if found
  1206. * @return 0 if found, -ve on error
  1207. */
  1208. int dm_pci_find_class(uint find_class, int index, struct udevice **devp);
  1209. /**
  1210. * struct dm_pci_emul_ops - PCI device emulator operations
  1211. */
  1212. struct dm_pci_emul_ops {
  1213. /**
  1214. * get_devfn(): Check which device and function this emulators
  1215. *
  1216. * @dev: device to check
  1217. * @return the device and function this emulates, or -ve on error
  1218. */
  1219. int (*get_devfn)(struct udevice *dev);
  1220. /**
  1221. * read_config() - Read a PCI configuration value
  1222. *
  1223. * @dev: Emulated device to read from
  1224. * @offset: Byte offset within the device's configuration space
  1225. * @valuep: Place to put the returned value
  1226. * @size: Access size
  1227. * @return 0 if OK, -ve on error
  1228. */
  1229. int (*read_config)(struct udevice *dev, uint offset, ulong *valuep,
  1230. enum pci_size_t size);
  1231. /**
  1232. * write_config() - Write a PCI configuration value
  1233. *
  1234. * @dev: Emulated device to write to
  1235. * @offset: Byte offset within the device's configuration space
  1236. * @value: Value to write
  1237. * @size: Access size
  1238. * @return 0 if OK, -ve on error
  1239. */
  1240. int (*write_config)(struct udevice *dev, uint offset, ulong value,
  1241. enum pci_size_t size);
  1242. /**
  1243. * read_io() - Read a PCI I/O value
  1244. *
  1245. * @dev: Emulated device to read from
  1246. * @addr: I/O address to read
  1247. * @valuep: Place to put the returned value
  1248. * @size: Access size
  1249. * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
  1250. * other -ve value on error
  1251. */
  1252. int (*read_io)(struct udevice *dev, unsigned int addr, ulong *valuep,
  1253. enum pci_size_t size);
  1254. /**
  1255. * write_io() - Write a PCI I/O value
  1256. *
  1257. * @dev: Emulated device to write from
  1258. * @addr: I/O address to write
  1259. * @value: Value to write
  1260. * @size: Access size
  1261. * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
  1262. * other -ve value on error
  1263. */
  1264. int (*write_io)(struct udevice *dev, unsigned int addr,
  1265. ulong value, enum pci_size_t size);
  1266. /**
  1267. * map_physmem() - Map a device into sandbox memory
  1268. *
  1269. * @dev: Emulated device to map
  1270. * @addr: Memory address, normally corresponding to a PCI BAR.
  1271. * The device should have been configured to have a BAR
  1272. * at this address.
  1273. * @lenp: On entry, the size of the area to map, On exit it is
  1274. * updated to the size actually mapped, which may be less
  1275. * if the device has less space
  1276. * @ptrp: Returns a pointer to the mapped address. The device's
  1277. * space can be accessed as @lenp bytes starting here
  1278. * @return 0 if OK, -ENOENT if @addr is not mapped by this device,
  1279. * other -ve value on error
  1280. */
  1281. int (*map_physmem)(struct udevice *dev, phys_addr_t addr,
  1282. unsigned long *lenp, void **ptrp);
  1283. /**
  1284. * unmap_physmem() - undo a memory mapping
  1285. *
  1286. * This must be called after map_physmem() to undo the mapping.
  1287. * Some devices can use this to check what has been written into
  1288. * their mapped memory and perform an operations they require on it.
  1289. * In this way, map/unmap can be used as a sort of handshake between
  1290. * the emulated device and its users.
  1291. *
  1292. * @dev: Emuated device to unmap
  1293. * @vaddr: Mapped memory address, as passed to map_physmem()
  1294. * @len: Size of area mapped, as returned by map_physmem()
  1295. * @return 0 if OK, -ve on error
  1296. */
  1297. int (*unmap_physmem)(struct udevice *dev, const void *vaddr,
  1298. unsigned long len);
  1299. };
  1300. /* Get access to a PCI device emulator's operations */
  1301. #define pci_get_emul_ops(dev) ((struct dm_pci_emul_ops *)(dev)->driver->ops)
  1302. /**
  1303. * sandbox_pci_get_emul() - Get the emulation device for a PCI device
  1304. *
  1305. * Searches for a suitable emulator for the given PCI bus device
  1306. *
  1307. * @bus: PCI bus to search
  1308. * @find_devfn: PCI device and function address (PCI_DEVFN())
  1309. * @emulp: Returns emulated device if found
  1310. * @return 0 if found, -ENODEV if not found
  1311. */
  1312. int sandbox_pci_get_emul(struct udevice *bus, pci_dev_t find_devfn,
  1313. struct udevice **emulp);
  1314. #endif /* CONFIG_DM_PCI */
  1315. /**
  1316. * PCI_DEVICE - macro used to describe a specific pci device
  1317. * @vend: the 16 bit PCI Vendor ID
  1318. * @dev: the 16 bit PCI Device ID
  1319. *
  1320. * This macro is used to create a struct pci_device_id that matches a
  1321. * specific device. The subvendor and subdevice fields will be set to
  1322. * PCI_ANY_ID.
  1323. */
  1324. #define PCI_DEVICE(vend, dev) \
  1325. .vendor = (vend), .device = (dev), \
  1326. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
  1327. /**
  1328. * PCI_DEVICE_SUB - macro used to describe a specific pci device with subsystem
  1329. * @vend: the 16 bit PCI Vendor ID
  1330. * @dev: the 16 bit PCI Device ID
  1331. * @subvend: the 16 bit PCI Subvendor ID
  1332. * @subdev: the 16 bit PCI Subdevice ID
  1333. *
  1334. * This macro is used to create a struct pci_device_id that matches a
  1335. * specific device with subsystem information.
  1336. */
  1337. #define PCI_DEVICE_SUB(vend, dev, subvend, subdev) \
  1338. .vendor = (vend), .device = (dev), \
  1339. .subvendor = (subvend), .subdevice = (subdev)
  1340. /**
  1341. * PCI_DEVICE_CLASS - macro used to describe a specific pci device class
  1342. * @dev_class: the class, subclass, prog-if triple for this device
  1343. * @dev_class_mask: the class mask for this device
  1344. *
  1345. * This macro is used to create a struct pci_device_id that matches a
  1346. * specific PCI class. The vendor, device, subvendor, and subdevice
  1347. * fields will be set to PCI_ANY_ID.
  1348. */
  1349. #define PCI_DEVICE_CLASS(dev_class, dev_class_mask) \
  1350. .class = (dev_class), .class_mask = (dev_class_mask), \
  1351. .vendor = PCI_ANY_ID, .device = PCI_ANY_ID, \
  1352. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID
  1353. /**
  1354. * PCI_VDEVICE - macro used to describe a specific pci device in short form
  1355. * @vend: the vendor name
  1356. * @dev: the 16 bit PCI Device ID
  1357. *
  1358. * This macro is used to create a struct pci_device_id that matches a
  1359. * specific PCI device. The subvendor, and subdevice fields will be set
  1360. * to PCI_ANY_ID. The macro allows the next field to follow as the device
  1361. * private data.
  1362. */
  1363. #define PCI_VDEVICE(vend, dev) \
  1364. .vendor = PCI_VENDOR_ID_##vend, .device = (dev), \
  1365. .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 0, 0
  1366. /**
  1367. * struct pci_driver_entry - Matches a driver to its pci_device_id list
  1368. * @driver: Driver to use
  1369. * @match: List of match records for this driver, terminated by {}
  1370. */
  1371. struct pci_driver_entry {
  1372. struct driver *driver;
  1373. const struct pci_device_id *match;
  1374. };
  1375. #define U_BOOT_PCI_DEVICE(__name, __match) \
  1376. ll_entry_declare(struct pci_driver_entry, __name, pci_driver_entry) = {\
  1377. .driver = llsym(struct driver, __name, driver), \
  1378. .match = __match, \
  1379. }
  1380. #endif /* __ASSEMBLY__ */
  1381. #endif /* _PCI_H */