mmc.h 24 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright 2008,2010 Freescale Semiconductor, Inc
  4. * Andy Fleming
  5. *
  6. * Based (loosely) on the Linux code
  7. */
  8. #ifndef _MMC_H_
  9. #define _MMC_H_
  10. #include <linux/list.h>
  11. #include <linux/sizes.h>
  12. #include <linux/compiler.h>
  13. #include <part.h>
  14. #if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
  15. #define MMC_SUPPORTS_TUNING
  16. #endif
  17. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  18. #define MMC_SUPPORTS_TUNING
  19. #endif
  20. /* SD/MMC version bits; 8 flags, 8 major, 8 minor, 8 change */
  21. #define SD_VERSION_SD (1U << 31)
  22. #define MMC_VERSION_MMC (1U << 30)
  23. #define MAKE_SDMMC_VERSION(a, b, c) \
  24. ((((u32)(a)) << 16) | ((u32)(b) << 8) | (u32)(c))
  25. #define MAKE_SD_VERSION(a, b, c) \
  26. (SD_VERSION_SD | MAKE_SDMMC_VERSION(a, b, c))
  27. #define MAKE_MMC_VERSION(a, b, c) \
  28. (MMC_VERSION_MMC | MAKE_SDMMC_VERSION(a, b, c))
  29. #define EXTRACT_SDMMC_MAJOR_VERSION(x) \
  30. (((u32)(x) >> 16) & 0xff)
  31. #define EXTRACT_SDMMC_MINOR_VERSION(x) \
  32. (((u32)(x) >> 8) & 0xff)
  33. #define EXTRACT_SDMMC_CHANGE_VERSION(x) \
  34. ((u32)(x) & 0xff)
  35. #define SD_VERSION_3 MAKE_SD_VERSION(3, 0, 0)
  36. #define SD_VERSION_2 MAKE_SD_VERSION(2, 0, 0)
  37. #define SD_VERSION_1_0 MAKE_SD_VERSION(1, 0, 0)
  38. #define SD_VERSION_1_10 MAKE_SD_VERSION(1, 10, 0)
  39. #define MMC_VERSION_UNKNOWN MAKE_MMC_VERSION(0, 0, 0)
  40. #define MMC_VERSION_1_2 MAKE_MMC_VERSION(1, 2, 0)
  41. #define MMC_VERSION_1_4 MAKE_MMC_VERSION(1, 4, 0)
  42. #define MMC_VERSION_2_2 MAKE_MMC_VERSION(2, 2, 0)
  43. #define MMC_VERSION_3 MAKE_MMC_VERSION(3, 0, 0)
  44. #define MMC_VERSION_4 MAKE_MMC_VERSION(4, 0, 0)
  45. #define MMC_VERSION_4_1 MAKE_MMC_VERSION(4, 1, 0)
  46. #define MMC_VERSION_4_2 MAKE_MMC_VERSION(4, 2, 0)
  47. #define MMC_VERSION_4_3 MAKE_MMC_VERSION(4, 3, 0)
  48. #define MMC_VERSION_4_4 MAKE_MMC_VERSION(4, 4, 0)
  49. #define MMC_VERSION_4_41 MAKE_MMC_VERSION(4, 4, 1)
  50. #define MMC_VERSION_4_5 MAKE_MMC_VERSION(4, 5, 0)
  51. #define MMC_VERSION_5_0 MAKE_MMC_VERSION(5, 0, 0)
  52. #define MMC_VERSION_5_1 MAKE_MMC_VERSION(5, 1, 0)
  53. #define MMC_CAP(mode) (1 << mode)
  54. #define MMC_MODE_HS (MMC_CAP(MMC_HS) | MMC_CAP(SD_HS))
  55. #define MMC_MODE_HS_52MHz MMC_CAP(MMC_HS_52)
  56. #define MMC_MODE_DDR_52MHz MMC_CAP(MMC_DDR_52)
  57. #define MMC_MODE_HS200 MMC_CAP(MMC_HS_200)
  58. #define MMC_MODE_8BIT BIT(30)
  59. #define MMC_MODE_4BIT BIT(29)
  60. #define MMC_MODE_1BIT BIT(28)
  61. #define MMC_MODE_SPI BIT(27)
  62. #define SD_DATA_4BIT 0x00040000
  63. #define IS_SD(x) ((x)->version & SD_VERSION_SD)
  64. #define IS_MMC(x) ((x)->version & MMC_VERSION_MMC)
  65. #define MMC_DATA_READ 1
  66. #define MMC_DATA_WRITE 2
  67. #define MMC_CMD_GO_IDLE_STATE 0
  68. #define MMC_CMD_SEND_OP_COND 1
  69. #define MMC_CMD_ALL_SEND_CID 2
  70. #define MMC_CMD_SET_RELATIVE_ADDR 3
  71. #define MMC_CMD_SET_DSR 4
  72. #define MMC_CMD_SWITCH 6
  73. #define MMC_CMD_SELECT_CARD 7
  74. #define MMC_CMD_SEND_EXT_CSD 8
  75. #define MMC_CMD_SEND_CSD 9
  76. #define MMC_CMD_SEND_CID 10
  77. #define MMC_CMD_STOP_TRANSMISSION 12
  78. #define MMC_CMD_SEND_STATUS 13
  79. #define MMC_CMD_SET_BLOCKLEN 16
  80. #define MMC_CMD_READ_SINGLE_BLOCK 17
  81. #define MMC_CMD_READ_MULTIPLE_BLOCK 18
  82. #define MMC_CMD_SEND_TUNING_BLOCK 19
  83. #define MMC_CMD_SEND_TUNING_BLOCK_HS200 21
  84. #define MMC_CMD_SET_BLOCK_COUNT 23
  85. #define MMC_CMD_WRITE_SINGLE_BLOCK 24
  86. #define MMC_CMD_WRITE_MULTIPLE_BLOCK 25
  87. #define MMC_CMD_ERASE_GROUP_START 35
  88. #define MMC_CMD_ERASE_GROUP_END 36
  89. #define MMC_CMD_ERASE 38
  90. #define MMC_CMD_APP_CMD 55
  91. #define MMC_CMD_SPI_READ_OCR 58
  92. #define MMC_CMD_SPI_CRC_ON_OFF 59
  93. #define MMC_CMD_RES_MAN 62
  94. #define MMC_CMD62_ARG1 0xefac62ec
  95. #define MMC_CMD62_ARG2 0xcbaea7
  96. #define SD_CMD_SEND_RELATIVE_ADDR 3
  97. #define SD_CMD_SWITCH_FUNC 6
  98. #define SD_CMD_SEND_IF_COND 8
  99. #define SD_CMD_SWITCH_UHS18V 11
  100. #define SD_CMD_APP_SET_BUS_WIDTH 6
  101. #define SD_CMD_APP_SD_STATUS 13
  102. #define SD_CMD_ERASE_WR_BLK_START 32
  103. #define SD_CMD_ERASE_WR_BLK_END 33
  104. #define SD_CMD_APP_SEND_OP_COND 41
  105. #define SD_CMD_APP_SEND_SCR 51
  106. static inline bool mmc_is_tuning_cmd(uint cmdidx)
  107. {
  108. if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
  109. (cmdidx == MMC_CMD_SEND_TUNING_BLOCK))
  110. return true;
  111. return false;
  112. }
  113. /* SCR definitions in different words */
  114. #define SD_HIGHSPEED_BUSY 0x00020000
  115. #define SD_HIGHSPEED_SUPPORTED 0x00020000
  116. #define UHS_SDR12_BUS_SPEED 0
  117. #define HIGH_SPEED_BUS_SPEED 1
  118. #define UHS_SDR25_BUS_SPEED 1
  119. #define UHS_SDR50_BUS_SPEED 2
  120. #define UHS_SDR104_BUS_SPEED 3
  121. #define UHS_DDR50_BUS_SPEED 4
  122. #define SD_MODE_UHS_SDR12 BIT(UHS_SDR12_BUS_SPEED)
  123. #define SD_MODE_UHS_SDR25 BIT(UHS_SDR25_BUS_SPEED)
  124. #define SD_MODE_UHS_SDR50 BIT(UHS_SDR50_BUS_SPEED)
  125. #define SD_MODE_UHS_SDR104 BIT(UHS_SDR104_BUS_SPEED)
  126. #define SD_MODE_UHS_DDR50 BIT(UHS_DDR50_BUS_SPEED)
  127. #define OCR_BUSY 0x80000000
  128. #define OCR_HCS 0x40000000
  129. #define OCR_S18R 0x1000000
  130. #define OCR_VOLTAGE_MASK 0x007FFF80
  131. #define OCR_ACCESS_MODE 0x60000000
  132. #define MMC_ERASE_ARG 0x00000000
  133. #define MMC_SECURE_ERASE_ARG 0x80000000
  134. #define MMC_TRIM_ARG 0x00000001
  135. #define MMC_DISCARD_ARG 0x00000003
  136. #define MMC_SECURE_TRIM1_ARG 0x80000001
  137. #define MMC_SECURE_TRIM2_ARG 0x80008000
  138. #define MMC_STATUS_MASK (~0x0206BF7F)
  139. #define MMC_STATUS_SWITCH_ERROR (1 << 7)
  140. #define MMC_STATUS_RDY_FOR_DATA (1 << 8)
  141. #define MMC_STATUS_CURR_STATE (0xf << 9)
  142. #define MMC_STATUS_ERROR (1 << 19)
  143. #define MMC_STATE_PRG (7 << 9)
  144. #define MMC_VDD_165_195 0x00000080 /* VDD voltage 1.65 - 1.95 */
  145. #define MMC_VDD_20_21 0x00000100 /* VDD voltage 2.0 ~ 2.1 */
  146. #define MMC_VDD_21_22 0x00000200 /* VDD voltage 2.1 ~ 2.2 */
  147. #define MMC_VDD_22_23 0x00000400 /* VDD voltage 2.2 ~ 2.3 */
  148. #define MMC_VDD_23_24 0x00000800 /* VDD voltage 2.3 ~ 2.4 */
  149. #define MMC_VDD_24_25 0x00001000 /* VDD voltage 2.4 ~ 2.5 */
  150. #define MMC_VDD_25_26 0x00002000 /* VDD voltage 2.5 ~ 2.6 */
  151. #define MMC_VDD_26_27 0x00004000 /* VDD voltage 2.6 ~ 2.7 */
  152. #define MMC_VDD_27_28 0x00008000 /* VDD voltage 2.7 ~ 2.8 */
  153. #define MMC_VDD_28_29 0x00010000 /* VDD voltage 2.8 ~ 2.9 */
  154. #define MMC_VDD_29_30 0x00020000 /* VDD voltage 2.9 ~ 3.0 */
  155. #define MMC_VDD_30_31 0x00040000 /* VDD voltage 3.0 ~ 3.1 */
  156. #define MMC_VDD_31_32 0x00080000 /* VDD voltage 3.1 ~ 3.2 */
  157. #define MMC_VDD_32_33 0x00100000 /* VDD voltage 3.2 ~ 3.3 */
  158. #define MMC_VDD_33_34 0x00200000 /* VDD voltage 3.3 ~ 3.4 */
  159. #define MMC_VDD_34_35 0x00400000 /* VDD voltage 3.4 ~ 3.5 */
  160. #define MMC_VDD_35_36 0x00800000 /* VDD voltage 3.5 ~ 3.6 */
  161. #define MMC_SWITCH_MODE_CMD_SET 0x00 /* Change the command set */
  162. #define MMC_SWITCH_MODE_SET_BITS 0x01 /* Set bits in EXT_CSD byte
  163. addressed by index which are
  164. 1 in value field */
  165. #define MMC_SWITCH_MODE_CLEAR_BITS 0x02 /* Clear bits in EXT_CSD byte
  166. addressed by index, which are
  167. 1 in value field */
  168. #define MMC_SWITCH_MODE_WRITE_BYTE 0x03 /* Set target byte to value */
  169. #define SD_SWITCH_CHECK 0
  170. #define SD_SWITCH_SWITCH 1
  171. /*
  172. * EXT_CSD fields
  173. */
  174. #define EXT_CSD_ENH_START_ADDR 136 /* R/W */
  175. #define EXT_CSD_ENH_SIZE_MULT 140 /* R/W */
  176. #define EXT_CSD_GP_SIZE_MULT 143 /* R/W */
  177. #define EXT_CSD_PARTITION_SETTING 155 /* R/W */
  178. #define EXT_CSD_PARTITIONS_ATTRIBUTE 156 /* R/W */
  179. #define EXT_CSD_MAX_ENH_SIZE_MULT 157 /* R */
  180. #define EXT_CSD_PARTITIONING_SUPPORT 160 /* RO */
  181. #define EXT_CSD_RST_N_FUNCTION 162 /* R/W */
  182. #define EXT_CSD_BKOPS_EN 163 /* R/W & R/W/E */
  183. #define EXT_CSD_WR_REL_PARAM 166 /* R */
  184. #define EXT_CSD_WR_REL_SET 167 /* R/W */
  185. #define EXT_CSD_RPMB_MULT 168 /* RO */
  186. #define EXT_CSD_ERASE_GROUP_DEF 175 /* R/W */
  187. #define EXT_CSD_BOOT_BUS_WIDTH 177
  188. #define EXT_CSD_PART_CONF 179 /* R/W */
  189. #define EXT_CSD_BUS_WIDTH 183 /* R/W */
  190. #define EXT_CSD_HS_TIMING 185 /* R/W */
  191. #define EXT_CSD_REV 192 /* RO */
  192. #define EXT_CSD_CARD_TYPE 196 /* RO */
  193. #define EXT_CSD_SEC_CNT 212 /* RO, 4 bytes */
  194. #define EXT_CSD_HC_WP_GRP_SIZE 221 /* RO */
  195. #define EXT_CSD_HC_ERASE_GRP_SIZE 224 /* RO */
  196. #define EXT_CSD_BOOT_MULT 226 /* RO */
  197. #define EXT_CSD_BKOPS_SUPPORT 502 /* RO */
  198. /*
  199. * EXT_CSD field definitions
  200. */
  201. #define EXT_CSD_CMD_SET_NORMAL (1 << 0)
  202. #define EXT_CSD_CMD_SET_SECURE (1 << 1)
  203. #define EXT_CSD_CMD_SET_CPSECURE (1 << 2)
  204. #define EXT_CSD_CARD_TYPE_26 (1 << 0) /* Card can run at 26MHz */
  205. #define EXT_CSD_CARD_TYPE_52 (1 << 1) /* Card can run at 52MHz */
  206. #define EXT_CSD_CARD_TYPE_DDR_1_8V (1 << 2)
  207. #define EXT_CSD_CARD_TYPE_DDR_1_2V (1 << 3)
  208. #define EXT_CSD_CARD_TYPE_DDR_52 (EXT_CSD_CARD_TYPE_DDR_1_8V \
  209. | EXT_CSD_CARD_TYPE_DDR_1_2V)
  210. #define EXT_CSD_CARD_TYPE_HS200_1_8V BIT(4) /* Card can run at 200MHz */
  211. /* SDR mode @1.8V I/O */
  212. #define EXT_CSD_CARD_TYPE_HS200_1_2V BIT(5) /* Card can run at 200MHz */
  213. /* SDR mode @1.2V I/O */
  214. #define EXT_CSD_CARD_TYPE_HS200 (EXT_CSD_CARD_TYPE_HS200_1_8V | \
  215. EXT_CSD_CARD_TYPE_HS200_1_2V)
  216. #define EXT_CSD_BUS_WIDTH_1 0 /* Card is in 1 bit mode */
  217. #define EXT_CSD_BUS_WIDTH_4 1 /* Card is in 4 bit mode */
  218. #define EXT_CSD_BUS_WIDTH_8 2 /* Card is in 8 bit mode */
  219. #define EXT_CSD_DDR_BUS_WIDTH_4 5 /* Card is in 4 bit DDR mode */
  220. #define EXT_CSD_DDR_BUS_WIDTH_8 6 /* Card is in 8 bit DDR mode */
  221. #define EXT_CSD_DDR_FLAG BIT(2) /* Flag for DDR mode */
  222. #define EXT_CSD_TIMING_LEGACY 0 /* no high speed */
  223. #define EXT_CSD_TIMING_HS 1 /* HS */
  224. #define EXT_CSD_TIMING_HS200 2 /* HS200 */
  225. #define EXT_CSD_BOOT_ACK_ENABLE (1 << 6)
  226. #define EXT_CSD_BOOT_PARTITION_ENABLE (1 << 3)
  227. #define EXT_CSD_PARTITION_ACCESS_ENABLE (1 << 0)
  228. #define EXT_CSD_PARTITION_ACCESS_DISABLE (0 << 0)
  229. #define EXT_CSD_BOOT_ACK(x) (x << 6)
  230. #define EXT_CSD_BOOT_PART_NUM(x) (x << 3)
  231. #define EXT_CSD_PARTITION_ACCESS(x) (x << 0)
  232. #define EXT_CSD_EXTRACT_BOOT_ACK(x) (((x) >> 6) & 0x1)
  233. #define EXT_CSD_EXTRACT_BOOT_PART(x) (((x) >> 3) & 0x7)
  234. #define EXT_CSD_EXTRACT_PARTITION_ACCESS(x) ((x) & 0x7)
  235. #define EXT_CSD_BOOT_BUS_WIDTH_MODE(x) (x << 3)
  236. #define EXT_CSD_BOOT_BUS_WIDTH_RESET(x) (x << 2)
  237. #define EXT_CSD_BOOT_BUS_WIDTH_WIDTH(x) (x)
  238. #define EXT_CSD_PARTITION_SETTING_COMPLETED (1 << 0)
  239. #define EXT_CSD_ENH_USR (1 << 0) /* user data area is enhanced */
  240. #define EXT_CSD_ENH_GP(x) (1 << ((x)+1)) /* GP part (x+1) is enhanced */
  241. #define EXT_CSD_HS_CTRL_REL (1 << 0) /* host controlled WR_REL_SET */
  242. #define EXT_CSD_WR_DATA_REL_USR (1 << 0) /* user data area WR_REL */
  243. #define EXT_CSD_WR_DATA_REL_GP(x) (1 << ((x)+1)) /* GP part (x+1) WR_REL */
  244. #define R1_ILLEGAL_COMMAND (1 << 22)
  245. #define R1_APP_CMD (1 << 5)
  246. #define MMC_RSP_PRESENT (1 << 0)
  247. #define MMC_RSP_136 (1 << 1) /* 136 bit response */
  248. #define MMC_RSP_CRC (1 << 2) /* expect valid crc */
  249. #define MMC_RSP_BUSY (1 << 3) /* card may send busy */
  250. #define MMC_RSP_OPCODE (1 << 4) /* response contains opcode */
  251. #define MMC_RSP_NONE (0)
  252. #define MMC_RSP_R1 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  253. #define MMC_RSP_R1b (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE| \
  254. MMC_RSP_BUSY)
  255. #define MMC_RSP_R2 (MMC_RSP_PRESENT|MMC_RSP_136|MMC_RSP_CRC)
  256. #define MMC_RSP_R3 (MMC_RSP_PRESENT)
  257. #define MMC_RSP_R4 (MMC_RSP_PRESENT)
  258. #define MMC_RSP_R5 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  259. #define MMC_RSP_R6 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  260. #define MMC_RSP_R7 (MMC_RSP_PRESENT|MMC_RSP_CRC|MMC_RSP_OPCODE)
  261. #define MMCPART_NOAVAILABLE (0xff)
  262. #define PART_ACCESS_MASK (0x7)
  263. #define PART_SUPPORT (0x1)
  264. #define ENHNCD_SUPPORT (0x2)
  265. #define PART_ENH_ATTRIB (0x1f)
  266. #define MMC_QUIRK_RETRY_SEND_CID BIT(0)
  267. #define MMC_QUIRK_RETRY_SET_BLOCKLEN BIT(1)
  268. enum mmc_voltage {
  269. MMC_SIGNAL_VOLTAGE_000 = 0,
  270. MMC_SIGNAL_VOLTAGE_120 = 1,
  271. MMC_SIGNAL_VOLTAGE_180 = 2,
  272. MMC_SIGNAL_VOLTAGE_330 = 4,
  273. };
  274. #define MMC_ALL_SIGNAL_VOLTAGE (MMC_SIGNAL_VOLTAGE_120 |\
  275. MMC_SIGNAL_VOLTAGE_180 |\
  276. MMC_SIGNAL_VOLTAGE_330)
  277. /* Maximum block size for MMC */
  278. #define MMC_MAX_BLOCK_LEN 512
  279. /* The number of MMC physical partitions. These consist of:
  280. * boot partitions (2), general purpose partitions (4) in MMC v4.4.
  281. */
  282. #define MMC_NUM_BOOT_PARTITION 2
  283. #define MMC_PART_RPMB 3 /* RPMB partition number */
  284. /* Driver model support */
  285. /**
  286. * struct mmc_uclass_priv - Holds information about a device used by the uclass
  287. */
  288. struct mmc_uclass_priv {
  289. struct mmc *mmc;
  290. };
  291. /**
  292. * mmc_get_mmc_dev() - get the MMC struct pointer for a device
  293. *
  294. * Provided that the device is already probed and ready for use, this value
  295. * will be available.
  296. *
  297. * @dev: Device
  298. * @return associated mmc struct pointer if available, else NULL
  299. */
  300. struct mmc *mmc_get_mmc_dev(struct udevice *dev);
  301. /* End of driver model support */
  302. struct mmc_cid {
  303. unsigned long psn;
  304. unsigned short oid;
  305. unsigned char mid;
  306. unsigned char prv;
  307. unsigned char mdt;
  308. char pnm[7];
  309. };
  310. struct mmc_cmd {
  311. ushort cmdidx;
  312. uint resp_type;
  313. uint cmdarg;
  314. uint response[4];
  315. };
  316. struct mmc_data {
  317. union {
  318. char *dest;
  319. const char *src; /* src buffers don't get written to */
  320. };
  321. uint flags;
  322. uint blocks;
  323. uint blocksize;
  324. };
  325. /* forward decl. */
  326. struct mmc;
  327. #if CONFIG_IS_ENABLED(DM_MMC)
  328. struct dm_mmc_ops {
  329. /**
  330. * send_cmd() - Send a command to the MMC device
  331. *
  332. * @dev: Device to receive the command
  333. * @cmd: Command to send
  334. * @data: Additional data to send/receive
  335. * @return 0 if OK, -ve on error
  336. */
  337. int (*send_cmd)(struct udevice *dev, struct mmc_cmd *cmd,
  338. struct mmc_data *data);
  339. /**
  340. * set_ios() - Set the I/O speed/width for an MMC device
  341. *
  342. * @dev: Device to update
  343. * @return 0 if OK, -ve on error
  344. */
  345. int (*set_ios)(struct udevice *dev);
  346. /**
  347. * send_init_stream() - send the initialization stream: 74 clock cycles
  348. * This is used after power up before sending the first command
  349. *
  350. * @dev: Device to update
  351. */
  352. void (*send_init_stream)(struct udevice *dev);
  353. /**
  354. * get_cd() - See whether a card is present
  355. *
  356. * @dev: Device to check
  357. * @return 0 if not present, 1 if present, -ve on error
  358. */
  359. int (*get_cd)(struct udevice *dev);
  360. /**
  361. * get_wp() - See whether a card has write-protect enabled
  362. *
  363. * @dev: Device to check
  364. * @return 0 if write-enabled, 1 if write-protected, -ve on error
  365. */
  366. int (*get_wp)(struct udevice *dev);
  367. #ifdef MMC_SUPPORTS_TUNING
  368. /**
  369. * execute_tuning() - Start the tuning process
  370. *
  371. * @dev: Device to start the tuning
  372. * @opcode: Command opcode to send
  373. * @return 0 if OK, -ve on error
  374. */
  375. int (*execute_tuning)(struct udevice *dev, uint opcode);
  376. #endif
  377. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  378. /**
  379. * wait_dat0() - wait until dat0 is in the target state
  380. * (CLK must be running during the wait)
  381. *
  382. * @dev: Device to check
  383. * @state: target state
  384. * @timeout: timeout in us
  385. * @return 0 if dat0 is in the target state, -ve on error
  386. */
  387. int (*wait_dat0)(struct udevice *dev, int state, int timeout);
  388. #endif
  389. };
  390. #define mmc_get_ops(dev) ((struct dm_mmc_ops *)(dev)->driver->ops)
  391. int dm_mmc_send_cmd(struct udevice *dev, struct mmc_cmd *cmd,
  392. struct mmc_data *data);
  393. int dm_mmc_set_ios(struct udevice *dev);
  394. void dm_mmc_send_init_stream(struct udevice *dev);
  395. int dm_mmc_get_cd(struct udevice *dev);
  396. int dm_mmc_get_wp(struct udevice *dev);
  397. int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
  398. int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
  399. /* Transition functions for compatibility */
  400. int mmc_set_ios(struct mmc *mmc);
  401. void mmc_send_init_stream(struct mmc *mmc);
  402. int mmc_getcd(struct mmc *mmc);
  403. int mmc_getwp(struct mmc *mmc);
  404. int mmc_execute_tuning(struct mmc *mmc, uint opcode);
  405. int mmc_wait_dat0(struct mmc *mmc, int state, int timeout);
  406. #else
  407. struct mmc_ops {
  408. int (*send_cmd)(struct mmc *mmc,
  409. struct mmc_cmd *cmd, struct mmc_data *data);
  410. int (*set_ios)(struct mmc *mmc);
  411. int (*init)(struct mmc *mmc);
  412. int (*getcd)(struct mmc *mmc);
  413. int (*getwp)(struct mmc *mmc);
  414. };
  415. #endif
  416. struct mmc_config {
  417. const char *name;
  418. #if !CONFIG_IS_ENABLED(DM_MMC)
  419. const struct mmc_ops *ops;
  420. #endif
  421. uint host_caps;
  422. uint voltages;
  423. uint f_min;
  424. uint f_max;
  425. uint b_max;
  426. unsigned char part_type;
  427. };
  428. struct sd_ssr {
  429. unsigned int au; /* In sectors */
  430. unsigned int erase_timeout; /* In milliseconds */
  431. unsigned int erase_offset; /* In milliseconds */
  432. };
  433. enum bus_mode {
  434. MMC_LEGACY,
  435. SD_LEGACY,
  436. MMC_HS,
  437. SD_HS,
  438. MMC_HS_52,
  439. MMC_DDR_52,
  440. UHS_SDR12,
  441. UHS_SDR25,
  442. UHS_SDR50,
  443. UHS_DDR50,
  444. UHS_SDR104,
  445. MMC_HS_200,
  446. MMC_MODES_END
  447. };
  448. const char *mmc_mode_name(enum bus_mode mode);
  449. void mmc_dump_capabilities(const char *text, uint caps);
  450. static inline bool mmc_is_mode_ddr(enum bus_mode mode)
  451. {
  452. if (mode == MMC_DDR_52)
  453. return true;
  454. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  455. else if (mode == UHS_DDR50)
  456. return true;
  457. #endif
  458. else
  459. return false;
  460. }
  461. #define UHS_CAPS (MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25) | \
  462. MMC_CAP(UHS_SDR50) | MMC_CAP(UHS_SDR104) | \
  463. MMC_CAP(UHS_DDR50))
  464. static inline bool supports_uhs(uint caps)
  465. {
  466. #if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
  467. return (caps & UHS_CAPS) ? true : false;
  468. #else
  469. return false;
  470. #endif
  471. }
  472. /*
  473. * With CONFIG_DM_MMC enabled, struct mmc can be accessed from the MMC device
  474. * with mmc_get_mmc_dev().
  475. *
  476. * TODO struct mmc should be in mmc_private but it's hard to fix right now
  477. */
  478. struct mmc {
  479. #if !CONFIG_IS_ENABLED(BLK)
  480. struct list_head link;
  481. #endif
  482. const struct mmc_config *cfg; /* provided configuration */
  483. uint version;
  484. void *priv;
  485. uint has_init;
  486. int high_capacity;
  487. bool clk_disable; /* true if the clock can be turned off */
  488. uint bus_width;
  489. uint clock;
  490. enum mmc_voltage signal_voltage;
  491. uint card_caps;
  492. uint host_caps;
  493. uint ocr;
  494. uint dsr;
  495. uint dsr_imp;
  496. uint scr[2];
  497. uint csd[4];
  498. uint cid[4];
  499. ushort rca;
  500. u8 part_support;
  501. u8 part_attr;
  502. u8 wr_rel_set;
  503. u8 part_config;
  504. uint tran_speed;
  505. uint legacy_speed; /* speed for the legacy mode provided by the card */
  506. uint read_bl_len;
  507. #if CONFIG_IS_ENABLED(MMC_WRITE)
  508. uint write_bl_len;
  509. uint erase_grp_size; /* in 512-byte sectors */
  510. #endif
  511. #if CONFIG_IS_ENABLED(MMC_HW_PARTITIONING)
  512. uint hc_wp_grp_size; /* in 512-byte sectors */
  513. #endif
  514. #if CONFIG_IS_ENABLED(MMC_WRITE)
  515. struct sd_ssr ssr; /* SD status register */
  516. #endif
  517. u64 capacity;
  518. u64 capacity_user;
  519. u64 capacity_boot;
  520. u64 capacity_rpmb;
  521. u64 capacity_gp[4];
  522. #ifndef CONFIG_SPL_BUILD
  523. u64 enh_user_start;
  524. u64 enh_user_size;
  525. #endif
  526. #if !CONFIG_IS_ENABLED(BLK)
  527. struct blk_desc block_dev;
  528. #endif
  529. char op_cond_pending; /* 1 if we are waiting on an op_cond command */
  530. char init_in_progress; /* 1 if we have done mmc_start_init() */
  531. char preinit; /* start init as early as possible */
  532. int ddr_mode;
  533. #if CONFIG_IS_ENABLED(DM_MMC)
  534. struct udevice *dev; /* Device for this MMC controller */
  535. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  536. struct udevice *vmmc_supply; /* Main voltage regulator (Vcc)*/
  537. struct udevice *vqmmc_supply; /* IO voltage regulator (Vccq)*/
  538. #endif
  539. #endif
  540. u8 *ext_csd;
  541. u32 cardtype; /* cardtype read from the MMC */
  542. enum mmc_voltage current_voltage;
  543. enum bus_mode selected_mode; /* mode currently used */
  544. enum bus_mode best_mode; /* best mode is the supported mode with the
  545. * highest bandwidth. It may not always be the
  546. * operating mode due to limitations when
  547. * accessing the boot partitions
  548. */
  549. u32 quirks;
  550. };
  551. struct mmc_hwpart_conf {
  552. struct {
  553. uint enh_start; /* in 512-byte sectors */
  554. uint enh_size; /* in 512-byte sectors, if 0 no enh area */
  555. unsigned wr_rel_change : 1;
  556. unsigned wr_rel_set : 1;
  557. } user;
  558. struct {
  559. uint size; /* in 512-byte sectors */
  560. unsigned enhanced : 1;
  561. unsigned wr_rel_change : 1;
  562. unsigned wr_rel_set : 1;
  563. } gp_part[4];
  564. };
  565. enum mmc_hwpart_conf_mode {
  566. MMC_HWPART_CONF_CHECK,
  567. MMC_HWPART_CONF_SET,
  568. MMC_HWPART_CONF_COMPLETE,
  569. };
  570. struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
  571. /**
  572. * mmc_bind() - Set up a new MMC device ready for probing
  573. *
  574. * A child block device is bound with the IF_TYPE_MMC interface type. This
  575. * allows the device to be used with CONFIG_BLK
  576. *
  577. * @dev: MMC device to set up
  578. * @mmc: MMC struct
  579. * @cfg: MMC configuration
  580. * @return 0 if OK, -ve on error
  581. */
  582. int mmc_bind(struct udevice *dev, struct mmc *mmc,
  583. const struct mmc_config *cfg);
  584. void mmc_destroy(struct mmc *mmc);
  585. /**
  586. * mmc_unbind() - Unbind a MMC device's child block device
  587. *
  588. * @dev: MMC device
  589. * @return 0 if OK, -ve on error
  590. */
  591. int mmc_unbind(struct udevice *dev);
  592. int mmc_initialize(bd_t *bis);
  593. int mmc_init(struct mmc *mmc);
  594. int mmc_send_tuning(struct mmc *mmc, u32 opcode, int *cmd_error);
  595. /**
  596. * mmc_of_parse() - Parse the device tree to get the capabilities of the host
  597. *
  598. * @dev: MMC device
  599. * @cfg: MMC configuration
  600. * @return 0 if OK, -ve on error
  601. */
  602. int mmc_of_parse(struct udevice *dev, struct mmc_config *cfg);
  603. int mmc_read(struct mmc *mmc, u64 src, uchar *dst, int size);
  604. /**
  605. * mmc_voltage_to_mv() - Convert a mmc_voltage in mV
  606. *
  607. * @voltage: The mmc_voltage to convert
  608. * @return the value in mV if OK, -EINVAL on error (invalid mmc_voltage value)
  609. */
  610. int mmc_voltage_to_mv(enum mmc_voltage voltage);
  611. /**
  612. * mmc_set_clock() - change the bus clock
  613. * @mmc: MMC struct
  614. * @clock: bus frequency in Hz
  615. * @disable: flag indicating if the clock must on or off
  616. * @return 0 if OK, -ve on error
  617. */
  618. int mmc_set_clock(struct mmc *mmc, uint clock, bool disable);
  619. #define MMC_CLK_ENABLE false
  620. #define MMC_CLK_DISABLE true
  621. struct mmc *find_mmc_device(int dev_num);
  622. int mmc_set_dev(int dev_num);
  623. void print_mmc_devices(char separator);
  624. /**
  625. * get_mmc_num() - get the total MMC device number
  626. *
  627. * @return 0 if there is no MMC device, else the number of devices
  628. */
  629. int get_mmc_num(void);
  630. int mmc_switch_part(struct mmc *mmc, unsigned int part_num);
  631. int mmc_hwpart_config(struct mmc *mmc, const struct mmc_hwpart_conf *conf,
  632. enum mmc_hwpart_conf_mode mode);
  633. #if !CONFIG_IS_ENABLED(DM_MMC)
  634. int mmc_getcd(struct mmc *mmc);
  635. int board_mmc_getcd(struct mmc *mmc);
  636. int mmc_getwp(struct mmc *mmc);
  637. int board_mmc_getwp(struct mmc *mmc);
  638. #endif
  639. int mmc_set_dsr(struct mmc *mmc, u16 val);
  640. /* Function to change the size of boot partition and rpmb partitions */
  641. int mmc_boot_partition_size_change(struct mmc *mmc, unsigned long bootsize,
  642. unsigned long rpmbsize);
  643. /* Function to modify the PARTITION_CONFIG field of EXT_CSD */
  644. int mmc_set_part_conf(struct mmc *mmc, u8 ack, u8 part_num, u8 access);
  645. /* Function to modify the BOOT_BUS_WIDTH field of EXT_CSD */
  646. int mmc_set_boot_bus_width(struct mmc *mmc, u8 width, u8 reset, u8 mode);
  647. /* Function to modify the RST_n_FUNCTION field of EXT_CSD */
  648. int mmc_set_rst_n_function(struct mmc *mmc, u8 enable);
  649. /* Functions to read / write the RPMB partition */
  650. int mmc_rpmb_set_key(struct mmc *mmc, void *key);
  651. int mmc_rpmb_get_counter(struct mmc *mmc, unsigned long *counter);
  652. int mmc_rpmb_read(struct mmc *mmc, void *addr, unsigned short blk,
  653. unsigned short cnt, unsigned char *key);
  654. int mmc_rpmb_write(struct mmc *mmc, void *addr, unsigned short blk,
  655. unsigned short cnt, unsigned char *key);
  656. #ifdef CONFIG_CMD_BKOPS_ENABLE
  657. int mmc_set_bkops_enable(struct mmc *mmc);
  658. #endif
  659. /**
  660. * Start device initialization and return immediately; it does not block on
  661. * polling OCR (operation condition register) status. Then you should call
  662. * mmc_init, which would block on polling OCR status and complete the device
  663. * initializatin.
  664. *
  665. * @param mmc Pointer to a MMC device struct
  666. * @return 0 on success, IN_PROGRESS on waiting for OCR status, <0 on error.
  667. */
  668. int mmc_start_init(struct mmc *mmc);
  669. /**
  670. * Set preinit flag of mmc device.
  671. *
  672. * This will cause the device to be pre-inited during mmc_initialize(),
  673. * which may save boot time if the device is not accessed until later.
  674. * Some eMMC devices take 200-300ms to init, but unfortunately they
  675. * must be sent a series of commands to even get them to start preparing
  676. * for operation.
  677. *
  678. * @param mmc Pointer to a MMC device struct
  679. * @param preinit preinit flag value
  680. */
  681. void mmc_set_preinit(struct mmc *mmc, int preinit);
  682. #ifdef CONFIG_MMC_SPI
  683. #define mmc_host_is_spi(mmc) ((mmc)->cfg->host_caps & MMC_MODE_SPI)
  684. #else
  685. #define mmc_host_is_spi(mmc) 0
  686. #endif
  687. struct mmc *mmc_spi_init(uint bus, uint cs, uint speed, uint mode);
  688. void board_mmc_power_init(void);
  689. int board_mmc_init(bd_t *bis);
  690. int cpu_mmc_init(bd_t *bis);
  691. int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr);
  692. int mmc_get_env_dev(void);
  693. /* Set block count limit because of 16 bit register limit on some hardware*/
  694. #ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT
  695. #define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535
  696. #endif
  697. /**
  698. * mmc_get_blk_desc() - Get the block descriptor for an MMC device
  699. *
  700. * @mmc: MMC device
  701. * @return block device if found, else NULL
  702. */
  703. struct blk_desc *mmc_get_blk_desc(struct mmc *mmc);
  704. #endif /* _MMC_H_ */