gdsys_fpga.h 7.2 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * (C) Copyright 2010
  4. * Dirk Eibach, Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
  5. */
  6. #ifndef __GDSYS_FPGA_H
  7. #define __GDSYS_FPGA_H
  8. int init_func_fpga(void);
  9. enum {
  10. FPGA_STATE_DONE_FAILED = 1 << 0,
  11. FPGA_STATE_REFLECTION_FAILED = 1 << 1,
  12. FPGA_STATE_PLATFORM = 1 << 2,
  13. };
  14. int get_fpga_state(unsigned dev);
  15. int fpga_set_reg(u32 fpga, u16 *reg, off_t regoff, u16 data);
  16. int fpga_get_reg(u32 fpga, u16 *reg, off_t regoff, u16 *data);
  17. extern struct ihs_fpga *fpga_ptr[];
  18. #define FPGA_SET_REG(ix, fld, val) \
  19. fpga_set_reg((ix), \
  20. &fpga_ptr[ix]->fld, \
  21. offsetof(struct ihs_fpga, fld), \
  22. val)
  23. #define FPGA_GET_REG(ix, fld, val) \
  24. fpga_get_reg((ix), \
  25. &fpga_ptr[ix]->fld, \
  26. offsetof(struct ihs_fpga, fld), \
  27. val)
  28. struct ihs_gpio {
  29. u16 read;
  30. u16 clear;
  31. u16 set;
  32. };
  33. struct ihs_i2c {
  34. u16 interrupt_status;
  35. u16 interrupt_enable;
  36. u16 write_mailbox_ext;
  37. u16 write_mailbox;
  38. u16 read_mailbox_ext;
  39. u16 read_mailbox;
  40. };
  41. struct ihs_osd {
  42. u16 version;
  43. u16 features;
  44. u16 control;
  45. u16 xy_size;
  46. u16 xy_scale;
  47. u16 x_pos;
  48. u16 y_pos;
  49. };
  50. struct ihs_mdio {
  51. u16 control;
  52. u16 address_data;
  53. u16 rx_data;
  54. };
  55. struct ihs_io_ep {
  56. u16 transmit_data;
  57. u16 rx_tx_control;
  58. u16 receive_data;
  59. u16 rx_tx_status;
  60. u16 reserved;
  61. u16 device_address;
  62. u16 target_address;
  63. };
  64. #ifdef CONFIG_NEO
  65. struct ihs_fpga {
  66. u16 reflection_low; /* 0x0000 */
  67. u16 versions; /* 0x0002 */
  68. u16 fpga_features; /* 0x0004 */
  69. u16 fpga_version; /* 0x0006 */
  70. u16 reserved_0[8187]; /* 0x0008 */
  71. u16 reflection_high; /* 0x3ffe */
  72. };
  73. #endif
  74. #ifdef CONFIG_IO
  75. struct ihs_fpga {
  76. u16 reflection_low; /* 0x0000 */
  77. u16 versions; /* 0x0002 */
  78. u16 fpga_features; /* 0x0004 */
  79. u16 fpga_version; /* 0x0006 */
  80. u16 reserved_0[5]; /* 0x0008 */
  81. u16 quad_serdes_reset; /* 0x0012 */
  82. u16 reserved_1[8181]; /* 0x0014 */
  83. u16 reflection_high; /* 0x3ffe */
  84. };
  85. #endif
  86. #ifdef CONFIG_IO64
  87. struct ihs_fpga_channel {
  88. u16 status_int;
  89. u16 config_int;
  90. u16 switch_connect_config;
  91. u16 tx_destination;
  92. };
  93. struct ihs_fpga_hicb {
  94. u16 status_int;
  95. u16 config_int;
  96. };
  97. struct ihs_fpga {
  98. u16 reflection_low; /* 0x0000 */
  99. u16 versions; /* 0x0002 */
  100. u16 fpga_features; /* 0x0004 */
  101. u16 fpga_version; /* 0x0006 */
  102. u16 reserved_0[5]; /* 0x0008 */
  103. u16 quad_serdes_reset; /* 0x0012 */
  104. u16 reserved_1[502]; /* 0x0014 */
  105. struct ihs_fpga_channel ch[32]; /* 0x0400 */
  106. struct ihs_fpga_channel hicb_ch[32]; /* 0x0500 */
  107. u16 reserved_2[7487]; /* 0x0580 */
  108. u16 reflection_high; /* 0x3ffe */
  109. };
  110. #endif
  111. #ifdef CONFIG_IOCON
  112. struct ihs_fpga {
  113. u16 reflection_low; /* 0x0000 */
  114. u16 versions; /* 0x0002 */
  115. u16 fpga_version; /* 0x0004 */
  116. u16 fpga_features; /* 0x0006 */
  117. u16 reserved_0[1]; /* 0x0008 */
  118. u16 top_interrupt; /* 0x000a */
  119. u16 reserved_1[4]; /* 0x000c */
  120. struct ihs_gpio gpio; /* 0x0014 */
  121. u16 mpc3w_control; /* 0x001a */
  122. u16 reserved_2[2]; /* 0x001c */
  123. struct ihs_io_ep ep; /* 0x0020 */
  124. u16 reserved_3[9]; /* 0x002e */
  125. struct ihs_i2c i2c0; /* 0x0040 */
  126. u16 reserved_4[10]; /* 0x004c */
  127. u16 mc_int; /* 0x0060 */
  128. u16 mc_int_en; /* 0x0062 */
  129. u16 mc_status; /* 0x0064 */
  130. u16 mc_control; /* 0x0066 */
  131. u16 mc_tx_data; /* 0x0068 */
  132. u16 mc_tx_address; /* 0x006a */
  133. u16 mc_tx_cmd; /* 0x006c */
  134. u16 mc_res; /* 0x006e */
  135. u16 mc_rx_cmd_status; /* 0x0070 */
  136. u16 mc_rx_data; /* 0x0072 */
  137. u16 reserved_5[69]; /* 0x0074 */
  138. u16 reflection_high; /* 0x00fe */
  139. struct ihs_osd osd0; /* 0x0100 */
  140. u16 reserved_6[889]; /* 0x010e */
  141. u16 videomem0[2048]; /* 0x0800 */
  142. };
  143. #endif
  144. #if defined(CONFIG_HRCON) || defined(CONFIG_STRIDER_CON_DP)
  145. struct ihs_fpga {
  146. u16 reflection_low; /* 0x0000 */
  147. u16 versions; /* 0x0002 */
  148. u16 fpga_version; /* 0x0004 */
  149. u16 fpga_features; /* 0x0006 */
  150. u16 reserved_0[1]; /* 0x0008 */
  151. u16 top_interrupt; /* 0x000a */
  152. u16 reserved_1[2]; /* 0x000c */
  153. u16 control; /* 0x0010 */
  154. u16 extended_control; /* 0x0012 */
  155. struct ihs_gpio gpio; /* 0x0014 */
  156. u16 mpc3w_control; /* 0x001a */
  157. u16 reserved_2[2]; /* 0x001c */
  158. struct ihs_io_ep ep; /* 0x0020 */
  159. u16 reserved_3[9]; /* 0x002e */
  160. struct ihs_i2c i2c0; /* 0x0040 */
  161. u16 reserved_4[10]; /* 0x004c */
  162. u16 mc_int; /* 0x0060 */
  163. u16 mc_int_en; /* 0x0062 */
  164. u16 mc_status; /* 0x0064 */
  165. u16 mc_control; /* 0x0066 */
  166. u16 mc_tx_data; /* 0x0068 */
  167. u16 mc_tx_address; /* 0x006a */
  168. u16 mc_tx_cmd; /* 0x006c */
  169. u16 mc_res; /* 0x006e */
  170. u16 mc_rx_cmd_status; /* 0x0070 */
  171. u16 mc_rx_data; /* 0x0072 */
  172. u16 reserved_5[69]; /* 0x0074 */
  173. u16 reflection_high; /* 0x00fe */
  174. struct ihs_osd osd0; /* 0x0100 */
  175. #ifdef CONFIG_SYS_OSD_DH
  176. u16 reserved_6[57]; /* 0x010e */
  177. struct ihs_osd osd1; /* 0x0180 */
  178. u16 reserved_7[9]; /* 0x018e */
  179. struct ihs_i2c i2c1; /* 0x01a0 */
  180. u16 reserved_8[1834]; /* 0x01ac */
  181. u16 videomem0[2048]; /* 0x1000 */
  182. u16 videomem1[2048]; /* 0x2000 */
  183. #else
  184. u16 reserved_6[889]; /* 0x010e */
  185. u16 videomem0[2048]; /* 0x0800 */
  186. #endif
  187. };
  188. #endif
  189. #ifdef CONFIG_STRIDER_CPU
  190. struct ihs_fpga {
  191. u16 reflection_low; /* 0x0000 */
  192. u16 versions; /* 0x0002 */
  193. u16 fpga_version; /* 0x0004 */
  194. u16 fpga_features; /* 0x0006 */
  195. u16 reserved_0[1]; /* 0x0008 */
  196. u16 top_interrupt; /* 0x000a */
  197. u16 reserved_1[3]; /* 0x000c */
  198. u16 extended_control; /* 0x0012 */
  199. struct ihs_gpio gpio; /* 0x0014 */
  200. u16 mpc3w_control; /* 0x001a */
  201. u16 reserved_2[2]; /* 0x001c */
  202. struct ihs_io_ep ep; /* 0x0020 */
  203. u16 reserved_3[9]; /* 0x002e */
  204. u16 mc_int; /* 0x0040 */
  205. u16 mc_int_en; /* 0x0042 */
  206. u16 mc_status; /* 0x0044 */
  207. u16 mc_control; /* 0x0046 */
  208. u16 mc_tx_data; /* 0x0048 */
  209. u16 mc_tx_address; /* 0x004a */
  210. u16 mc_tx_cmd; /* 0x004c */
  211. u16 mc_res; /* 0x004e */
  212. u16 mc_rx_cmd_status; /* 0x0050 */
  213. u16 mc_rx_data; /* 0x0052 */
  214. u16 reserved_4[62]; /* 0x0054 */
  215. struct ihs_i2c i2c0; /* 0x00d0 */
  216. };
  217. #endif
  218. #ifdef CONFIG_STRIDER_CON
  219. struct ihs_fpga {
  220. u16 reflection_low; /* 0x0000 */
  221. u16 versions; /* 0x0002 */
  222. u16 fpga_version; /* 0x0004 */
  223. u16 fpga_features; /* 0x0006 */
  224. u16 reserved_0[1]; /* 0x0008 */
  225. u16 top_interrupt; /* 0x000a */
  226. u16 reserved_1[4]; /* 0x000c */
  227. struct ihs_gpio gpio; /* 0x0014 */
  228. u16 mpc3w_control; /* 0x001a */
  229. u16 reserved_2[2]; /* 0x001c */
  230. struct ihs_io_ep ep; /* 0x0020 */
  231. u16 reserved_3[9]; /* 0x002e */
  232. struct ihs_i2c i2c0; /* 0x0040 */
  233. u16 reserved_4[10]; /* 0x004c */
  234. u16 mc_int; /* 0x0060 */
  235. u16 mc_int_en; /* 0x0062 */
  236. u16 mc_status; /* 0x0064 */
  237. u16 mc_control; /* 0x0066 */
  238. u16 mc_tx_data; /* 0x0068 */
  239. u16 mc_tx_address; /* 0x006a */
  240. u16 mc_tx_cmd; /* 0x006c */
  241. u16 mc_res; /* 0x006e */
  242. u16 mc_rx_cmd_status; /* 0x0070 */
  243. u16 mc_rx_data; /* 0x0072 */
  244. u16 reserved_5[70]; /* 0x0074 */
  245. struct ihs_osd osd0; /* 0x0100 */
  246. u16 reserved_6[889]; /* 0x010e */
  247. u16 videomem0[2048]; /* 0x0800 */
  248. };
  249. #endif
  250. #ifdef CONFIG_DLVISION_10G
  251. struct ihs_fpga {
  252. u16 reflection_low; /* 0x0000 */
  253. u16 versions; /* 0x0002 */
  254. u16 fpga_version; /* 0x0004 */
  255. u16 fpga_features; /* 0x0006 */
  256. u16 reserved_0[10]; /* 0x0008 */
  257. u16 extended_interrupt; /* 0x001c */
  258. u16 reserved_1[29]; /* 0x001e */
  259. u16 mpc3w_control; /* 0x0058 */
  260. u16 reserved_2[3]; /* 0x005a */
  261. struct ihs_i2c i2c0; /* 0x0060 */
  262. u16 reserved_3[2]; /* 0x006c */
  263. struct ihs_i2c i2c1; /* 0x0070 */
  264. u16 reserved_4[194]; /* 0x007c */
  265. struct ihs_osd osd0; /* 0x0200 */
  266. u16 reserved_5[761]; /* 0x020e */
  267. u16 videomem0[2048]; /* 0x0800 */
  268. };
  269. #endif
  270. #endif