dw_hdmi.h 19 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (c) 2015 Google, Inc
  4. * Copyright 2014 Rockchip Inc.
  5. * Copyright (C) 2011 Freescale Semiconductor, Inc.
  6. * (C) Copyright 2017 Jernej Skrabec <jernej.skrabec@siol.net>
  7. */
  8. #ifndef _DW_HDMI_H
  9. #define _DW_HDMI_H
  10. #include <edid.h>
  11. #define HDMI_EDID_BLOCK_SIZE 128
  12. /* Identification Registers */
  13. #define HDMI_DESIGN_ID 0x0000
  14. #define HDMI_REVISION_ID 0x0001
  15. #define HDMI_PRODUCT_ID0 0x0002
  16. #define HDMI_PRODUCT_ID1 0x0003
  17. #define HDMI_CONFIG0_ID 0x0004
  18. #define HDMI_CONFIG1_ID 0x0005
  19. #define HDMI_CONFIG2_ID 0x0006
  20. #define HDMI_CONFIG3_ID 0x0007
  21. /* Interrupt Registers */
  22. #define HDMI_IH_FC_STAT0 0x0100
  23. #define HDMI_IH_FC_STAT1 0x0101
  24. #define HDMI_IH_FC_STAT2 0x0102
  25. #define HDMI_IH_AS_STAT0 0x0103
  26. #define HDMI_IH_PHY_STAT0 0x0104
  27. #define HDMI_IH_I2CM_STAT0 0x0105
  28. #define HDMI_IH_CEC_STAT0 0x0106
  29. #define HDMI_IH_VP_STAT0 0x0107
  30. #define HDMI_IH_I2CMPHY_STAT0 0x0108
  31. #define HDMI_IH_AHBDMAAUD_STAT0 0x0109
  32. #define HDMI_IH_MUTE_FC_STAT0 0x0180
  33. #define HDMI_IH_MUTE_FC_STAT1 0x0181
  34. #define HDMI_IH_MUTE_FC_STAT2 0x0182
  35. #define HDMI_IH_MUTE_AS_STAT0 0x0183
  36. #define HDMI_IH_MUTE_PHY_STAT0 0x0184
  37. #define HDMI_IH_MUTE_I2CM_STAT0 0x0185
  38. #define HDMI_IH_MUTE_CEC_STAT0 0x0186
  39. #define HDMI_IH_MUTE_VP_STAT0 0x0187
  40. #define HDMI_IH_MUTE_I2CMPHY_STAT0 0x0188
  41. #define HDMI_IH_MUTE_AHBDMAAUD_STAT0 0x0189
  42. #define HDMI_IH_MUTE 0x01FF
  43. /* Video Sample Registers */
  44. #define HDMI_TX_INVID0 0x0200
  45. #define HDMI_TX_INSTUFFING 0x0201
  46. #define HDMI_TX_GYDATA0 0x0202
  47. #define HDMI_TX_GYDATA1 0x0203
  48. #define HDMI_TX_RCRDATA0 0x0204
  49. #define HDMI_TX_RCRDATA1 0x0205
  50. #define HDMI_TX_BCBDATA0 0x0206
  51. #define HDMI_TX_BCBDATA1 0x0207
  52. /* Video Packetizer Registers */
  53. #define HDMI_VP_STATUS 0x0800
  54. #define HDMI_VP_PR_CD 0x0801
  55. #define HDMI_VP_STUFF 0x0802
  56. #define HDMI_VP_REMAP 0x0803
  57. #define HDMI_VP_CONF 0x0804
  58. #define HDMI_VP_STAT 0x0805
  59. #define HDMI_VP_INT 0x0806
  60. #define HDMI_VP_MASK 0x0807
  61. #define HDMI_VP_POL 0x0808
  62. /* Frame Composer Registers */
  63. #define HDMI_FC_INVIDCONF 0x1000
  64. #define HDMI_FC_INHACTV0 0x1001
  65. #define HDMI_FC_INHACTV1 0x1002
  66. #define HDMI_FC_INHBLANK0 0x1003
  67. #define HDMI_FC_INHBLANK1 0x1004
  68. #define HDMI_FC_INVACTV0 0x1005
  69. #define HDMI_FC_INVACTV1 0x1006
  70. #define HDMI_FC_INVBLANK 0x1007
  71. #define HDMI_FC_HSYNCINDELAY0 0x1008
  72. #define HDMI_FC_HSYNCINDELAY1 0x1009
  73. #define HDMI_FC_HSYNCINWIDTH0 0x100A
  74. #define HDMI_FC_HSYNCINWIDTH1 0x100B
  75. #define HDMI_FC_VSYNCINDELAY 0x100C
  76. #define HDMI_FC_VSYNCINWIDTH 0x100D
  77. #define HDMI_FC_INFREQ0 0x100E
  78. #define HDMI_FC_INFREQ1 0x100F
  79. #define HDMI_FC_INFREQ2 0x1010
  80. #define HDMI_FC_CTRLDUR 0x1011
  81. #define HDMI_FC_EXCTRLDUR 0x1012
  82. #define HDMI_FC_EXCTRLSPAC 0x1013
  83. #define HDMI_FC_CH0PREAM 0x1014
  84. #define HDMI_FC_CH1PREAM 0x1015
  85. #define HDMI_FC_CH2PREAM 0x1016
  86. #define HDMI_FC_AVICONF3 0x1017
  87. #define HDMI_FC_GCP 0x1018
  88. #define HDMI_FC_AVICONF0 0x1019
  89. #define HDMI_FC_AVICONF1 0x101A
  90. #define HDMI_FC_AVICONF2 0x101B
  91. #define HDMI_FC_AVIVID 0x101C
  92. #define HDMI_FC_AVIETB0 0x101D
  93. #define HDMI_FC_AVIETB1 0x101E
  94. #define HDMI_FC_AVISBB0 0x101F
  95. #define HDMI_FC_AVISBB1 0x1020
  96. #define HDMI_FC_AVIELB0 0x1021
  97. #define HDMI_FC_AVIELB1 0x1022
  98. #define HDMI_FC_AVISRB0 0x1023
  99. #define HDMI_FC_AVISRB1 0x1024
  100. #define HDMI_FC_AUDICONF0 0x1025
  101. #define HDMI_FC_AUDICONF1 0x1026
  102. #define HDMI_FC_AUDICONF2 0x1027
  103. #define HDMI_FC_AUDICONF3 0x1028
  104. #define HDMI_FC_VSDIEEEID0 0x1029
  105. #define HDMI_FC_VSDSIZE 0x102A
  106. /* HDMI Source PHY Registers */
  107. #define HDMI_PHY_CONF0 0x3000
  108. #define HDMI_PHY_TST0 0x3001
  109. #define HDMI_PHY_TST1 0x3002
  110. #define HDMI_PHY_TST2 0x3003
  111. #define HDMI_PHY_STAT0 0x3004
  112. #define HDMI_PHY_INT0 0x3005
  113. #define HDMI_PHY_MASK0 0x3006
  114. #define HDMI_PHY_POL0 0x3007
  115. /* HDMI Master PHY Registers */
  116. #define HDMI_PHY_I2CM_SLAVE_ADDR 0x3020
  117. #define HDMI_PHY_I2CM_ADDRESS_ADDR 0x3021
  118. #define HDMI_PHY_I2CM_DATAO_1_ADDR 0x3022
  119. #define HDMI_PHY_I2CM_DATAO_0_ADDR 0x3023
  120. #define HDMI_PHY_I2CM_DATAI_1_ADDR 0x3024
  121. #define HDMI_PHY_I2CM_DATAI_0_ADDR 0x3025
  122. #define HDMI_PHY_I2CM_OPERATION_ADDR 0x3026
  123. #define HDMI_PHY_I2CM_INT_ADDR 0x3027
  124. #define HDMI_PHY_I2CM_CTLINT_ADDR 0x3028
  125. #define HDMI_PHY_I2CM_DIV_ADDR 0x3029
  126. #define HDMI_PHY_I2CM_SOFTRSTZ_ADDR 0x302a
  127. #define HDMI_PHY_I2CM_SS_SCL_HCNT_1_ADDR 0x302b
  128. #define HDMI_PHY_I2CM_SS_SCL_HCNT_0_ADDR 0x302c
  129. #define HDMI_PHY_I2CM_SS_SCL_LCNT_1_ADDR 0x302d
  130. #define HDMI_PHY_I2CM_SS_SCL_LCNT_0_ADDR 0x302e
  131. #define HDMI_PHY_I2CM_FS_SCL_HCNT_1_ADDR 0x302f
  132. #define HDMI_PHY_I2CM_FS_SCL_HCNT_0_ADDR 0x3030
  133. #define HDMI_PHY_I2CM_FS_SCL_LCNT_1_ADDR 0x3031
  134. #define HDMI_PHY_I2CM_FS_SCL_LCNT_0_ADDR 0x3032
  135. /* Audio Sampler Registers */
  136. #define HDMI_AUD_CONF0 0x3100
  137. #define HDMI_AUD_CONF1 0x3101
  138. #define HDMI_AUD_INT 0x3102
  139. #define HDMI_AUD_CONF2 0x3103
  140. #define HDMI_AUD_INT1 0x3104
  141. #define HDMI_AUD_N1 0x3200
  142. #define HDMI_AUD_N2 0x3201
  143. #define HDMI_AUD_N3 0x3202
  144. #define HDMI_AUD_CTS1 0x3203
  145. #define HDMI_AUD_CTS2 0x3204
  146. #define HDMI_AUD_CTS3 0x3205
  147. #define HDMI_AUD_INPUTCLKFS 0x3206
  148. #define HDMI_AUD_SPDIFINT 0x3302
  149. #define HDMI_AUD_CONF0_HBR 0x3400
  150. #define HDMI_AUD_HBR_STATUS 0x3401
  151. #define HDMI_AUD_HBR_INT 0x3402
  152. #define HDMI_AUD_HBR_POL 0x3403
  153. #define HDMI_AUD_HBR_MASK 0x3404
  154. /* Main Controller Registers */
  155. #define HDMI_MC_SFRDIV 0x4000
  156. #define HDMI_MC_CLKDIS 0x4001
  157. #define HDMI_MC_SWRSTZ 0x4002
  158. #define HDMI_MC_OPCTRL 0x4003
  159. #define HDMI_MC_FLOWCTRL 0x4004
  160. #define HDMI_MC_PHYRSTZ 0x4005
  161. #define HDMI_MC_LOCKONCLOCK 0x4006
  162. #define HDMI_MC_HEACPHY_RST 0x4007
  163. /* I2C Master Registers (E-DDC) */
  164. #define HDMI_I2CM_SLAVE 0x7E00
  165. #define HDMI_I2CM_ADDRESS 0x7E01
  166. #define HDMI_I2CM_DATAO 0x7E02
  167. #define HDMI_I2CM_DATAI 0x7E03
  168. #define HDMI_I2CM_OPERATION 0x7E04
  169. #define HDMI_I2CM_INT 0x7E05
  170. #define HDMI_I2CM_CTLINT 0x7E06
  171. #define HDMI_I2CM_DIV 0x7E07
  172. #define HDMI_I2CM_SEGADDR 0x7E08
  173. #define HDMI_I2CM_SOFTRSTZ 0x7E09
  174. #define HDMI_I2CM_SEGPTR 0x7E0A
  175. #define HDMI_I2CM_SS_SCL_HCNT_1_ADDR 0x7E0B
  176. #define HDMI_I2CM_SS_SCL_HCNT_0_ADDR 0x7E0C
  177. #define HDMI_I2CM_SS_SCL_LCNT_1_ADDR 0x7E0D
  178. #define HDMI_I2CM_SS_SCL_LCNT_0_ADDR 0x7E0E
  179. #define HDMI_I2CM_FS_SCL_HCNT_1_ADDR 0x7E0F
  180. #define HDMI_I2CM_FS_SCL_HCNT_0_ADDR 0x7E10
  181. #define HDMI_I2CM_FS_SCL_LCNT_1_ADDR 0x7E11
  182. #define HDMI_I2CM_FS_SCL_LCNT_0_ADDR 0x7E12
  183. #define HDMI_I2CM_BUF0 0x7E20
  184. enum {
  185. /* HDMI PHY registers define */
  186. PHY_OPMODE_PLLCFG = 0x06,
  187. PHY_CKCALCTRL = 0x05,
  188. PHY_CKSYMTXCTRL = 0x09,
  189. PHY_VLEVCTRL = 0x0e,
  190. PHY_PLLCURRCTRL = 0x10,
  191. PHY_PLLPHBYCTRL = 0x13,
  192. PHY_PLLGMPCTRL = 0x15,
  193. PHY_PLLCLKBISTPHASE = 0x17,
  194. PHY_TXTERM = 0x19,
  195. /* ih_phy_stat0 field values */
  196. HDMI_IH_PHY_STAT0_HPD = 0x1,
  197. /* ih_mute field values */
  198. HDMI_IH_MUTE_MUTE_WAKEUP_INTERRUPT = 0x2,
  199. HDMI_IH_MUTE_MUTE_ALL_INTERRUPT = 0x1,
  200. /* tx_invid0 field values */
  201. HDMI_TX_INVID0_INTERNAL_DE_GENERATOR_DISABLE = 0x00,
  202. HDMI_TX_INVID0_VIDEO_MAPPING_MASK = 0x1f,
  203. HDMI_TX_INVID0_VIDEO_MAPPING_OFFSET = 0,
  204. /* tx_instuffing field values */
  205. HDMI_TX_INSTUFFING_BDBDATA_STUFFING_ENABLE = 0x4,
  206. HDMI_TX_INSTUFFING_RCRDATA_STUFFING_ENABLE = 0x2,
  207. HDMI_TX_INSTUFFING_GYDATA_STUFFING_ENABLE = 0x1,
  208. /* vp_pr_cd field values */
  209. HDMI_VP_PR_CD_COLOR_DEPTH_MASK = 0xf0,
  210. HDMI_VP_PR_CD_COLOR_DEPTH_OFFSET = 4,
  211. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_MASK = 0x0f,
  212. HDMI_VP_PR_CD_DESIRED_PR_FACTOR_OFFSET = 0,
  213. /* vp_stuff field values */
  214. HDMI_VP_STUFF_IDEFAULT_PHASE_MASK = 0x20,
  215. HDMI_VP_STUFF_IDEFAULT_PHASE_OFFSET = 5,
  216. HDMI_VP_STUFF_YCC422_STUFFING_MASK = 0x4,
  217. HDMI_VP_STUFF_YCC422_STUFFING_STUFFING_MODE = 0x4,
  218. HDMI_VP_STUFF_PP_STUFFING_MASK = 0x2,
  219. HDMI_VP_STUFF_PP_STUFFING_STUFFING_MODE = 0x2,
  220. HDMI_VP_STUFF_PR_STUFFING_MASK = 0x1,
  221. HDMI_VP_STUFF_PR_STUFFING_STUFFING_MODE = 0x1,
  222. /* vp_conf field values */
  223. HDMI_VP_CONF_BYPASS_EN_MASK = 0x40,
  224. HDMI_VP_CONF_BYPASS_EN_ENABLE = 0x40,
  225. HDMI_VP_CONF_PP_EN_ENMASK = 0x20,
  226. HDMI_VP_CONF_PP_EN_DISABLE = 0x00,
  227. HDMI_VP_CONF_PR_EN_MASK = 0x10,
  228. HDMI_VP_CONF_PR_EN_DISABLE = 0x00,
  229. HDMI_VP_CONF_YCC422_EN_MASK = 0x8,
  230. HDMI_VP_CONF_YCC422_EN_DISABLE = 0x0,
  231. HDMI_VP_CONF_BYPASS_SELECT_MASK = 0x4,
  232. HDMI_VP_CONF_BYPASS_SELECT_VID_PACKETIZER = 0x4,
  233. HDMI_VP_CONF_OUTPUT_SELECTOR_MASK = 0x3,
  234. HDMI_VP_CONF_OUTPUT_SELECTOR_BYPASS = 0x3,
  235. /* vp_remap field values */
  236. HDMI_VP_REMAP_YCC422_16BIT = 0x0,
  237. /* fc_invidconf field values */
  238. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_MASK = 0x80,
  239. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_ACTIVE = 0x80,
  240. HDMI_FC_INVIDCONF_HDCP_KEEPOUT_INACTIVE = 0x00,
  241. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_MASK = 0x40,
  242. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_HIGH = 0x40,
  243. HDMI_FC_INVIDCONF_VSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
  244. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_MASK = 0x20,
  245. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_HIGH = 0x20,
  246. HDMI_FC_INVIDCONF_HSYNC_IN_POLARITY_ACTIVE_LOW = 0x00,
  247. HDMI_FC_INVIDCONF_DE_IN_POLARITY_MASK = 0x10,
  248. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_HIGH = 0x10,
  249. HDMI_FC_INVIDCONF_DE_IN_POLARITY_ACTIVE_LOW = 0x00,
  250. HDMI_FC_INVIDCONF_DVI_MODEZ_MASK = 0x8,
  251. HDMI_FC_INVIDCONF_DVI_MODEZ_HDMI_MODE = 0x8,
  252. HDMI_FC_INVIDCONF_DVI_MODEZ_DVI_MODE = 0x0,
  253. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_MASK = 0x2,
  254. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_HIGH = 0x2,
  255. HDMI_FC_INVIDCONF_R_V_BLANK_IN_OSC_ACTIVE_LOW = 0x0,
  256. HDMI_FC_INVIDCONF_IN_I_P_MASK = 0x1,
  257. HDMI_FC_INVIDCONF_IN_I_P_INTERLACED = 0x1,
  258. HDMI_FC_INVIDCONF_IN_I_P_PROGRESSIVE = 0x0,
  259. /* fc_aviconf0-fc_aviconf3 field values */
  260. HDMI_FC_AVICONF0_PIX_FMT_MASK = 0x03,
  261. HDMI_FC_AVICONF0_PIX_FMT_RGB = 0x00,
  262. HDMI_FC_AVICONF0_PIX_FMT_YCBCR422 = 0x01,
  263. HDMI_FC_AVICONF0_PIX_FMT_YCBCR444 = 0x02,
  264. HDMI_FC_AVICONF0_ACTIVE_FMT_MASK = 0x40,
  265. HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT = 0x40,
  266. HDMI_FC_AVICONF0_ACTIVE_FMT_NO_INFO = 0x00,
  267. HDMI_FC_AVICONF0_BAR_DATA_MASK = 0x0c,
  268. HDMI_FC_AVICONF0_BAR_DATA_NO_DATA = 0x00,
  269. HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR = 0x04,
  270. HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR = 0x08,
  271. HDMI_FC_AVICONF0_BAR_DATA_VERT_HORIZ_BAR = 0x0c,
  272. HDMI_FC_AVICONF0_SCAN_INFO_MASK = 0x30,
  273. HDMI_FC_AVICONF0_SCAN_INFO_OVERSCAN = 0x10,
  274. HDMI_FC_AVICONF0_SCAN_INFO_UNDERSCAN = 0x20,
  275. HDMI_FC_AVICONF0_SCAN_INFO_NODATA = 0x00,
  276. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_MASK = 0x0f,
  277. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_USE_CODED = 0x08,
  278. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_4_3 = 0x09,
  279. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_16_9 = 0x0a,
  280. HDMI_FC_AVICONF1_ACTIVE_ASPECT_RATIO_14_9 = 0x0b,
  281. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_MASK = 0x30,
  282. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_NO_DATA = 0x00,
  283. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_4_3 = 0x10,
  284. HDMI_FC_AVICONF1_CODED_ASPECT_RATIO_16_9 = 0x20,
  285. HDMI_FC_AVICONF1_COLORIMETRY_MASK = 0xc0,
  286. HDMI_FC_AVICONF1_COLORIMETRY_NO_DATA = 0x00,
  287. HDMI_FC_AVICONF1_COLORIMETRY_SMPTE = 0x40,
  288. HDMI_FC_AVICONF1_COLORIMETRY_ITUR = 0x80,
  289. HDMI_FC_AVICONF1_COLORIMETRY_EXTENDED_INFO = 0xc0,
  290. HDMI_FC_AVICONF2_SCALING_MASK = 0x03,
  291. HDMI_FC_AVICONF2_SCALING_NONE = 0x00,
  292. HDMI_FC_AVICONF2_SCALING_HORIZ = 0x01,
  293. HDMI_FC_AVICONF2_SCALING_VERT = 0x02,
  294. HDMI_FC_AVICONF2_SCALING_HORIZ_vert = 0x03,
  295. HDMI_FC_AVICONF2_RGB_QUANT_MASK = 0x0c,
  296. HDMI_FC_AVICONF2_RGB_QUANT_DEFAULT = 0x00,
  297. HDMI_FC_AVICONF2_RGB_QUANT_LIMITED_RANGE = 0x04,
  298. HDMI_FC_AVICONF2_RGB_QUANT_FULL_RANGE = 0x08,
  299. HDMI_FC_AVICONF2_EXT_COLORIMETRY_MASK = 0x70,
  300. HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC601 = 0x00,
  301. HDMI_FC_AVICONF2_EXT_COLORIMETRY_XVYCC709 = 0x10,
  302. HDMI_FC_AVICONF2_EXT_COLORIMETRY_SYCC601 = 0x20,
  303. HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_YCC601 = 0x30,
  304. HDMI_FC_AVICONF2_EXT_COLORIMETRY_ADOBE_RGB = 0x40,
  305. HDMI_FC_AVICONF2_IT_CONTENT_MASK = 0x80,
  306. HDMI_FC_AVICONF2_IT_CONTENT_NO_DATA = 0x00,
  307. HDMI_FC_AVICONF2_IT_CONTENT_VALID = 0x80,
  308. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_MASK = 0x03,
  309. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GRAPHICS = 0x00,
  310. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_PHOTO = 0x01,
  311. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_CINEMA = 0x02,
  312. HDMI_FC_AVICONF3_IT_CONTENT_TYPE_GAME = 0x03,
  313. HDMI_FC_AVICONF3_QUANT_RANGE_MASK = 0x0c,
  314. HDMI_FC_AVICONF3_QUANT_RANGE_LIMITED = 0x00,
  315. HDMI_FC_AVICONF3_QUANT_RANGE_FULL = 0x04,
  316. /* fc_gcp field values*/
  317. HDMI_FC_GCP_SET_AVMUTE = 0x02,
  318. HDMI_FC_GCP_CLEAR_AVMUTE = 0x01,
  319. /* phy_conf0 field values */
  320. HDMI_PHY_CONF0_PDZ_MASK = 0x80,
  321. HDMI_PHY_CONF0_PDZ_OFFSET = 7,
  322. HDMI_PHY_CONF0_ENTMDS_MASK = 0x40,
  323. HDMI_PHY_CONF0_ENTMDS_OFFSET = 6,
  324. HDMI_PHY_CONF0_SPARECTRL_MASK = 0x20,
  325. HDMI_PHY_CONF0_SPARECTRL_OFFSET = 5,
  326. HDMI_PHY_CONF0_GEN2_PDDQ_MASK = 0x10,
  327. HDMI_PHY_CONF0_GEN2_PDDQ_OFFSET = 4,
  328. HDMI_PHY_CONF0_GEN2_TXPWRON_MASK = 0x8,
  329. HDMI_PHY_CONF0_GEN2_TXPWRON_OFFSET = 3,
  330. HDMI_PHY_CONF0_SELDATAENPOL_MASK = 0x2,
  331. HDMI_PHY_CONF0_SELDATAENPOL_OFFSET = 1,
  332. HDMI_PHY_CONF0_SELDIPIF_MASK = 0x1,
  333. HDMI_PHY_CONF0_SELDIPIF_OFFSET = 0,
  334. /* phy_tst0 field values */
  335. HDMI_PHY_TST0_TSTCLR_MASK = 0x20,
  336. HDMI_PHY_TST0_TSTCLR_OFFSET = 5,
  337. /* phy_stat0 field values */
  338. HDMI_PHY_HPD = 0x02,
  339. HDMI_PHY_TX_PHY_LOCK = 0x01,
  340. /* phy_i2cm_slave_addr field values */
  341. HDMI_PHY_I2CM_SLAVE_ADDR_PHY_GEN2 = 0x69,
  342. /* phy_i2cm_operation_addr field values */
  343. HDMI_PHY_I2CM_OPERATION_ADDR_WRITE = 0x10,
  344. /* hdmi_phy_i2cm_int_addr */
  345. HDMI_PHY_I2CM_INT_ADDR_DONE_POL = 0x08,
  346. /* hdmi_phy_i2cm_ctlint_addr */
  347. HDMI_PHY_I2CM_CTLINT_ADDR_NAC_POL = 0x80,
  348. HDMI_PHY_I2CM_CTLINT_ADDR_ARBITRATION_POL = 0x08,
  349. /* aud_conf0 field values */
  350. HDMI_AUD_CONF0_SW_AUDIO_FIFO_RST = 0x80,
  351. HDMI_AUD_CONF0_I2S_SELECT = 0x20,
  352. HDMI_AUD_CONF0_I2S_IN_EN_0 = 0x01,
  353. HDMI_AUD_CONF0_I2S_IN_EN_1 = 0x02,
  354. HDMI_AUD_CONF0_I2S_IN_EN_2 = 0x04,
  355. HDMI_AUD_CONF0_I2S_IN_EN_3 = 0x08,
  356. /* aud_conf0 field values */
  357. HDMI_AUD_CONF1_I2S_MODE_STANDARD_MODE = 0x0,
  358. HDMI_AUD_CONF1_I2S_WIDTH_16BIT = 0x10,
  359. /* aud_n3 field values */
  360. HDMI_AUD_N3_NCTS_ATOMIC_WRITE = 0x80,
  361. HDMI_AUD_N3_AUDN19_16_MASK = 0x0f,
  362. /* aud_cts3 field values */
  363. HDMI_AUD_CTS3_N_SHIFT_OFFSET = 5,
  364. HDMI_AUD_CTS3_N_SHIFT_MASK = 0xe0,
  365. HDMI_AUD_CTS3_N_SHIFT_1 = 0,
  366. HDMI_AUD_CTS3_N_SHIFT_16 = 0x20,
  367. HDMI_AUD_CTS3_N_SHIFT_32 = 0x40,
  368. HDMI_AUD_CTS3_N_SHIFT_64 = 0x60,
  369. HDMI_AUD_CTS3_N_SHIFT_128 = 0x80,
  370. HDMI_AUD_CTS3_N_SHIFT_256 = 0xa0,
  371. HDMI_AUD_CTS3_CTS_MANUAL = 0x10,
  372. HDMI_AUD_CTS3_AUDCTS19_16_MASK = 0x0f,
  373. /* aud_inputclkfs filed values */
  374. HDMI_AUD_INPUTCLKFS_128 = 0x0,
  375. /* mc_clkdis field values */
  376. HDMI_MC_CLKDIS_AUDCLK_DISABLE = 0x8,
  377. HDMI_MC_CLKDIS_TMDSCLK_DISABLE = 0x2,
  378. HDMI_MC_CLKDIS_PIXELCLK_DISABLE = 0x1,
  379. /* mc_swrstz field values */
  380. HDMI_MC_SWRSTZ_II2SSWRST_REQ = 0x08,
  381. HDMI_MC_SWRSTZ_TMDSSWRST_REQ = 0x02,
  382. /* mc_flowctrl field values */
  383. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_IN_PATH = 0x1,
  384. HDMI_MC_FLOWCTRL_FEED_THROUGH_OFF_CSC_BYPASS = 0x0,
  385. /* mc_phyrstz field values */
  386. HDMI_MC_PHYRSTZ_ASSERT = 0x0,
  387. HDMI_MC_PHYRSTZ_DEASSERT = 0x1,
  388. /* mc_heacphy_rst field values */
  389. HDMI_MC_HEACPHY_RST_ASSERT = 0x1,
  390. /* i2cm filed values */
  391. HDMI_I2CM_SLAVE_DDC_ADDR = 0x50,
  392. HDMI_I2CM_SEGADDR_DDC = 0x30,
  393. HDMI_I2CM_OP_RD8_EXT = 0x2,
  394. HDMI_I2CM_OP_RD8 = 0x1,
  395. HDMI_I2CM_DIV_FAST_STD_MODE = 0x8,
  396. HDMI_I2CM_DIV_FAST_MODE = 0x8,
  397. HDMI_I2CM_DIV_STD_MODE = 0x0,
  398. HDMI_I2CM_SOFTRSTZ_MASK = 0x1,
  399. };
  400. struct hdmi_mpll_config {
  401. u64 mpixelclock;
  402. /* Mode of Operation and PLL Dividers Control Register */
  403. u32 cpce;
  404. /* PLL Gmp Control Register */
  405. u32 gmp;
  406. /* PLL Current Control Register */
  407. u32 curr;
  408. };
  409. struct hdmi_phy_config {
  410. u64 mpixelclock;
  411. u32 sym_ctr; /* clock symbol and transmitter control */
  412. u32 term; /* transmission termination value */
  413. u32 vlev_ctr; /* voltage level control */
  414. };
  415. struct dw_hdmi {
  416. ulong ioaddr;
  417. const struct hdmi_mpll_config *mpll_cfg;
  418. const struct hdmi_phy_config *phy_cfg;
  419. u8 i2c_clk_high;
  420. u8 i2c_clk_low;
  421. u8 reg_io_width;
  422. int (*phy_set)(struct dw_hdmi *hdmi, uint mpixelclock);
  423. };
  424. int dw_hdmi_phy_cfg(struct dw_hdmi *hdmi, uint mpixelclock);
  425. int dw_hdmi_phy_wait_for_hpd(struct dw_hdmi *hdmi);
  426. void dw_hdmi_phy_init(struct dw_hdmi *hdmi);
  427. int dw_hdmi_enable(struct dw_hdmi *hdmi, const struct display_timing *edid);
  428. int dw_hdmi_read_edid(struct dw_hdmi *hdmi, u8 *buf, int buf_size);
  429. void dw_hdmi_init(struct dw_hdmi *hdmi);
  430. #endif