ahci.h 8.8 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) Freescale Semiconductor, Inc. 2006.
  4. * Author: Jason Jin<Jason.jin@freescale.com>
  5. * Zhang Wei<wei.zhang@freescale.com>
  6. */
  7. #ifndef _AHCI_H_
  8. #define _AHCI_H_
  9. #include <pci.h>
  10. #define AHCI_PCI_BAR 0x24
  11. #define AHCI_MAX_SG 56 /* hardware max is 64K */
  12. #define AHCI_CMD_SLOT_SZ 32
  13. #define AHCI_MAX_CMD_SLOT 32
  14. #define AHCI_RX_FIS_SZ 256
  15. #define AHCI_CMD_TBL_HDR 0x80
  16. #define AHCI_CMD_TBL_CDB 0x40
  17. #define AHCI_CMD_TBL_SZ AHCI_CMD_TBL_HDR + (AHCI_MAX_SG * 16)
  18. #define AHCI_PORT_PRIV_DMA_SZ (AHCI_CMD_SLOT_SZ * AHCI_MAX_CMD_SLOT + \
  19. AHCI_CMD_TBL_SZ + AHCI_RX_FIS_SZ)
  20. #define AHCI_CMD_ATAPI (1 << 5)
  21. #define AHCI_CMD_WRITE (1 << 6)
  22. #define AHCI_CMD_PREFETCH (1 << 7)
  23. #define AHCI_CMD_RESET (1 << 8)
  24. #define AHCI_CMD_CLR_BUSY (1 << 10)
  25. #define RX_FIS_D2H_REG 0x40 /* offset of D2H Register FIS data */
  26. /* Global controller registers */
  27. #define HOST_CAP 0x00 /* host capabilities */
  28. #define HOST_CTL 0x04 /* global host control */
  29. #define HOST_IRQ_STAT 0x08 /* interrupt status */
  30. #define HOST_PORTS_IMPL 0x0c /* bitmap of implemented ports */
  31. #define HOST_VERSION 0x10 /* AHCI spec. version compliancy */
  32. #define HOST_CAP2 0x24 /* host capabilities, extended */
  33. /* HOST_CTL bits */
  34. #define HOST_RESET (1 << 0) /* reset controller; self-clear */
  35. #define HOST_IRQ_EN (1 << 1) /* global IRQ enable */
  36. #define HOST_AHCI_EN (1 << 31) /* AHCI enabled */
  37. /* Registers for each SATA port */
  38. #define PORT_LST_ADDR 0x00 /* command list DMA addr */
  39. #define PORT_LST_ADDR_HI 0x04 /* command list DMA addr hi */
  40. #define PORT_FIS_ADDR 0x08 /* FIS rx buf addr */
  41. #define PORT_FIS_ADDR_HI 0x0c /* FIS rx buf addr hi */
  42. #define PORT_IRQ_STAT 0x10 /* interrupt status */
  43. #define PORT_IRQ_MASK 0x14 /* interrupt enable/disable mask */
  44. #define PORT_CMD 0x18 /* port command */
  45. #define PORT_TFDATA 0x20 /* taskfile data */
  46. #define PORT_SIG 0x24 /* device TF signature */
  47. #define PORT_CMD_ISSUE 0x38 /* command issue */
  48. #define PORT_SCR 0x28 /* SATA phy register block */
  49. #define PORT_SCR_STAT 0x28 /* SATA phy register: SStatus */
  50. #define PORT_SCR_CTL 0x2c /* SATA phy register: SControl */
  51. #define PORT_SCR_ERR 0x30 /* SATA phy register: SError */
  52. #define PORT_SCR_ACT 0x34 /* SATA phy register: SActive */
  53. #ifdef CONFIG_SUNXI_AHCI
  54. #define PORT_P0DMACR 0x70 /* SUNXI specific "DMA register" */
  55. #endif
  56. /* PORT_IRQ_{STAT,MASK} bits */
  57. #define PORT_IRQ_COLD_PRES (1 << 31) /* cold presence detect */
  58. #define PORT_IRQ_TF_ERR (1 << 30) /* task file error */
  59. #define PORT_IRQ_HBUS_ERR (1 << 29) /* host bus fatal error */
  60. #define PORT_IRQ_HBUS_DATA_ERR (1 << 28) /* host bus data error */
  61. #define PORT_IRQ_IF_ERR (1 << 27) /* interface fatal error */
  62. #define PORT_IRQ_IF_NONFATAL (1 << 26) /* interface non-fatal error */
  63. #define PORT_IRQ_OVERFLOW (1 << 24) /* xfer exhausted available S/G */
  64. #define PORT_IRQ_BAD_PMP (1 << 23) /* incorrect port multiplier */
  65. #define PORT_IRQ_PHYRDY (1 << 22) /* PhyRdy changed */
  66. #define PORT_IRQ_DEV_ILCK (1 << 7) /* device interlock */
  67. #define PORT_IRQ_CONNECT (1 << 6) /* port connect change status */
  68. #define PORT_IRQ_SG_DONE (1 << 5) /* descriptor processed */
  69. #define PORT_IRQ_UNK_FIS (1 << 4) /* unknown FIS rx'd */
  70. #define PORT_IRQ_SDB_FIS (1 << 3) /* Set Device Bits FIS rx'd */
  71. #define PORT_IRQ_DMAS_FIS (1 << 2) /* DMA Setup FIS rx'd */
  72. #define PORT_IRQ_PIOS_FIS (1 << 1) /* PIO Setup FIS rx'd */
  73. #define PORT_IRQ_D2H_REG_FIS (1 << 0) /* D2H Register FIS rx'd */
  74. #define PORT_IRQ_FATAL PORT_IRQ_TF_ERR | PORT_IRQ_HBUS_ERR \
  75. | PORT_IRQ_HBUS_DATA_ERR | PORT_IRQ_IF_ERR
  76. #define DEF_PORT_IRQ PORT_IRQ_FATAL | PORT_IRQ_PHYRDY \
  77. | PORT_IRQ_CONNECT | PORT_IRQ_SG_DONE \
  78. | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_FIS \
  79. | PORT_IRQ_DMAS_FIS | PORT_IRQ_PIOS_FIS \
  80. | PORT_IRQ_D2H_REG_FIS
  81. /* PORT_SCR_STAT bits */
  82. #define PORT_SCR_STAT_DET_MASK 0x3
  83. #define PORT_SCR_STAT_DET_COMINIT 0x1
  84. #define PORT_SCR_STAT_DET_PHYRDY 0x3
  85. /* PORT_CMD bits */
  86. #define PORT_CMD_ATAPI (1 << 24) /* Device is ATAPI */
  87. #define PORT_CMD_LIST_ON (1 << 15) /* cmd list DMA engine running */
  88. #define PORT_CMD_FIS_ON (1 << 14) /* FIS DMA engine running */
  89. #define PORT_CMD_FIS_RX (1 << 4) /* Enable FIS receive DMA engine */
  90. #define PORT_CMD_CLO (1 << 3) /* Command list override */
  91. #define PORT_CMD_POWER_ON (1 << 2) /* Power up device */
  92. #define PORT_CMD_SPIN_UP (1 << 1) /* Spin up device */
  93. #define PORT_CMD_START (1 << 0) /* Enable port DMA engine */
  94. #define PORT_CMD_ICC_ACTIVE (0x1 << 28) /* Put i/f in active state */
  95. #define PORT_CMD_ICC_PARTIAL (0x2 << 28) /* Put i/f in partial state */
  96. #define PORT_CMD_ICC_SLUMBER (0x6 << 28) /* Put i/f in slumber state */
  97. #define AHCI_MAX_PORTS 32
  98. #define ATA_FLAG_SATA (1 << 3)
  99. #define ATA_FLAG_NO_LEGACY (1 << 4) /* no legacy mode check */
  100. #define ATA_FLAG_MMIO (1 << 6) /* use MMIO, not PIO */
  101. #define ATA_FLAG_SATA_RESET (1 << 7) /* (obsolete) use COMRESET */
  102. #define ATA_FLAG_PIO_DMA (1 << 8) /* PIO cmds via DMA */
  103. #define ATA_FLAG_NO_ATAPI (1 << 11) /* No ATAPI support */
  104. struct ahci_cmd_hdr {
  105. u32 opts;
  106. u32 status;
  107. u32 tbl_addr;
  108. u32 tbl_addr_hi;
  109. u32 reserved[4];
  110. };
  111. struct ahci_sg {
  112. u32 addr;
  113. u32 addr_hi;
  114. u32 reserved;
  115. u32 flags_size;
  116. };
  117. struct ahci_ioports {
  118. void __iomem *cmd_addr;
  119. void __iomem *scr_addr;
  120. void __iomem *port_mmio;
  121. struct ahci_cmd_hdr *cmd_slot;
  122. struct ahci_sg *cmd_tbl_sg;
  123. ulong cmd_tbl;
  124. u32 rx_fis;
  125. };
  126. /**
  127. * struct ahci_uc_priv - information about an AHCI controller
  128. *
  129. * When driver model is used, this is accessible using dev_get_uclass_priv(dev)
  130. * where dev is the controller (although at present it sometimes stands alone).
  131. */
  132. struct ahci_uc_priv {
  133. #if defined(CONFIG_DM_PCI) || defined(CONFIG_DM_SCSI)
  134. /*
  135. * TODO(sjg@chromium.org): Drop this once this structure is only used
  136. * in a driver-model context (i.e. attached to a device with
  137. * dev_get_uclass_priv()
  138. */
  139. struct udevice *dev;
  140. #else
  141. pci_dev_t dev;
  142. #endif
  143. struct ahci_ioports port[AHCI_MAX_PORTS];
  144. u16 *ataid[AHCI_MAX_PORTS];
  145. u32 n_ports;
  146. u32 hard_port_no;
  147. u32 host_flags;
  148. u32 host_set_flags;
  149. void __iomem *mmio_base;
  150. u32 pio_mask;
  151. u32 udma_mask;
  152. u32 flags;
  153. u32 cap; /* cache of HOST_CAP register */
  154. u32 port_map; /* cache of HOST_PORTS_IMPL reg */
  155. u32 link_port_map; /*linkup port map*/
  156. };
  157. struct ahci_ops {
  158. /**
  159. * reset() - reset the controller
  160. *
  161. * @dev: Controller to reset
  162. * @return 0 if OK, -ve on error
  163. */
  164. int (*reset)(struct udevice *dev);
  165. /**
  166. * port_status() - get the status of a SATA port
  167. *
  168. * @dev: Controller to reset
  169. * @port: Port number to check (0 for first)
  170. * @return 0 if detected, -ENXIO if nothing on port, other -ve on error
  171. */
  172. int (*port_status)(struct udevice *dev, int port);
  173. /**
  174. * scan() - scan SATA ports
  175. *
  176. * @dev: Controller to scan
  177. * @return 0 if OK, -ve on error
  178. */
  179. int (*scan)(struct udevice *dev);
  180. };
  181. #define ahci_get_ops(dev) ((struct ahci_ops *)(dev)->driver->ops)
  182. /**
  183. * sata_reset() - reset the controller
  184. *
  185. * @dev: Controller to reset
  186. * @return 0 if OK, -ve on error
  187. */
  188. int sata_reset(struct udevice *dev);
  189. /**
  190. * sata_port_status() - get the status of a SATA port
  191. *
  192. * @dev: Controller to reset
  193. * @port: Port number to check (0 for first)
  194. * @return 0 if detected, -ENXIO if nothin on port, other -ve on error
  195. */
  196. int sata_dm_port_status(struct udevice *dev, int port);
  197. /**
  198. * sata_scan() - scan SATA ports
  199. *
  200. * @dev: Controller to scan
  201. * @return 0 if OK, -ve on error
  202. */
  203. int sata_scan(struct udevice *dev);
  204. int ahci_init(void __iomem *base);
  205. int ahci_reset(void __iomem *base);
  206. /**
  207. * ahci_init_one_dm() - set up a single AHCI port
  208. *
  209. * @dev: Controller to init
  210. */
  211. int ahci_init_one_dm(struct udevice *dev);
  212. /**
  213. * ahci_start_ports_dm() - start all AHCI ports for a controller
  214. *
  215. * @dev: Controller containing ports to start
  216. */
  217. int ahci_start_ports_dm(struct udevice *dev);
  218. /**
  219. * ahci_init_dm() - init AHCI for a controller, finding all ports
  220. *
  221. * @dev: Device to init
  222. */
  223. int ahci_init_dm(struct udevice *dev, void __iomem *base);
  224. /**
  225. * ahci_bind_scsi() - bind a new SCSI bus as a child
  226. *
  227. * Note that the SCSI bus device will itself bind block devices
  228. *
  229. * @ahci_dev: AHCI parent device
  230. * @devp: Returns new SCSI bus device
  231. * @return 0 if OK, -ve on error
  232. */
  233. int ahci_bind_scsi(struct udevice *ahci_dev, struct udevice **devp);
  234. /**
  235. * ahci_probe_scsi() - probe and scan the attached SCSI bus
  236. *
  237. * Note that the SCSI device will itself bind block devices for any storage
  238. * devices it finds.
  239. *
  240. * @ahci_dev: AHCI parent device
  241. * @base: Base address of AHCI port
  242. * @return 0 if OK, -ve on error
  243. */
  244. int ahci_probe_scsi(struct udevice *ahci_dev, ulong base);
  245. /**
  246. * ahci_probe_scsi_pci() - probe and scan the attached SCSI bus on PCI
  247. *
  248. * Note that the SCSI device will itself bind block devices for any storage
  249. * devices it finds.
  250. *
  251. * @ahci_dev: AHCI parent device
  252. * @return 0 if OK, -ve on error
  253. */
  254. int ahci_probe_scsi_pci(struct udevice *ahci_dev);
  255. #endif