anx6345.c 10.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Vasily Khoruzhick <anarsoul@gmail.com>
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <errno.h>
  8. #include <i2c.h>
  9. #include <edid.h>
  10. #include <video_bridge.h>
  11. #include "../anx98xx-edp.h"
  12. #define DP_MAX_LINK_RATE 0x001
  13. #define DP_MAX_LANE_COUNT 0x002
  14. #define DP_MAX_LANE_COUNT_MASK 0x1f
  15. struct anx6345_priv {
  16. u8 edid[EDID_SIZE];
  17. };
  18. static int anx6345_write(struct udevice *dev, unsigned int addr_off,
  19. unsigned char reg_addr, unsigned char value)
  20. {
  21. uint8_t buf[2];
  22. struct i2c_msg msg;
  23. int ret;
  24. msg.addr = addr_off;
  25. msg.flags = 0;
  26. buf[0] = reg_addr;
  27. buf[1] = value;
  28. msg.buf = buf;
  29. msg.len = 2;
  30. ret = dm_i2c_xfer(dev, &msg, 1);
  31. if (ret) {
  32. debug("%s: write failed, reg=%#x, value=%#x, ret=%d\n",
  33. __func__, reg_addr, value, ret);
  34. return ret;
  35. }
  36. return 0;
  37. }
  38. static int anx6345_read(struct udevice *dev, unsigned int addr_off,
  39. unsigned char reg_addr, unsigned char *value)
  40. {
  41. uint8_t addr, val;
  42. struct i2c_msg msg[2];
  43. int ret;
  44. msg[0].addr = addr_off;
  45. msg[0].flags = 0;
  46. addr = reg_addr;
  47. msg[0].buf = &addr;
  48. msg[0].len = 1;
  49. msg[1].addr = addr_off;
  50. msg[1].flags = I2C_M_RD;
  51. msg[1].buf = &val;
  52. msg[1].len = 1;
  53. ret = dm_i2c_xfer(dev, msg, 2);
  54. if (ret) {
  55. debug("%s: read failed, reg=%.2x, value=%p, ret=%d\n",
  56. __func__, (int)reg_addr, value, ret);
  57. return ret;
  58. }
  59. *value = val;
  60. return 0;
  61. }
  62. static int anx6345_write_r0(struct udevice *dev, unsigned char reg_addr,
  63. unsigned char value)
  64. {
  65. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  66. return anx6345_write(dev, chip->chip_addr, reg_addr, value);
  67. }
  68. static int anx6345_read_r0(struct udevice *dev, unsigned char reg_addr,
  69. unsigned char *value)
  70. {
  71. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  72. return anx6345_read(dev, chip->chip_addr, reg_addr, value);
  73. }
  74. static int anx6345_write_r1(struct udevice *dev, unsigned char reg_addr,
  75. unsigned char value)
  76. {
  77. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  78. return anx6345_write(dev, chip->chip_addr + 1, reg_addr, value);
  79. }
  80. static int anx6345_read_r1(struct udevice *dev, unsigned char reg_addr,
  81. unsigned char *value)
  82. {
  83. struct dm_i2c_chip *chip = dev_get_parent_platdata(dev);
  84. return anx6345_read(dev, chip->chip_addr + 1, reg_addr, value);
  85. }
  86. static int anx6345_set_backlight(struct udevice *dev, int percent)
  87. {
  88. return -ENOSYS;
  89. }
  90. static int anx6345_aux_wait(struct udevice *dev)
  91. {
  92. int ret = -ETIMEDOUT;
  93. u8 v;
  94. int retries = 1000;
  95. do {
  96. anx6345_read_r0(dev, ANX9804_DP_AUX_CH_CTL_2, &v);
  97. if (!(v & ANX9804_AUX_EN)) {
  98. ret = 0;
  99. break;
  100. }
  101. udelay(100);
  102. } while (retries--);
  103. if (ret) {
  104. debug("%s: timed out waiting for AUX_EN to clear\n", __func__);
  105. return ret;
  106. }
  107. ret = -ETIMEDOUT;
  108. retries = 1000;
  109. do {
  110. anx6345_read_r1(dev, ANX9804_DP_INT_STA, &v);
  111. if (v & ANX9804_RPLY_RECEIV) {
  112. ret = 0;
  113. break;
  114. }
  115. udelay(100);
  116. } while (retries--);
  117. if (ret) {
  118. debug("%s: timed out waiting to receive reply\n", __func__);
  119. return ret;
  120. }
  121. /* Clear RPLY_RECEIV bit */
  122. anx6345_write_r1(dev, ANX9804_DP_INT_STA, v);
  123. anx6345_read_r0(dev, ANX9804_AUX_CH_STA, &v);
  124. if ((v & ANX9804_AUX_STATUS_MASK) != 0) {
  125. debug("AUX status: %d\n", v & ANX9804_AUX_STATUS_MASK);
  126. ret = -EIO;
  127. }
  128. return ret;
  129. }
  130. static void anx6345_aux_addr(struct udevice *dev, u32 addr)
  131. {
  132. u8 val;
  133. val = addr & 0xff;
  134. anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_7_0, val);
  135. val = (addr >> 8) & 0xff;
  136. anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_15_8, val);
  137. val = (addr >> 16) & 0x0f;
  138. anx6345_write_r0(dev, ANX9804_DP_AUX_ADDR_19_16, val);
  139. }
  140. static int anx6345_aux_transfer(struct udevice *dev, u8 req,
  141. u32 addr, u8 *buf, size_t len)
  142. {
  143. int i, ret;
  144. u8 ctrl1 = req;
  145. u8 ctrl2 = ANX9804_AUX_EN;
  146. if (len > 16)
  147. return -E2BIG;
  148. if (len)
  149. ctrl1 |= ANX9804_AUX_LENGTH(len);
  150. else
  151. ctrl2 |= ANX9804_ADDR_ONLY;
  152. if (len && !(req & ANX9804_AUX_TX_COMM_READ)) {
  153. for (i = 0; i < len; i++)
  154. anx6345_write_r0(dev, ANX9804_BUF_DATA_0 + i, buf[i]);
  155. }
  156. anx6345_aux_addr(dev, addr);
  157. anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_1, ctrl1);
  158. anx6345_write_r0(dev, ANX9804_DP_AUX_CH_CTL_2, ctrl2);
  159. ret = anx6345_aux_wait(dev);
  160. if (ret) {
  161. debug("AUX transaction timed out\n");
  162. return ret;
  163. }
  164. if (len && (req & ANX9804_AUX_TX_COMM_READ)) {
  165. for (i = 0; i < len; i++)
  166. anx6345_read_r0(dev, ANX9804_BUF_DATA_0 + i, &buf[i]);
  167. }
  168. return 0;
  169. }
  170. static int anx6345_read_aux_i2c(struct udevice *dev, u8 chip_addr,
  171. u8 offset, size_t count, u8 *buf)
  172. {
  173. int i, ret;
  174. size_t cur_cnt;
  175. u8 cur_offset;
  176. for (i = 0; i < count; i += 16) {
  177. cur_cnt = (count - i) > 16 ? 16 : count - i;
  178. cur_offset = offset + i;
  179. ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_MOT,
  180. chip_addr, &cur_offset, 1);
  181. if (ret) {
  182. debug("%s: failed to set i2c offset: %d\n",
  183. __func__, ret);
  184. return ret;
  185. }
  186. ret = anx6345_aux_transfer(dev, ANX9804_AUX_TX_COMM_READ,
  187. chip_addr, buf + i, cur_cnt);
  188. if (ret) {
  189. debug("%s: failed to read from i2c device: %d\n",
  190. __func__, ret);
  191. return ret;
  192. }
  193. }
  194. return 0;
  195. }
  196. static int anx6345_read_dpcd(struct udevice *dev, u32 reg, u8 *val)
  197. {
  198. int ret;
  199. ret = anx6345_aux_transfer(dev,
  200. ANX9804_AUX_TX_COMM_READ |
  201. ANX9804_AUX_TX_COMM_DP_TRANSACTION,
  202. reg, val, 1);
  203. if (ret) {
  204. debug("Failed to read DPCD\n");
  205. return ret;
  206. }
  207. return 0;
  208. }
  209. static int anx6345_read_edid(struct udevice *dev, u8 *buf, int size)
  210. {
  211. struct anx6345_priv *priv = dev_get_priv(dev);
  212. if (size > EDID_SIZE)
  213. size = EDID_SIZE;
  214. memcpy(buf, priv->edid, size);
  215. return size;
  216. }
  217. static int anx6345_attach(struct udevice *dev)
  218. {
  219. /* No-op */
  220. return 0;
  221. }
  222. static int anx6345_enable(struct udevice *dev)
  223. {
  224. u8 chipid, colordepth, lanes, data_rate, c;
  225. int ret, i, bpp;
  226. struct display_timing timing;
  227. struct anx6345_priv *priv = dev_get_priv(dev);
  228. /* Deassert reset and enable power */
  229. ret = video_bridge_set_active(dev, true);
  230. if (ret)
  231. return ret;
  232. /* Reset */
  233. anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 1);
  234. mdelay(100);
  235. anx6345_write_r1(dev, ANX9804_RST_CTRL_REG, 0);
  236. /* Write 0 to the powerdown reg (powerup everything) */
  237. anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, 0);
  238. ret = anx6345_read_r1(dev, ANX9804_DEV_IDH_REG, &chipid);
  239. if (ret)
  240. debug("%s: read id failed: %d\n", __func__, ret);
  241. switch (chipid) {
  242. case 0x63:
  243. debug("ANX63xx detected.\n");
  244. break;
  245. default:
  246. debug("Error anx6345 chipid mismatch: %.2x\n", (int)chipid);
  247. return -ENODEV;
  248. }
  249. for (i = 0; i < 100; i++) {
  250. anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
  251. anx6345_write_r0(dev, ANX9804_SYS_CTRL2_REG, c);
  252. anx6345_read_r0(dev, ANX9804_SYS_CTRL2_REG, &c);
  253. if ((c & ANX9804_SYS_CTRL2_CHA_STA) == 0)
  254. break;
  255. mdelay(5);
  256. }
  257. if (i == 100)
  258. debug("Error anx6345 clock is not stable\n");
  259. /* Set a bunch of analog related register values */
  260. anx6345_write_r0(dev, ANX9804_PLL_CTRL_REG, 0x00);
  261. anx6345_write_r1(dev, ANX9804_ANALOG_DEBUG_REG1, 0x70);
  262. anx6345_write_r0(dev, ANX9804_LINK_DEBUG_REG, 0x30);
  263. /* Force HPD */
  264. anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
  265. ANX9804_SYS_CTRL3_F_HPD | ANX9804_SYS_CTRL3_HPD_CTRL);
  266. /* Power up and configure lanes */
  267. anx6345_write_r0(dev, ANX9804_ANALOG_POWER_DOWN_REG, 0x00);
  268. anx6345_write_r0(dev, ANX9804_TRAINING_LANE0_SET_REG, 0x00);
  269. anx6345_write_r0(dev, ANX9804_TRAINING_LANE1_SET_REG, 0x00);
  270. anx6345_write_r0(dev, ANX9804_TRAINING_LANE2_SET_REG, 0x00);
  271. anx6345_write_r0(dev, ANX9804_TRAINING_LANE3_SET_REG, 0x00);
  272. /* Reset AUX CH */
  273. anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG,
  274. ANX9804_RST_CTRL2_AUX);
  275. anx6345_write_r1(dev, ANX9804_RST_CTRL2_REG, 0);
  276. /* Powerdown audio and some other unused bits */
  277. anx6345_write_r1(dev, ANX9804_POWERD_CTRL_REG, ANX9804_POWERD_AUDIO);
  278. anx6345_write_r0(dev, ANX9804_HDCP_CONTROL_0_REG, 0x00);
  279. anx6345_write_r0(dev, 0xa7, 0x00);
  280. anx6345_read_aux_i2c(dev, 0x50, 0x0, EDID_SIZE, priv->edid);
  281. if (edid_get_timing(priv->edid, EDID_SIZE, &timing, &bpp) != 0) {
  282. debug("Failed to parse EDID\n");
  283. return -EIO;
  284. }
  285. debug("%s: panel found: %dx%d, bpp %d\n", __func__,
  286. timing.hactive.typ, timing.vactive.typ, bpp);
  287. if (bpp == 6)
  288. colordepth = 0x00; /* 6 bit */
  289. else
  290. colordepth = 0x10; /* 8 bit */
  291. anx6345_write_r1(dev, ANX9804_VID_CTRL2_REG, colordepth);
  292. if (anx6345_read_dpcd(dev, DP_MAX_LINK_RATE, &data_rate)) {
  293. debug("%s: Failed to DP_MAX_LINK_RATE\n", __func__);
  294. return -EIO;
  295. }
  296. debug("%s: data_rate: %d\n", __func__, (int)data_rate);
  297. if (anx6345_read_dpcd(dev, DP_MAX_LANE_COUNT, &lanes)) {
  298. debug("%s: Failed to read DP_MAX_LANE_COUNT\n", __func__);
  299. return -EIO;
  300. }
  301. lanes &= DP_MAX_LANE_COUNT_MASK;
  302. debug("%s: lanes: %d\n", __func__, (int)lanes);
  303. /* Set data-rate / lanes */
  304. anx6345_write_r0(dev, ANX9804_LINK_BW_SET_REG, data_rate);
  305. anx6345_write_r0(dev, ANX9804_LANE_COUNT_SET_REG, lanes);
  306. /* Link training */
  307. anx6345_write_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG,
  308. ANX9804_LINK_TRAINING_CTRL_EN);
  309. mdelay(5);
  310. for (i = 0; i < 100; i++) {
  311. anx6345_read_r0(dev, ANX9804_LINK_TRAINING_CTRL_REG, &c);
  312. if ((chipid == 0x63) && (c & 0x80) == 0)
  313. break;
  314. mdelay(5);
  315. }
  316. if (i == 100) {
  317. debug("Error anx6345 link training timeout\n");
  318. return -ENODEV;
  319. }
  320. /* Enable */
  321. anx6345_write_r1(dev, ANX9804_VID_CTRL1_REG,
  322. ANX9804_VID_CTRL1_VID_EN | ANX9804_VID_CTRL1_EDGE);
  323. /* Force stream valid */
  324. anx6345_write_r0(dev, ANX9804_SYS_CTRL3_REG,
  325. ANX9804_SYS_CTRL3_F_HPD |
  326. ANX9804_SYS_CTRL3_HPD_CTRL |
  327. ANX9804_SYS_CTRL3_F_VALID |
  328. ANX9804_SYS_CTRL3_VALID_CTRL);
  329. return 0;
  330. }
  331. static int anx6345_probe(struct udevice *dev)
  332. {
  333. if (device_get_uclass_id(dev->parent) != UCLASS_I2C)
  334. return -EPROTONOSUPPORT;
  335. return anx6345_enable(dev);
  336. }
  337. struct video_bridge_ops anx6345_ops = {
  338. .attach = anx6345_attach,
  339. .set_backlight = anx6345_set_backlight,
  340. .read_edid = anx6345_read_edid,
  341. };
  342. static const struct udevice_id anx6345_ids[] = {
  343. { .compatible = "analogix,anx6345", },
  344. { }
  345. };
  346. U_BOOT_DRIVER(analogix_anx6345) = {
  347. .name = "analogix_anx6345",
  348. .id = UCLASS_VIDEO_BRIDGE,
  349. .of_match = anx6345_ids,
  350. .probe = anx6345_probe,
  351. .ops = &anx6345_ops,
  352. .priv_auto_alloc_size = sizeof(struct anx6345_priv),
  353. };