xhci.c 42 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB HOST XHCI Controller stack
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. /**
  16. * This file gives the xhci stack for usb3.0 looking into
  17. * xhci specification Rev1.0 (5/21/10).
  18. * The quirk devices support hasn't been given yet.
  19. */
  20. #include <common.h>
  21. #include <dm.h>
  22. #include <asm/byteorder.h>
  23. #include <usb.h>
  24. #include <malloc.h>
  25. #include <watchdog.h>
  26. #include <asm/cache.h>
  27. #include <asm/unaligned.h>
  28. #include <linux/errno.h>
  29. #include "xhci.h"
  30. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  31. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  32. #endif
  33. static struct descriptor {
  34. struct usb_hub_descriptor hub;
  35. struct usb_device_descriptor device;
  36. struct usb_config_descriptor config;
  37. struct usb_interface_descriptor interface;
  38. struct usb_endpoint_descriptor endpoint;
  39. struct usb_ss_ep_comp_descriptor ep_companion;
  40. } __attribute__ ((packed)) descriptor = {
  41. {
  42. 0xc, /* bDescLength */
  43. 0x2a, /* bDescriptorType: hub descriptor */
  44. 2, /* bNrPorts -- runtime modified */
  45. cpu_to_le16(0x8), /* wHubCharacteristics */
  46. 10, /* bPwrOn2PwrGood */
  47. 0, /* bHubCntrCurrent */
  48. { /* Device removable */
  49. } /* at most 7 ports! XXX */
  50. },
  51. {
  52. 0x12, /* bLength */
  53. 1, /* bDescriptorType: UDESC_DEVICE */
  54. cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
  55. 9, /* bDeviceClass: UDCLASS_HUB */
  56. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  57. 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
  58. 9, /* bMaxPacketSize: 512 bytes 2^9 */
  59. 0x0000, /* idVendor */
  60. 0x0000, /* idProduct */
  61. cpu_to_le16(0x0100), /* bcdDevice */
  62. 1, /* iManufacturer */
  63. 2, /* iProduct */
  64. 0, /* iSerialNumber */
  65. 1 /* bNumConfigurations: 1 */
  66. },
  67. {
  68. 0x9,
  69. 2, /* bDescriptorType: UDESC_CONFIG */
  70. cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
  71. 1, /* bNumInterface */
  72. 1, /* bConfigurationValue */
  73. 0, /* iConfiguration */
  74. 0x40, /* bmAttributes: UC_SELF_POWER */
  75. 0 /* bMaxPower */
  76. },
  77. {
  78. 0x9, /* bLength */
  79. 4, /* bDescriptorType: UDESC_INTERFACE */
  80. 0, /* bInterfaceNumber */
  81. 0, /* bAlternateSetting */
  82. 1, /* bNumEndpoints */
  83. 9, /* bInterfaceClass: UICLASS_HUB */
  84. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  85. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  86. 0 /* iInterface */
  87. },
  88. {
  89. 0x7, /* bLength */
  90. 5, /* bDescriptorType: UDESC_ENDPOINT */
  91. 0x81, /* bEndpointAddress: IN endpoint 1 */
  92. 3, /* bmAttributes: UE_INTERRUPT */
  93. 8, /* wMaxPacketSize */
  94. 255 /* bInterval */
  95. },
  96. {
  97. 0x06, /* ss_bLength */
  98. 0x30, /* ss_bDescriptorType: SS EP Companion */
  99. 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
  100. /* ss_bmAttributes: 1 packet per service interval */
  101. 0x00,
  102. /* ss_wBytesPerInterval: 15 bits for max 15 ports */
  103. cpu_to_le16(0x02),
  104. },
  105. };
  106. #ifndef CONFIG_DM_USB
  107. static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  108. #endif
  109. struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
  110. {
  111. #ifdef CONFIG_DM_USB
  112. struct udevice *dev;
  113. /* Find the USB controller */
  114. for (dev = udev->dev;
  115. device_get_uclass_id(dev) != UCLASS_USB;
  116. dev = dev->parent)
  117. ;
  118. return dev_get_priv(dev);
  119. #else
  120. return udev->controller;
  121. #endif
  122. }
  123. /**
  124. * Waits for as per specified amount of time
  125. * for the "result" to match with "done"
  126. *
  127. * @param ptr pointer to the register to be read
  128. * @param mask mask for the value read
  129. * @param done value to be campared with result
  130. * @param usec time to wait till
  131. * @return 0 if handshake is success else < 0 on failure
  132. */
  133. static int handshake(uint32_t volatile *ptr, uint32_t mask,
  134. uint32_t done, int usec)
  135. {
  136. uint32_t result;
  137. do {
  138. result = xhci_readl(ptr);
  139. if (result == ~(uint32_t)0)
  140. return -ENODEV;
  141. result &= mask;
  142. if (result == done)
  143. return 0;
  144. usec--;
  145. udelay(1);
  146. } while (usec > 0);
  147. return -ETIMEDOUT;
  148. }
  149. /**
  150. * Set the run bit and wait for the host to be running.
  151. *
  152. * @param hcor pointer to host controller operation registers
  153. * @return status of the Handshake
  154. */
  155. static int xhci_start(struct xhci_hcor *hcor)
  156. {
  157. u32 temp;
  158. int ret;
  159. puts("Starting the controller\n");
  160. temp = xhci_readl(&hcor->or_usbcmd);
  161. temp |= (CMD_RUN);
  162. xhci_writel(&hcor->or_usbcmd, temp);
  163. /*
  164. * Wait for the HCHalted Status bit to be 0 to indicate the host is
  165. * running.
  166. */
  167. ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
  168. if (ret)
  169. debug("Host took too long to start, "
  170. "waited %u microseconds.\n",
  171. XHCI_MAX_HALT_USEC);
  172. return ret;
  173. }
  174. /**
  175. * Resets the XHCI Controller
  176. *
  177. * @param hcor pointer to host controller operation registers
  178. * @return -EBUSY if XHCI Controller is not halted else status of handshake
  179. */
  180. static int xhci_reset(struct xhci_hcor *hcor)
  181. {
  182. u32 cmd;
  183. u32 state;
  184. int ret;
  185. /* Halting the Host first */
  186. debug("// Halt the HC: %p\n", hcor);
  187. state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
  188. if (!state) {
  189. cmd = xhci_readl(&hcor->or_usbcmd);
  190. cmd &= ~CMD_RUN;
  191. xhci_writel(&hcor->or_usbcmd, cmd);
  192. }
  193. ret = handshake(&hcor->or_usbsts,
  194. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  195. if (ret) {
  196. printf("Host not halted after %u microseconds.\n",
  197. XHCI_MAX_HALT_USEC);
  198. return -EBUSY;
  199. }
  200. debug("// Reset the HC\n");
  201. cmd = xhci_readl(&hcor->or_usbcmd);
  202. cmd |= CMD_RESET;
  203. xhci_writel(&hcor->or_usbcmd, cmd);
  204. ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
  205. if (ret)
  206. return ret;
  207. /*
  208. * xHCI cannot write to any doorbells or operational registers other
  209. * than status until the "Controller Not Ready" flag is cleared.
  210. */
  211. return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
  212. }
  213. /**
  214. * Used for passing endpoint bitmasks between the core and HCDs.
  215. * Find the index for an endpoint given its descriptor.
  216. * Use the return value to right shift 1 for the bitmask.
  217. *
  218. * Index = (epnum * 2) + direction - 1,
  219. * where direction = 0 for OUT, 1 for IN.
  220. * For control endpoints, the IN index is used (OUT index is unused), so
  221. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  222. *
  223. * @param desc USB enpdoint Descriptor
  224. * @return index of the Endpoint
  225. */
  226. static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
  227. {
  228. unsigned int index;
  229. if (usb_endpoint_xfer_control(desc))
  230. index = (unsigned int)(usb_endpoint_num(desc) * 2);
  231. else
  232. index = (unsigned int)((usb_endpoint_num(desc) * 2) -
  233. (usb_endpoint_dir_in(desc) ? 0 : 1));
  234. return index;
  235. }
  236. /*
  237. * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
  238. * microframes, rounded down to nearest power of 2.
  239. */
  240. static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
  241. unsigned int min_exponent,
  242. unsigned int max_exponent)
  243. {
  244. unsigned int interval;
  245. interval = fls(desc_interval) - 1;
  246. interval = clamp_val(interval, min_exponent, max_exponent);
  247. if ((1 << interval) != desc_interval)
  248. debug("rounding interval to %d microframes, "\
  249. "ep desc says %d microframes\n",
  250. 1 << interval, desc_interval);
  251. return interval;
  252. }
  253. static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
  254. struct usb_endpoint_descriptor *endpt_desc)
  255. {
  256. if (endpt_desc->bInterval == 0)
  257. return 0;
  258. return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
  259. }
  260. static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
  261. struct usb_endpoint_descriptor *endpt_desc)
  262. {
  263. return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
  264. }
  265. /*
  266. * Convert interval expressed as 2^(bInterval - 1) == interval into
  267. * straight exponent value 2^n == interval.
  268. */
  269. static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
  270. struct usb_endpoint_descriptor *endpt_desc)
  271. {
  272. unsigned int interval;
  273. interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
  274. if (interval != endpt_desc->bInterval - 1)
  275. debug("ep %#x - rounding interval to %d %sframes\n",
  276. endpt_desc->bEndpointAddress, 1 << interval,
  277. udev->speed == USB_SPEED_FULL ? "" : "micro");
  278. if (udev->speed == USB_SPEED_FULL) {
  279. /*
  280. * Full speed isoc endpoints specify interval in frames,
  281. * not microframes. We are using microframes everywhere,
  282. * so adjust accordingly.
  283. */
  284. interval += 3; /* 1 frame = 2^3 uframes */
  285. }
  286. return interval;
  287. }
  288. /*
  289. * Return the polling or NAK interval.
  290. *
  291. * The polling interval is expressed in "microframes". If xHCI's Interval field
  292. * is set to N, it will service the endpoint every 2^(Interval)*125us.
  293. *
  294. * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
  295. * is set to 0.
  296. */
  297. static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
  298. struct usb_endpoint_descriptor *endpt_desc)
  299. {
  300. unsigned int interval = 0;
  301. switch (udev->speed) {
  302. case USB_SPEED_HIGH:
  303. /* Max NAK rate */
  304. if (usb_endpoint_xfer_control(endpt_desc) ||
  305. usb_endpoint_xfer_bulk(endpt_desc)) {
  306. interval = xhci_parse_microframe_interval(udev,
  307. endpt_desc);
  308. break;
  309. }
  310. /* Fall through - SS and HS isoc/int have same decoding */
  311. case USB_SPEED_SUPER:
  312. if (usb_endpoint_xfer_int(endpt_desc) ||
  313. usb_endpoint_xfer_isoc(endpt_desc)) {
  314. interval = xhci_parse_exponent_interval(udev,
  315. endpt_desc);
  316. }
  317. break;
  318. case USB_SPEED_FULL:
  319. if (usb_endpoint_xfer_isoc(endpt_desc)) {
  320. interval = xhci_parse_exponent_interval(udev,
  321. endpt_desc);
  322. break;
  323. }
  324. /*
  325. * Fall through for interrupt endpoint interval decoding
  326. * since it uses the same rules as low speed interrupt
  327. * endpoints.
  328. */
  329. case USB_SPEED_LOW:
  330. if (usb_endpoint_xfer_int(endpt_desc) ||
  331. usb_endpoint_xfer_isoc(endpt_desc)) {
  332. interval = xhci_parse_frame_interval(udev, endpt_desc);
  333. }
  334. break;
  335. default:
  336. BUG();
  337. }
  338. return interval;
  339. }
  340. /*
  341. * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
  342. * High speed endpoint descriptors can define "the number of additional
  343. * transaction opportunities per microframe", but that goes in the Max Burst
  344. * endpoint context field.
  345. */
  346. static u32 xhci_get_endpoint_mult(struct usb_device *udev,
  347. struct usb_endpoint_descriptor *endpt_desc,
  348. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  349. {
  350. if (udev->speed < USB_SPEED_SUPER ||
  351. !usb_endpoint_xfer_isoc(endpt_desc))
  352. return 0;
  353. return ss_ep_comp_desc->bmAttributes;
  354. }
  355. static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
  356. struct usb_endpoint_descriptor *endpt_desc,
  357. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  358. {
  359. /* Super speed and Plus have max burst in ep companion desc */
  360. if (udev->speed >= USB_SPEED_SUPER)
  361. return ss_ep_comp_desc->bMaxBurst;
  362. if (udev->speed == USB_SPEED_HIGH &&
  363. (usb_endpoint_xfer_isoc(endpt_desc) ||
  364. usb_endpoint_xfer_int(endpt_desc)))
  365. return usb_endpoint_maxp_mult(endpt_desc) - 1;
  366. return 0;
  367. }
  368. /*
  369. * Return the maximum endpoint service interval time (ESIT) payload.
  370. * Basically, this is the maxpacket size, multiplied by the burst size
  371. * and mult size.
  372. */
  373. static u32 xhci_get_max_esit_payload(struct usb_device *udev,
  374. struct usb_endpoint_descriptor *endpt_desc,
  375. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  376. {
  377. int max_burst;
  378. int max_packet;
  379. /* Only applies for interrupt or isochronous endpoints */
  380. if (usb_endpoint_xfer_control(endpt_desc) ||
  381. usb_endpoint_xfer_bulk(endpt_desc))
  382. return 0;
  383. /* SuperSpeed Isoc ep with less than 48k per esit */
  384. if (udev->speed >= USB_SPEED_SUPER)
  385. return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
  386. max_packet = usb_endpoint_maxp(endpt_desc);
  387. max_burst = usb_endpoint_maxp_mult(endpt_desc);
  388. /* A 0 in max burst means 1 transfer per ESIT */
  389. return max_packet * max_burst;
  390. }
  391. /**
  392. * Issue a configure endpoint command or evaluate context command
  393. * and wait for it to finish.
  394. *
  395. * @param udev pointer to the Device Data Structure
  396. * @param ctx_change flag to indicate the Context has changed or NOT
  397. * @return 0 on success, -1 on failure
  398. */
  399. static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
  400. {
  401. struct xhci_container_ctx *in_ctx;
  402. struct xhci_virt_device *virt_dev;
  403. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  404. union xhci_trb *event;
  405. virt_dev = ctrl->devs[udev->slot_id];
  406. in_ctx = virt_dev->in_ctx;
  407. xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
  408. xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
  409. ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
  410. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  411. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
  412. != udev->slot_id);
  413. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  414. case COMP_SUCCESS:
  415. debug("Successful %s command\n",
  416. ctx_change ? "Evaluate Context" : "Configure Endpoint");
  417. break;
  418. default:
  419. printf("ERROR: %s command returned completion code %d.\n",
  420. ctx_change ? "Evaluate Context" : "Configure Endpoint",
  421. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  422. return -EINVAL;
  423. }
  424. xhci_acknowledge_event(ctrl);
  425. return 0;
  426. }
  427. /**
  428. * Configure the endpoint, programming the device contexts.
  429. *
  430. * @param udev pointer to the USB device structure
  431. * @return returns the status of the xhci_configure_endpoints
  432. */
  433. static int xhci_set_configuration(struct usb_device *udev)
  434. {
  435. struct xhci_container_ctx *in_ctx;
  436. struct xhci_container_ctx *out_ctx;
  437. struct xhci_input_control_ctx *ctrl_ctx;
  438. struct xhci_slot_ctx *slot_ctx;
  439. struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
  440. int cur_ep;
  441. int max_ep_flag = 0;
  442. int ep_index;
  443. unsigned int dir;
  444. unsigned int ep_type;
  445. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  446. int num_of_ep;
  447. int ep_flag = 0;
  448. u64 trb_64 = 0;
  449. int slot_id = udev->slot_id;
  450. struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
  451. struct usb_interface *ifdesc;
  452. u32 max_esit_payload;
  453. unsigned int interval;
  454. unsigned int mult;
  455. unsigned int max_burst;
  456. unsigned int avg_trb_len;
  457. unsigned int err_count = 0;
  458. out_ctx = virt_dev->out_ctx;
  459. in_ctx = virt_dev->in_ctx;
  460. num_of_ep = udev->config.if_desc[0].no_of_ep;
  461. ifdesc = &udev->config.if_desc[0];
  462. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  463. /* Initialize the input context control */
  464. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  465. ctrl_ctx->drop_flags = 0;
  466. /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
  467. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  468. ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
  469. ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
  470. if (max_ep_flag < ep_flag)
  471. max_ep_flag = ep_flag;
  472. }
  473. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  474. /* slot context */
  475. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  476. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  477. slot_ctx->dev_info &= ~(LAST_CTX_MASK);
  478. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
  479. xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
  480. /* filling up ep contexts */
  481. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  482. struct usb_endpoint_descriptor *endpt_desc = NULL;
  483. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
  484. endpt_desc = &ifdesc->ep_desc[cur_ep];
  485. ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
  486. trb_64 = 0;
  487. /*
  488. * Get values to fill the endpoint context, mostly from ep
  489. * descriptor. The average TRB buffer lengt for bulk endpoints
  490. * is unclear as we have no clue on scatter gather list entry
  491. * size. For Isoc and Int, set it to max available.
  492. * See xHCI 1.1 spec 4.14.1.1 for details.
  493. */
  494. max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
  495. ss_ep_comp_desc);
  496. interval = xhci_get_endpoint_interval(udev, endpt_desc);
  497. mult = xhci_get_endpoint_mult(udev, endpt_desc,
  498. ss_ep_comp_desc);
  499. max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
  500. ss_ep_comp_desc);
  501. avg_trb_len = max_esit_payload;
  502. ep_index = xhci_get_ep_index(endpt_desc);
  503. ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  504. /* Allocate the ep rings */
  505. virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
  506. if (!virt_dev->eps[ep_index].ring)
  507. return -ENOMEM;
  508. /*NOTE: ep_desc[0] actually represents EP1 and so on */
  509. dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
  510. ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
  511. ep_ctx[ep_index]->ep_info =
  512. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
  513. EP_INTERVAL(interval) | EP_MULT(mult));
  514. ep_ctx[ep_index]->ep_info2 =
  515. cpu_to_le32(ep_type << EP_TYPE_SHIFT);
  516. ep_ctx[ep_index]->ep_info2 |=
  517. cpu_to_le32(MAX_PACKET
  518. (get_unaligned(&endpt_desc->wMaxPacketSize)));
  519. /* Allow 3 retries for everything but isoc, set CErr = 3 */
  520. if (!usb_endpoint_xfer_isoc(endpt_desc))
  521. err_count = 3;
  522. ep_ctx[ep_index]->ep_info2 |=
  523. cpu_to_le32(MAX_BURST(max_burst) |
  524. ERROR_COUNT(err_count));
  525. trb_64 = (uintptr_t)
  526. virt_dev->eps[ep_index].ring->enqueue;
  527. ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
  528. virt_dev->eps[ep_index].ring->cycle_state);
  529. /*
  530. * xHCI spec 6.2.3:
  531. * 'Average TRB Length' should be 8 for control endpoints.
  532. */
  533. if (usb_endpoint_xfer_control(endpt_desc))
  534. avg_trb_len = 8;
  535. ep_ctx[ep_index]->tx_info =
  536. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
  537. EP_AVG_TRB_LENGTH(avg_trb_len));
  538. }
  539. return xhci_configure_endpoints(udev, false);
  540. }
  541. /**
  542. * Issue an Address Device command (which will issue a SetAddress request to
  543. * the device).
  544. *
  545. * @param udev pointer to the Device Data Structure
  546. * @return 0 if successful else error code on failure
  547. */
  548. static int xhci_address_device(struct usb_device *udev, int root_portnr)
  549. {
  550. int ret = 0;
  551. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  552. struct xhci_slot_ctx *slot_ctx;
  553. struct xhci_input_control_ctx *ctrl_ctx;
  554. struct xhci_virt_device *virt_dev;
  555. int slot_id = udev->slot_id;
  556. union xhci_trb *event;
  557. virt_dev = ctrl->devs[slot_id];
  558. /*
  559. * This is the first Set Address since device plug-in
  560. * so setting up the slot context.
  561. */
  562. debug("Setting up addressable devices %p\n", ctrl->dcbaa);
  563. xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
  564. ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
  565. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
  566. ctrl_ctx->drop_flags = 0;
  567. xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
  568. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  569. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
  570. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  571. case COMP_CTX_STATE:
  572. case COMP_EBADSLT:
  573. printf("Setup ERROR: address device command for slot %d.\n",
  574. slot_id);
  575. ret = -EINVAL;
  576. break;
  577. case COMP_TX_ERR:
  578. puts("Device not responding to set address.\n");
  579. ret = -EPROTO;
  580. break;
  581. case COMP_DEV_ERR:
  582. puts("ERROR: Incompatible device"
  583. "for address device command.\n");
  584. ret = -ENODEV;
  585. break;
  586. case COMP_SUCCESS:
  587. debug("Successful Address Device command\n");
  588. udev->status = 0;
  589. break;
  590. default:
  591. printf("ERROR: unexpected command completion code 0x%x.\n",
  592. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  593. ret = -EINVAL;
  594. break;
  595. }
  596. xhci_acknowledge_event(ctrl);
  597. if (ret < 0)
  598. /*
  599. * TODO: Unsuccessful Address Device command shall leave the
  600. * slot in default state. So, issue Disable Slot command now.
  601. */
  602. return ret;
  603. xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
  604. virt_dev->out_ctx->size);
  605. slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
  606. debug("xHC internal address is: %d\n",
  607. le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
  608. return 0;
  609. }
  610. /**
  611. * Issue Enable slot command to the controller to allocate
  612. * device slot and assign the slot id. It fails if the xHC
  613. * ran out of device slots, the Enable Slot command timed out,
  614. * or allocating memory failed.
  615. *
  616. * @param udev pointer to the Device Data Structure
  617. * @return Returns 0 on succes else return error code on failure
  618. */
  619. static int _xhci_alloc_device(struct usb_device *udev)
  620. {
  621. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  622. union xhci_trb *event;
  623. int ret;
  624. /*
  625. * Root hub will be first device to be initailized.
  626. * If this device is root-hub, don't do any xHC related
  627. * stuff.
  628. */
  629. if (ctrl->rootdev == 0) {
  630. udev->speed = USB_SPEED_SUPER;
  631. return 0;
  632. }
  633. xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
  634. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  635. BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
  636. != COMP_SUCCESS);
  637. udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
  638. xhci_acknowledge_event(ctrl);
  639. ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
  640. if (ret < 0) {
  641. /*
  642. * TODO: Unsuccessful Address Device command shall leave
  643. * the slot in default. So, issue Disable Slot command now.
  644. */
  645. puts("Could not allocate xHCI USB device data structures\n");
  646. return ret;
  647. }
  648. return 0;
  649. }
  650. #ifndef CONFIG_DM_USB
  651. int usb_alloc_device(struct usb_device *udev)
  652. {
  653. return _xhci_alloc_device(udev);
  654. }
  655. #endif
  656. /*
  657. * Full speed devices may have a max packet size greater than 8 bytes, but the
  658. * USB core doesn't know that until it reads the first 8 bytes of the
  659. * descriptor. If the usb_device's max packet size changes after that point,
  660. * we need to issue an evaluate context command and wait on it.
  661. *
  662. * @param udev pointer to the Device Data Structure
  663. * @return returns the status of the xhci_configure_endpoints
  664. */
  665. int xhci_check_maxpacket(struct usb_device *udev)
  666. {
  667. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  668. unsigned int slot_id = udev->slot_id;
  669. int ep_index = 0; /* control endpoint */
  670. struct xhci_container_ctx *in_ctx;
  671. struct xhci_container_ctx *out_ctx;
  672. struct xhci_input_control_ctx *ctrl_ctx;
  673. struct xhci_ep_ctx *ep_ctx;
  674. int max_packet_size;
  675. int hw_max_packet_size;
  676. int ret = 0;
  677. out_ctx = ctrl->devs[slot_id]->out_ctx;
  678. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  679. ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
  680. hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
  681. max_packet_size = udev->epmaxpacketin[0];
  682. if (hw_max_packet_size != max_packet_size) {
  683. debug("Max Packet Size for ep 0 changed.\n");
  684. debug("Max packet size in usb_device = %d\n", max_packet_size);
  685. debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
  686. debug("Issuing evaluate context command.\n");
  687. /* Set up the modified control endpoint 0 */
  688. xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
  689. ctrl->devs[slot_id]->out_ctx, ep_index);
  690. in_ctx = ctrl->devs[slot_id]->in_ctx;
  691. ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  692. ep_ctx->ep_info2 &= cpu_to_le32(~((0xffff & MAX_PACKET_MASK)
  693. << MAX_PACKET_SHIFT));
  694. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
  695. /*
  696. * Set up the input context flags for the command
  697. * FIXME: This won't work if a non-default control endpoint
  698. * changes max packet sizes.
  699. */
  700. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  701. ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
  702. ctrl_ctx->drop_flags = 0;
  703. ret = xhci_configure_endpoints(udev, true);
  704. }
  705. return ret;
  706. }
  707. /**
  708. * Clears the Change bits of the Port Status Register
  709. *
  710. * @param wValue request value
  711. * @param wIndex request index
  712. * @param addr address of posrt status register
  713. * @param port_status state of port status register
  714. * @return none
  715. */
  716. static void xhci_clear_port_change_bit(u16 wValue,
  717. u16 wIndex, volatile uint32_t *addr, u32 port_status)
  718. {
  719. char *port_change_bit;
  720. u32 status;
  721. switch (wValue) {
  722. case USB_PORT_FEAT_C_RESET:
  723. status = PORT_RC;
  724. port_change_bit = "reset";
  725. break;
  726. case USB_PORT_FEAT_C_CONNECTION:
  727. status = PORT_CSC;
  728. port_change_bit = "connect";
  729. break;
  730. case USB_PORT_FEAT_C_OVER_CURRENT:
  731. status = PORT_OCC;
  732. port_change_bit = "over-current";
  733. break;
  734. case USB_PORT_FEAT_C_ENABLE:
  735. status = PORT_PEC;
  736. port_change_bit = "enable/disable";
  737. break;
  738. case USB_PORT_FEAT_C_SUSPEND:
  739. status = PORT_PLC;
  740. port_change_bit = "suspend/resume";
  741. break;
  742. default:
  743. /* Should never happen */
  744. return;
  745. }
  746. /* Change bits are all write 1 to clear */
  747. xhci_writel(addr, port_status | status);
  748. port_status = xhci_readl(addr);
  749. debug("clear port %s change, actual port %d status = 0x%x\n",
  750. port_change_bit, wIndex, port_status);
  751. }
  752. /**
  753. * Save Read Only (RO) bits and save read/write bits where
  754. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  755. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  756. *
  757. * @param state state of the Port Status and Control Regsiter
  758. * @return a value that would result in the port being in the
  759. * same state, if the value was written to the port
  760. * status control register.
  761. */
  762. static u32 xhci_port_state_to_neutral(u32 state)
  763. {
  764. /* Save read-only status and port state */
  765. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  766. }
  767. /**
  768. * Submits the Requests to the XHCI Host Controller
  769. *
  770. * @param udev pointer to the USB device structure
  771. * @param pipe contains the DIR_IN or OUT , devnum
  772. * @param buffer buffer to be read/written based on the request
  773. * @return returns 0 if successful else -1 on failure
  774. */
  775. static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
  776. void *buffer, struct devrequest *req)
  777. {
  778. uint8_t tmpbuf[4];
  779. u16 typeReq;
  780. void *srcptr = NULL;
  781. int len, srclen;
  782. uint32_t reg;
  783. volatile uint32_t *status_reg;
  784. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  785. struct xhci_hccr *hccr = ctrl->hccr;
  786. struct xhci_hcor *hcor = ctrl->hcor;
  787. int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
  788. if ((req->requesttype & USB_RT_PORT) &&
  789. le16_to_cpu(req->index) > max_ports) {
  790. printf("The request port(%d) exceeds maximum port number\n",
  791. le16_to_cpu(req->index) - 1);
  792. return -EINVAL;
  793. }
  794. status_reg = (volatile uint32_t *)
  795. (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
  796. srclen = 0;
  797. typeReq = req->request | req->requesttype << 8;
  798. switch (typeReq) {
  799. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  800. switch (le16_to_cpu(req->value) >> 8) {
  801. case USB_DT_DEVICE:
  802. debug("USB_DT_DEVICE request\n");
  803. srcptr = &descriptor.device;
  804. srclen = 0x12;
  805. break;
  806. case USB_DT_CONFIG:
  807. debug("USB_DT_CONFIG config\n");
  808. srcptr = &descriptor.config;
  809. srclen = 0x19;
  810. break;
  811. case USB_DT_STRING:
  812. debug("USB_DT_STRING config\n");
  813. switch (le16_to_cpu(req->value) & 0xff) {
  814. case 0: /* Language */
  815. srcptr = "\4\3\11\4";
  816. srclen = 4;
  817. break;
  818. case 1: /* Vendor String */
  819. srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
  820. srclen = 14;
  821. break;
  822. case 2: /* Product Name */
  823. srcptr = "\52\3X\0H\0C\0I\0 "
  824. "\0H\0o\0s\0t\0 "
  825. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  826. srclen = 42;
  827. break;
  828. default:
  829. printf("unknown value DT_STRING %x\n",
  830. le16_to_cpu(req->value));
  831. goto unknown;
  832. }
  833. break;
  834. default:
  835. printf("unknown value %x\n", le16_to_cpu(req->value));
  836. goto unknown;
  837. }
  838. break;
  839. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  840. switch (le16_to_cpu(req->value) >> 8) {
  841. case USB_DT_HUB:
  842. case USB_DT_SS_HUB:
  843. debug("USB_DT_HUB config\n");
  844. srcptr = &descriptor.hub;
  845. srclen = 0x8;
  846. break;
  847. default:
  848. printf("unknown value %x\n", le16_to_cpu(req->value));
  849. goto unknown;
  850. }
  851. break;
  852. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  853. debug("USB_REQ_SET_ADDRESS\n");
  854. ctrl->rootdev = le16_to_cpu(req->value);
  855. break;
  856. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  857. /* Do nothing */
  858. break;
  859. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  860. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  861. tmpbuf[1] = 0;
  862. srcptr = tmpbuf;
  863. srclen = 2;
  864. break;
  865. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  866. memset(tmpbuf, 0, 4);
  867. reg = xhci_readl(status_reg);
  868. if (reg & PORT_CONNECT) {
  869. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  870. switch (reg & DEV_SPEED_MASK) {
  871. case XDEV_FS:
  872. debug("SPEED = FULLSPEED\n");
  873. break;
  874. case XDEV_LS:
  875. debug("SPEED = LOWSPEED\n");
  876. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  877. break;
  878. case XDEV_HS:
  879. debug("SPEED = HIGHSPEED\n");
  880. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  881. break;
  882. case XDEV_SS:
  883. debug("SPEED = SUPERSPEED\n");
  884. tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
  885. break;
  886. }
  887. }
  888. if (reg & PORT_PE)
  889. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  890. if ((reg & PORT_PLS_MASK) == XDEV_U3)
  891. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  892. if (reg & PORT_OC)
  893. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  894. if (reg & PORT_RESET)
  895. tmpbuf[0] |= USB_PORT_STAT_RESET;
  896. if (reg & PORT_POWER)
  897. /*
  898. * XXX: This Port power bit (for USB 3.0 hub)
  899. * we are faking in USB 2.0 hub port status;
  900. * since there's a change in bit positions in
  901. * two:
  902. * USB 2.0 port status PP is at position[8]
  903. * USB 3.0 port status PP is at position[9]
  904. * So, we are still keeping it at position [8]
  905. */
  906. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  907. if (reg & PORT_CSC)
  908. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  909. if (reg & PORT_PEC)
  910. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  911. if (reg & PORT_OCC)
  912. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  913. if (reg & PORT_RC)
  914. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  915. srcptr = tmpbuf;
  916. srclen = 4;
  917. break;
  918. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  919. reg = xhci_readl(status_reg);
  920. reg = xhci_port_state_to_neutral(reg);
  921. switch (le16_to_cpu(req->value)) {
  922. case USB_PORT_FEAT_ENABLE:
  923. reg |= PORT_PE;
  924. xhci_writel(status_reg, reg);
  925. break;
  926. case USB_PORT_FEAT_POWER:
  927. reg |= PORT_POWER;
  928. xhci_writel(status_reg, reg);
  929. break;
  930. case USB_PORT_FEAT_RESET:
  931. reg |= PORT_RESET;
  932. xhci_writel(status_reg, reg);
  933. break;
  934. default:
  935. printf("unknown feature %x\n", le16_to_cpu(req->value));
  936. goto unknown;
  937. }
  938. break;
  939. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  940. reg = xhci_readl(status_reg);
  941. reg = xhci_port_state_to_neutral(reg);
  942. switch (le16_to_cpu(req->value)) {
  943. case USB_PORT_FEAT_ENABLE:
  944. reg &= ~PORT_PE;
  945. break;
  946. case USB_PORT_FEAT_POWER:
  947. reg &= ~PORT_POWER;
  948. break;
  949. case USB_PORT_FEAT_C_RESET:
  950. case USB_PORT_FEAT_C_CONNECTION:
  951. case USB_PORT_FEAT_C_OVER_CURRENT:
  952. case USB_PORT_FEAT_C_ENABLE:
  953. xhci_clear_port_change_bit((le16_to_cpu(req->value)),
  954. le16_to_cpu(req->index),
  955. status_reg, reg);
  956. break;
  957. default:
  958. printf("unknown feature %x\n", le16_to_cpu(req->value));
  959. goto unknown;
  960. }
  961. xhci_writel(status_reg, reg);
  962. break;
  963. default:
  964. puts("Unknown request\n");
  965. goto unknown;
  966. }
  967. debug("scrlen = %d\n req->length = %d\n",
  968. srclen, le16_to_cpu(req->length));
  969. len = min(srclen, (int)le16_to_cpu(req->length));
  970. if (srcptr != NULL && len > 0)
  971. memcpy(buffer, srcptr, len);
  972. else
  973. debug("Len is 0\n");
  974. udev->act_len = len;
  975. udev->status = 0;
  976. return 0;
  977. unknown:
  978. udev->act_len = 0;
  979. udev->status = USB_ST_STALLED;
  980. return -ENODEV;
  981. }
  982. /**
  983. * Submits the INT request to XHCI Host cotroller
  984. *
  985. * @param udev pointer to the USB device
  986. * @param pipe contains the DIR_IN or OUT , devnum
  987. * @param buffer buffer to be read/written based on the request
  988. * @param length length of the buffer
  989. * @param interval interval of the interrupt
  990. * @return 0
  991. */
  992. static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
  993. void *buffer, int length, int interval)
  994. {
  995. if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
  996. printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
  997. return -EINVAL;
  998. }
  999. /*
  1000. * xHCI uses normal TRBs for both bulk and interrupt. When the
  1001. * interrupt endpoint is to be serviced, the xHC will consume
  1002. * (at most) one TD. A TD (comprised of sg list entries) can
  1003. * take several service intervals to transmit.
  1004. */
  1005. return xhci_bulk_tx(udev, pipe, length, buffer);
  1006. }
  1007. /**
  1008. * submit the BULK type of request to the USB Device
  1009. *
  1010. * @param udev pointer to the USB device
  1011. * @param pipe contains the DIR_IN or OUT , devnum
  1012. * @param buffer buffer to be read/written based on the request
  1013. * @param length length of the buffer
  1014. * @return returns 0 if successful else -1 on failure
  1015. */
  1016. static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
  1017. void *buffer, int length)
  1018. {
  1019. if (usb_pipetype(pipe) != PIPE_BULK) {
  1020. printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  1021. return -EINVAL;
  1022. }
  1023. return xhci_bulk_tx(udev, pipe, length, buffer);
  1024. }
  1025. /**
  1026. * submit the control type of request to the Root hub/Device based on the devnum
  1027. *
  1028. * @param udev pointer to the USB device
  1029. * @param pipe contains the DIR_IN or OUT , devnum
  1030. * @param buffer buffer to be read/written based on the request
  1031. * @param length length of the buffer
  1032. * @param setup Request type
  1033. * @param root_portnr Root port number that this device is on
  1034. * @return returns 0 if successful else -1 on failure
  1035. */
  1036. static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1037. void *buffer, int length,
  1038. struct devrequest *setup, int root_portnr)
  1039. {
  1040. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  1041. int ret = 0;
  1042. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  1043. printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
  1044. return -EINVAL;
  1045. }
  1046. if (usb_pipedevice(pipe) == ctrl->rootdev)
  1047. return xhci_submit_root(udev, pipe, buffer, setup);
  1048. if (setup->request == USB_REQ_SET_ADDRESS &&
  1049. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  1050. return xhci_address_device(udev, root_portnr);
  1051. if (setup->request == USB_REQ_SET_CONFIGURATION &&
  1052. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  1053. ret = xhci_set_configuration(udev);
  1054. if (ret) {
  1055. puts("Failed to configure xHCI endpoint\n");
  1056. return ret;
  1057. }
  1058. }
  1059. return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
  1060. }
  1061. static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
  1062. {
  1063. struct xhci_hccr *hccr;
  1064. struct xhci_hcor *hcor;
  1065. uint32_t val;
  1066. uint32_t val2;
  1067. uint32_t reg;
  1068. hccr = ctrl->hccr;
  1069. hcor = ctrl->hcor;
  1070. /*
  1071. * Program the Number of Device Slots Enabled field in the CONFIG
  1072. * register with the max value of slots the HC can handle.
  1073. */
  1074. val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
  1075. val2 = xhci_readl(&hcor->or_config);
  1076. val |= (val2 & ~HCS_SLOTS_MASK);
  1077. xhci_writel(&hcor->or_config, val);
  1078. /* initializing xhci data structures */
  1079. if (xhci_mem_init(ctrl, hccr, hcor) < 0)
  1080. return -ENOMEM;
  1081. reg = xhci_readl(&hccr->cr_hcsparams1);
  1082. descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
  1083. HCS_MAX_PORTS_SHIFT);
  1084. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  1085. /* Port Indicators */
  1086. reg = xhci_readl(&hccr->cr_hccparams);
  1087. if (HCS_INDICATOR(reg))
  1088. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1089. | 0x80, &descriptor.hub.wHubCharacteristics);
  1090. /* Port Power Control */
  1091. if (HCC_PPC(reg))
  1092. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1093. | 0x01, &descriptor.hub.wHubCharacteristics);
  1094. if (xhci_start(hcor)) {
  1095. xhci_reset(hcor);
  1096. return -ENODEV;
  1097. }
  1098. /* Zero'ing IRQ control register and IRQ pending register */
  1099. xhci_writel(&ctrl->ir_set->irq_control, 0x0);
  1100. xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
  1101. reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
  1102. printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
  1103. return 0;
  1104. }
  1105. static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
  1106. {
  1107. u32 temp;
  1108. xhci_reset(ctrl->hcor);
  1109. debug("// Disabling event ring interrupts\n");
  1110. temp = xhci_readl(&ctrl->hcor->or_usbsts);
  1111. xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
  1112. temp = xhci_readl(&ctrl->ir_set->irq_pending);
  1113. xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
  1114. return 0;
  1115. }
  1116. #ifndef CONFIG_DM_USB
  1117. int submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1118. void *buffer, int length, struct devrequest *setup)
  1119. {
  1120. struct usb_device *hop = udev;
  1121. if (hop->parent)
  1122. while (hop->parent->parent)
  1123. hop = hop->parent;
  1124. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1125. hop->portnr);
  1126. }
  1127. int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1128. int length)
  1129. {
  1130. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1131. }
  1132. int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1133. int length, int interval)
  1134. {
  1135. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval);
  1136. }
  1137. /**
  1138. * Intialises the XHCI host controller
  1139. * and allocates the necessary data structures
  1140. *
  1141. * @param index index to the host controller data structure
  1142. * @return pointer to the intialised controller
  1143. */
  1144. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1145. {
  1146. struct xhci_hccr *hccr;
  1147. struct xhci_hcor *hcor;
  1148. struct xhci_ctrl *ctrl;
  1149. int ret;
  1150. *controller = NULL;
  1151. if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
  1152. return -ENODEV;
  1153. if (xhci_reset(hcor) != 0)
  1154. return -ENODEV;
  1155. ctrl = &xhcic[index];
  1156. ctrl->hccr = hccr;
  1157. ctrl->hcor = hcor;
  1158. ret = xhci_lowlevel_init(ctrl);
  1159. if (ret) {
  1160. ctrl->hccr = NULL;
  1161. ctrl->hcor = NULL;
  1162. } else {
  1163. *controller = &xhcic[index];
  1164. }
  1165. return ret;
  1166. }
  1167. /**
  1168. * Stops the XHCI host controller
  1169. * and cleans up all the related data structures
  1170. *
  1171. * @param index index to the host controller data structure
  1172. * @return none
  1173. */
  1174. int usb_lowlevel_stop(int index)
  1175. {
  1176. struct xhci_ctrl *ctrl = (xhcic + index);
  1177. if (ctrl->hcor) {
  1178. xhci_lowlevel_stop(ctrl);
  1179. xhci_hcd_stop(index);
  1180. xhci_cleanup(ctrl);
  1181. }
  1182. return 0;
  1183. }
  1184. #endif /* CONFIG_DM_USB */
  1185. #ifdef CONFIG_DM_USB
  1186. static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1187. unsigned long pipe, void *buffer, int length,
  1188. struct devrequest *setup)
  1189. {
  1190. struct usb_device *uhop;
  1191. struct udevice *hub;
  1192. int root_portnr = 0;
  1193. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1194. dev->name, udev, udev->dev->name, udev->portnr);
  1195. hub = udev->dev;
  1196. if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
  1197. /* Figure out our port number on the root hub */
  1198. if (usb_hub_is_root_hub(hub)) {
  1199. root_portnr = udev->portnr;
  1200. } else {
  1201. while (!usb_hub_is_root_hub(hub->parent))
  1202. hub = hub->parent;
  1203. uhop = dev_get_parent_priv(hub);
  1204. root_portnr = uhop->portnr;
  1205. }
  1206. }
  1207. /*
  1208. struct usb_device *hop = udev;
  1209. if (hop->parent)
  1210. while (hop->parent->parent)
  1211. hop = hop->parent;
  1212. */
  1213. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1214. root_portnr);
  1215. }
  1216. static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1217. unsigned long pipe, void *buffer, int length)
  1218. {
  1219. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1220. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1221. }
  1222. static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1223. unsigned long pipe, void *buffer, int length,
  1224. int interval)
  1225. {
  1226. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1227. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval);
  1228. }
  1229. static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
  1230. {
  1231. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1232. return _xhci_alloc_device(udev);
  1233. }
  1234. static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
  1235. {
  1236. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1237. struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
  1238. struct xhci_virt_device *virt_dev;
  1239. struct xhci_input_control_ctx *ctrl_ctx;
  1240. struct xhci_container_ctx *out_ctx;
  1241. struct xhci_container_ctx *in_ctx;
  1242. struct xhci_slot_ctx *slot_ctx;
  1243. int slot_id = udev->slot_id;
  1244. unsigned think_time;
  1245. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1246. /* Ignore root hubs */
  1247. if (usb_hub_is_root_hub(udev->dev))
  1248. return 0;
  1249. virt_dev = ctrl->devs[slot_id];
  1250. BUG_ON(!virt_dev);
  1251. out_ctx = virt_dev->out_ctx;
  1252. in_ctx = virt_dev->in_ctx;
  1253. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  1254. /* Initialize the input context control */
  1255. ctrl_ctx->add_flags |= cpu_to_le32(SLOT_FLAG);
  1256. ctrl_ctx->drop_flags = 0;
  1257. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  1258. /* slot context */
  1259. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  1260. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  1261. /* Update hub related fields */
  1262. slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
  1263. if (hub->tt.multi && udev->speed == USB_SPEED_HIGH)
  1264. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  1265. slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
  1266. /*
  1267. * Set TT think time - convert from ns to FS bit times.
  1268. * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
  1269. *
  1270. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  1271. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  1272. *
  1273. * This field shall be 0 if the device is not a high-spped hub.
  1274. */
  1275. think_time = hub->tt.think_time;
  1276. if (think_time != 0)
  1277. think_time = (think_time / 666) - 1;
  1278. if (udev->speed == USB_SPEED_HIGH)
  1279. slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
  1280. return xhci_configure_endpoints(udev, false);
  1281. }
  1282. static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
  1283. {
  1284. /*
  1285. * xHCD allocates one segment which includes 64 TRBs for each endpoint
  1286. * and the last TRB in this segment is configured as a link TRB to form
  1287. * a TRB ring. Each TRB can transfer up to 64K bytes, however data
  1288. * buffers referenced by transfer TRBs shall not span 64KB boundaries.
  1289. * Hence the maximum number of TRBs we can use in one transfer is 62.
  1290. */
  1291. *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
  1292. return 0;
  1293. }
  1294. int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
  1295. struct xhci_hcor *hcor)
  1296. {
  1297. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1298. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1299. int ret;
  1300. debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
  1301. ctrl, hccr, hcor);
  1302. ctrl->dev = dev;
  1303. /*
  1304. * XHCI needs to issue a Address device command to setup
  1305. * proper device context structures, before it can interact
  1306. * with the device. So a get_descriptor will fail before any
  1307. * of that is done for XHCI unlike EHCI.
  1308. */
  1309. priv->desc_before_addr = false;
  1310. ret = xhci_reset(hcor);
  1311. if (ret)
  1312. goto err;
  1313. ctrl->hccr = hccr;
  1314. ctrl->hcor = hcor;
  1315. ret = xhci_lowlevel_init(ctrl);
  1316. if (ret)
  1317. goto err;
  1318. return 0;
  1319. err:
  1320. free(ctrl);
  1321. debug("%s: failed, ret=%d\n", __func__, ret);
  1322. return ret;
  1323. }
  1324. int xhci_deregister(struct udevice *dev)
  1325. {
  1326. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1327. xhci_lowlevel_stop(ctrl);
  1328. xhci_cleanup(ctrl);
  1329. return 0;
  1330. }
  1331. struct dm_usb_ops xhci_usb_ops = {
  1332. .control = xhci_submit_control_msg,
  1333. .bulk = xhci_submit_bulk_msg,
  1334. .interrupt = xhci_submit_int_msg,
  1335. .alloc_device = xhci_alloc_device,
  1336. .update_hub_device = xhci_update_hub_device,
  1337. .get_max_xfer_size = xhci_get_max_xfer_size,
  1338. };
  1339. #endif