xhci-zynqmp.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2015 Xilinx, Inc.
  4. *
  5. * Zynq USB HOST xHCI Controller
  6. *
  7. * Author: Siva Durga Prasad Paladugu<sivadur@xilinx.com>
  8. *
  9. * This file was reused from Freescale USB xHCI
  10. */
  11. #include <common.h>
  12. #include <usb.h>
  13. #include <linux/errno.h>
  14. #include <asm/arch-zynqmp/hardware.h>
  15. #include <linux/compat.h>
  16. #include <linux/usb/dwc3.h>
  17. #include "xhci.h"
  18. /* Declare global data pointer */
  19. /* Default to the ZYNQMP XHCI defines */
  20. #define USB3_PWRCTL_CLK_CMD_MASK 0x3FE000
  21. #define USB3_PWRCTL_CLK_FREQ_MASK 0xFFC
  22. #define USB3_PHY_PARTIAL_RX_POWERON BIT(6)
  23. #define USB3_PHY_RX_POWERON BIT(14)
  24. #define USB3_PHY_TX_POWERON BIT(15)
  25. #define USB3_PHY_TX_RX_POWERON (USB3_PHY_RX_POWERON | USB3_PHY_TX_POWERON)
  26. #define USB3_PWRCTL_CLK_CMD_SHIFT 14
  27. #define USB3_PWRCTL_CLK_FREQ_SHIFT 22
  28. /* USBOTGSS_WRAPPER definitions */
  29. #define USBOTGSS_WRAPRESET BIT(17)
  30. #define USBOTGSS_DMADISABLE BIT(16)
  31. #define USBOTGSS_STANDBYMODE_NO_STANDBY BIT(4)
  32. #define USBOTGSS_STANDBYMODE_SMRT BIT(5)
  33. #define USBOTGSS_STANDBYMODE_SMRT_WKUP (0x3 << 4)
  34. #define USBOTGSS_IDLEMODE_NOIDLE BIT(2)
  35. #define USBOTGSS_IDLEMODE_SMRT BIT(3)
  36. #define USBOTGSS_IDLEMODE_SMRT_WKUP (0x3 << 2)
  37. /* USBOTGSS_IRQENABLE_SET_0 bit */
  38. #define USBOTGSS_COREIRQ_EN BIT(1)
  39. /* USBOTGSS_IRQENABLE_SET_1 bits */
  40. #define USBOTGSS_IRQ_SET_1_IDPULLUP_FALL_EN BIT(1)
  41. #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_FALL_EN BIT(3)
  42. #define USBOTGSS_IRQ_SET_1_CHRGVBUS_FALL_EN BIT(4)
  43. #define USBOTGSS_IRQ_SET_1_DRVVBUS_FALL_EN BIT(5)
  44. #define USBOTGSS_IRQ_SET_1_IDPULLUP_RISE_EN BIT(8)
  45. #define USBOTGSS_IRQ_SET_1_DISCHRGVBUS_RISE_EN BIT(11)
  46. #define USBOTGSS_IRQ_SET_1_CHRGVBUS_RISE_EN BIT(12)
  47. #define USBOTGSS_IRQ_SET_1_DRVVBUS_RISE_EN BIT(13)
  48. #define USBOTGSS_IRQ_SET_1_OEVT_EN BIT(16)
  49. #define USBOTGSS_IRQ_SET_1_DMADISABLECLR_EN BIT(17)
  50. struct zynqmp_xhci {
  51. struct xhci_hccr *hcd;
  52. struct dwc3 *dwc3_reg;
  53. };
  54. static struct zynqmp_xhci zynqmp_xhci;
  55. unsigned long ctr_addr[] = CONFIG_ZYNQMP_XHCI_LIST;
  56. static int zynqmp_xhci_core_init(struct zynqmp_xhci *zynqmp_xhci)
  57. {
  58. int ret = 0;
  59. ret = dwc3_core_init(zynqmp_xhci->dwc3_reg);
  60. if (ret) {
  61. debug("%s:failed to initialize core\n", __func__);
  62. return ret;
  63. }
  64. /* We are hard-coding DWC3 core to Host Mode */
  65. dwc3_set_mode(zynqmp_xhci->dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
  66. return ret;
  67. }
  68. int xhci_hcd_init(int index, struct xhci_hccr **hccr, struct xhci_hcor **hcor)
  69. {
  70. struct zynqmp_xhci *ctx = &zynqmp_xhci;
  71. int ret = 0;
  72. uint32_t hclen;
  73. if (index < 0 || index >= ARRAY_SIZE(ctr_addr))
  74. return -EINVAL;
  75. ctx->hcd = (struct xhci_hccr *)ctr_addr[index];
  76. ctx->dwc3_reg = (struct dwc3 *)((void *)ctx->hcd + DWC3_REG_OFFSET);
  77. ret = board_usb_init(index, USB_INIT_HOST);
  78. if (ret != 0) {
  79. puts("Failed to initialize board for USB\n");
  80. return ret;
  81. }
  82. ret = zynqmp_xhci_core_init(ctx);
  83. if (ret < 0) {
  84. puts("Failed to initialize xhci\n");
  85. return ret;
  86. }
  87. *hccr = (struct xhci_hccr *)ctx->hcd;
  88. hclen = HC_LENGTH(xhci_readl(&(*hccr)->cr_capbase));
  89. *hcor = (struct xhci_hcor *)((uintptr_t) *hccr + hclen);
  90. debug("zynqmp-xhci: init hccr %p and hcor %p hc_length %d\n",
  91. *hccr, *hcor, hclen);
  92. return ret;
  93. }
  94. void xhci_hcd_stop(int index)
  95. {
  96. /*
  97. * Currently zynqmp socs do not support PHY shutdown from
  98. * sw. But this support may be added in future socs.
  99. */
  100. return;
  101. }