xhci-mem.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB HOST XHCI Controller stack
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. #include <common.h>
  16. #include <dm.h>
  17. #include <asm/byteorder.h>
  18. #include <usb.h>
  19. #include <malloc.h>
  20. #include <asm/cache.h>
  21. #include <linux/errno.h>
  22. #include "xhci.h"
  23. #define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
  24. /**
  25. * flushes the address passed till the length
  26. *
  27. * @param addr pointer to memory region to be flushed
  28. * @param len the length of the cache line to be flushed
  29. * @return none
  30. */
  31. void xhci_flush_cache(uintptr_t addr, u32 len)
  32. {
  33. BUG_ON((void *)addr == NULL || len == 0);
  34. flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
  35. ALIGN(addr + len, CACHELINE_SIZE));
  36. }
  37. /**
  38. * invalidates the address passed till the length
  39. *
  40. * @param addr pointer to memory region to be invalidates
  41. * @param len the length of the cache line to be invalidated
  42. * @return none
  43. */
  44. void xhci_inval_cache(uintptr_t addr, u32 len)
  45. {
  46. BUG_ON((void *)addr == NULL || len == 0);
  47. invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
  48. ALIGN(addr + len, CACHELINE_SIZE));
  49. }
  50. /**
  51. * frees the "segment" pointer passed
  52. *
  53. * @param ptr pointer to "segement" to be freed
  54. * @return none
  55. */
  56. static void xhci_segment_free(struct xhci_segment *seg)
  57. {
  58. free(seg->trbs);
  59. seg->trbs = NULL;
  60. free(seg);
  61. }
  62. /**
  63. * frees the "ring" pointer passed
  64. *
  65. * @param ptr pointer to "ring" to be freed
  66. * @return none
  67. */
  68. static void xhci_ring_free(struct xhci_ring *ring)
  69. {
  70. struct xhci_segment *seg;
  71. struct xhci_segment *first_seg;
  72. BUG_ON(!ring);
  73. first_seg = ring->first_seg;
  74. seg = first_seg->next;
  75. while (seg != first_seg) {
  76. struct xhci_segment *next = seg->next;
  77. xhci_segment_free(seg);
  78. seg = next;
  79. }
  80. xhci_segment_free(first_seg);
  81. free(ring);
  82. }
  83. /**
  84. * Free the scratchpad buffer array and scratchpad buffers
  85. *
  86. * @ctrl host controller data structure
  87. * @return none
  88. */
  89. static void xhci_scratchpad_free(struct xhci_ctrl *ctrl)
  90. {
  91. if (!ctrl->scratchpad)
  92. return;
  93. ctrl->dcbaa->dev_context_ptrs[0] = 0;
  94. free((void *)(uintptr_t)ctrl->scratchpad->sp_array[0]);
  95. free(ctrl->scratchpad->sp_array);
  96. free(ctrl->scratchpad);
  97. ctrl->scratchpad = NULL;
  98. }
  99. /**
  100. * frees the "xhci_container_ctx" pointer passed
  101. *
  102. * @param ptr pointer to "xhci_container_ctx" to be freed
  103. * @return none
  104. */
  105. static void xhci_free_container_ctx(struct xhci_container_ctx *ctx)
  106. {
  107. free(ctx->bytes);
  108. free(ctx);
  109. }
  110. /**
  111. * frees the virtual devices for "xhci_ctrl" pointer passed
  112. *
  113. * @param ptr pointer to "xhci_ctrl" whose virtual devices are to be freed
  114. * @return none
  115. */
  116. static void xhci_free_virt_devices(struct xhci_ctrl *ctrl)
  117. {
  118. int i;
  119. int slot_id;
  120. struct xhci_virt_device *virt_dev;
  121. /*
  122. * refactored here to loop through all virt_dev
  123. * Slot ID 0 is reserved
  124. */
  125. for (slot_id = 0; slot_id < MAX_HC_SLOTS; slot_id++) {
  126. virt_dev = ctrl->devs[slot_id];
  127. if (!virt_dev)
  128. continue;
  129. ctrl->dcbaa->dev_context_ptrs[slot_id] = 0;
  130. for (i = 0; i < 31; ++i)
  131. if (virt_dev->eps[i].ring)
  132. xhci_ring_free(virt_dev->eps[i].ring);
  133. if (virt_dev->in_ctx)
  134. xhci_free_container_ctx(virt_dev->in_ctx);
  135. if (virt_dev->out_ctx)
  136. xhci_free_container_ctx(virt_dev->out_ctx);
  137. free(virt_dev);
  138. /* make sure we are pointing to NULL */
  139. ctrl->devs[slot_id] = NULL;
  140. }
  141. }
  142. /**
  143. * frees all the memory allocated
  144. *
  145. * @param ptr pointer to "xhci_ctrl" to be cleaned up
  146. * @return none
  147. */
  148. void xhci_cleanup(struct xhci_ctrl *ctrl)
  149. {
  150. xhci_ring_free(ctrl->event_ring);
  151. xhci_ring_free(ctrl->cmd_ring);
  152. xhci_scratchpad_free(ctrl);
  153. xhci_free_virt_devices(ctrl);
  154. free(ctrl->erst.entries);
  155. free(ctrl->dcbaa);
  156. memset(ctrl, '\0', sizeof(struct xhci_ctrl));
  157. }
  158. /**
  159. * Malloc the aligned memory
  160. *
  161. * @param size size of memory to be allocated
  162. * @return allocates the memory and returns the aligned pointer
  163. */
  164. static void *xhci_malloc(unsigned int size)
  165. {
  166. void *ptr;
  167. size_t cacheline_size = max(XHCI_ALIGNMENT, CACHELINE_SIZE);
  168. ptr = memalign(cacheline_size, ALIGN(size, cacheline_size));
  169. BUG_ON(!ptr);
  170. memset(ptr, '\0', size);
  171. xhci_flush_cache((uintptr_t)ptr, size);
  172. return ptr;
  173. }
  174. /**
  175. * Make the prev segment point to the next segment.
  176. * Change the last TRB in the prev segment to be a Link TRB which points to the
  177. * address of the next segment. The caller needs to set any Link TRB
  178. * related flags, such as End TRB, Toggle Cycle, and no snoop.
  179. *
  180. * @param prev pointer to the previous segment
  181. * @param next pointer to the next segment
  182. * @param link_trbs flag to indicate whether to link the trbs or NOT
  183. * @return none
  184. */
  185. static void xhci_link_segments(struct xhci_segment *prev,
  186. struct xhci_segment *next, bool link_trbs)
  187. {
  188. u32 val;
  189. u64 val_64 = 0;
  190. if (!prev || !next)
  191. return;
  192. prev->next = next;
  193. if (link_trbs) {
  194. val_64 = (uintptr_t)next->trbs;
  195. prev->trbs[TRBS_PER_SEGMENT-1].link.segment_ptr = val_64;
  196. /*
  197. * Set the last TRB in the segment to
  198. * have a TRB type ID of Link TRB
  199. */
  200. val = le32_to_cpu(prev->trbs[TRBS_PER_SEGMENT-1].link.control);
  201. val &= ~TRB_TYPE_BITMASK;
  202. val |= (TRB_LINK << TRB_TYPE_SHIFT);
  203. prev->trbs[TRBS_PER_SEGMENT-1].link.control = cpu_to_le32(val);
  204. }
  205. }
  206. /**
  207. * Initialises the Ring's enqueue,dequeue,enq_seg pointers
  208. *
  209. * @param ring pointer to the RING to be intialised
  210. * @return none
  211. */
  212. static void xhci_initialize_ring_info(struct xhci_ring *ring)
  213. {
  214. /*
  215. * The ring is empty, so the enqueue pointer == dequeue pointer
  216. */
  217. ring->enqueue = ring->first_seg->trbs;
  218. ring->enq_seg = ring->first_seg;
  219. ring->dequeue = ring->enqueue;
  220. ring->deq_seg = ring->first_seg;
  221. /*
  222. * The ring is initialized to 0. The producer must write 1 to the
  223. * cycle bit to handover ownership of the TRB, so PCS = 1.
  224. * The consumer must compare CCS to the cycle bit to
  225. * check ownership, so CCS = 1.
  226. */
  227. ring->cycle_state = 1;
  228. }
  229. /**
  230. * Allocates a generic ring segment from the ring pool, sets the dma address,
  231. * initializes the segment to zero, and sets the private next pointer to NULL.
  232. * Section 4.11.1.1:
  233. * "All components of all Command and Transfer TRBs shall be initialized to '0'"
  234. *
  235. * @param none
  236. * @return pointer to the newly allocated SEGMENT
  237. */
  238. static struct xhci_segment *xhci_segment_alloc(void)
  239. {
  240. struct xhci_segment *seg;
  241. seg = (struct xhci_segment *)malloc(sizeof(struct xhci_segment));
  242. BUG_ON(!seg);
  243. seg->trbs = (union xhci_trb *)xhci_malloc(SEGMENT_SIZE);
  244. seg->next = NULL;
  245. return seg;
  246. }
  247. /**
  248. * Create a new ring with zero or more segments.
  249. * TODO: current code only uses one-time-allocated single-segment rings
  250. * of 1KB anyway, so we might as well get rid of all the segment and
  251. * linking code (and maybe increase the size a bit, e.g. 4KB).
  252. *
  253. *
  254. * Link each segment together into a ring.
  255. * Set the end flag and the cycle toggle bit on the last segment.
  256. * See section 4.9.2 and figures 15 and 16 of XHCI spec rev1.0.
  257. *
  258. * @param num_segs number of segments in the ring
  259. * @param link_trbs flag to indicate whether to link the trbs or NOT
  260. * @return pointer to the newly created RING
  261. */
  262. struct xhci_ring *xhci_ring_alloc(unsigned int num_segs, bool link_trbs)
  263. {
  264. struct xhci_ring *ring;
  265. struct xhci_segment *prev;
  266. ring = (struct xhci_ring *)malloc(sizeof(struct xhci_ring));
  267. BUG_ON(!ring);
  268. if (num_segs == 0)
  269. return ring;
  270. ring->first_seg = xhci_segment_alloc();
  271. BUG_ON(!ring->first_seg);
  272. num_segs--;
  273. prev = ring->first_seg;
  274. while (num_segs > 0) {
  275. struct xhci_segment *next;
  276. next = xhci_segment_alloc();
  277. BUG_ON(!next);
  278. xhci_link_segments(prev, next, link_trbs);
  279. prev = next;
  280. num_segs--;
  281. }
  282. xhci_link_segments(prev, ring->first_seg, link_trbs);
  283. if (link_trbs) {
  284. /* See section 4.9.2.1 and 6.4.4.1 */
  285. prev->trbs[TRBS_PER_SEGMENT-1].link.control |=
  286. cpu_to_le32(LINK_TOGGLE);
  287. }
  288. xhci_initialize_ring_info(ring);
  289. return ring;
  290. }
  291. /**
  292. * Set up the scratchpad buffer array and scratchpad buffers
  293. *
  294. * @ctrl host controller data structure
  295. * @return -ENOMEM if buffer allocation fails, 0 on success
  296. */
  297. static int xhci_scratchpad_alloc(struct xhci_ctrl *ctrl)
  298. {
  299. struct xhci_hccr *hccr = ctrl->hccr;
  300. struct xhci_hcor *hcor = ctrl->hcor;
  301. struct xhci_scratchpad *scratchpad;
  302. int num_sp;
  303. uint32_t page_size;
  304. void *buf;
  305. int i;
  306. num_sp = HCS_MAX_SCRATCHPAD(xhci_readl(&hccr->cr_hcsparams2));
  307. if (!num_sp)
  308. return 0;
  309. scratchpad = malloc(sizeof(*scratchpad));
  310. if (!scratchpad)
  311. goto fail_sp;
  312. ctrl->scratchpad = scratchpad;
  313. scratchpad->sp_array = xhci_malloc(num_sp * sizeof(u64));
  314. if (!scratchpad->sp_array)
  315. goto fail_sp2;
  316. ctrl->dcbaa->dev_context_ptrs[0] =
  317. cpu_to_le64((uintptr_t)scratchpad->sp_array);
  318. page_size = xhci_readl(&hcor->or_pagesize) & 0xffff;
  319. for (i = 0; i < 16; i++) {
  320. if ((0x1 & page_size) != 0)
  321. break;
  322. page_size = page_size >> 1;
  323. }
  324. BUG_ON(i == 16);
  325. page_size = 1 << (i + 12);
  326. buf = memalign(page_size, num_sp * page_size);
  327. if (!buf)
  328. goto fail_sp3;
  329. memset(buf, '\0', num_sp * page_size);
  330. xhci_flush_cache((uintptr_t)buf, num_sp * page_size);
  331. for (i = 0; i < num_sp; i++) {
  332. uintptr_t ptr = (uintptr_t)buf + i * page_size;
  333. scratchpad->sp_array[i] = cpu_to_le64(ptr);
  334. }
  335. return 0;
  336. fail_sp3:
  337. free(scratchpad->sp_array);
  338. fail_sp2:
  339. free(scratchpad);
  340. ctrl->scratchpad = NULL;
  341. fail_sp:
  342. return -ENOMEM;
  343. }
  344. /**
  345. * Allocates the Container context
  346. *
  347. * @param ctrl Host controller data structure
  348. * @param type type of XHCI Container Context
  349. * @return NULL if failed else pointer to the context on success
  350. */
  351. static struct xhci_container_ctx
  352. *xhci_alloc_container_ctx(struct xhci_ctrl *ctrl, int type)
  353. {
  354. struct xhci_container_ctx *ctx;
  355. ctx = (struct xhci_container_ctx *)
  356. malloc(sizeof(struct xhci_container_ctx));
  357. BUG_ON(!ctx);
  358. BUG_ON((type != XHCI_CTX_TYPE_DEVICE) && (type != XHCI_CTX_TYPE_INPUT));
  359. ctx->type = type;
  360. ctx->size = (MAX_EP_CTX_NUM + 1) *
  361. CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
  362. if (type == XHCI_CTX_TYPE_INPUT)
  363. ctx->size += CTX_SIZE(readl(&ctrl->hccr->cr_hccparams));
  364. ctx->bytes = (u8 *)xhci_malloc(ctx->size);
  365. return ctx;
  366. }
  367. /**
  368. * Allocating virtual device
  369. *
  370. * @param udev pointer to USB deivce structure
  371. * @return 0 on success else -1 on failure
  372. */
  373. int xhci_alloc_virt_device(struct xhci_ctrl *ctrl, unsigned int slot_id)
  374. {
  375. u64 byte_64 = 0;
  376. struct xhci_virt_device *virt_dev;
  377. /* Slot ID 0 is reserved */
  378. if (ctrl->devs[slot_id]) {
  379. printf("Virt dev for slot[%d] already allocated\n", slot_id);
  380. return -EEXIST;
  381. }
  382. ctrl->devs[slot_id] = (struct xhci_virt_device *)
  383. malloc(sizeof(struct xhci_virt_device));
  384. if (!ctrl->devs[slot_id]) {
  385. puts("Failed to allocate virtual device\n");
  386. return -ENOMEM;
  387. }
  388. memset(ctrl->devs[slot_id], 0, sizeof(struct xhci_virt_device));
  389. virt_dev = ctrl->devs[slot_id];
  390. /* Allocate the (output) device context that will be used in the HC. */
  391. virt_dev->out_ctx = xhci_alloc_container_ctx(ctrl,
  392. XHCI_CTX_TYPE_DEVICE);
  393. if (!virt_dev->out_ctx) {
  394. puts("Failed to allocate out context for virt dev\n");
  395. return -ENOMEM;
  396. }
  397. /* Allocate the (input) device context for address device command */
  398. virt_dev->in_ctx = xhci_alloc_container_ctx(ctrl,
  399. XHCI_CTX_TYPE_INPUT);
  400. if (!virt_dev->in_ctx) {
  401. puts("Failed to allocate in context for virt dev\n");
  402. return -ENOMEM;
  403. }
  404. /* Allocate endpoint 0 ring */
  405. virt_dev->eps[0].ring = xhci_ring_alloc(1, true);
  406. byte_64 = (uintptr_t)(virt_dev->out_ctx->bytes);
  407. /* Point to output device context in dcbaa. */
  408. ctrl->dcbaa->dev_context_ptrs[slot_id] = byte_64;
  409. xhci_flush_cache((uintptr_t)&ctrl->dcbaa->dev_context_ptrs[slot_id],
  410. sizeof(__le64));
  411. return 0;
  412. }
  413. /**
  414. * Allocates the necessary data structures
  415. * for XHCI host controller
  416. *
  417. * @param ctrl Host controller data structure
  418. * @param hccr pointer to HOST Controller Control Registers
  419. * @param hcor pointer to HOST Controller Operational Registers
  420. * @return 0 if successful else -1 on failure
  421. */
  422. int xhci_mem_init(struct xhci_ctrl *ctrl, struct xhci_hccr *hccr,
  423. struct xhci_hcor *hcor)
  424. {
  425. uint64_t val_64;
  426. uint64_t trb_64;
  427. uint32_t val;
  428. unsigned long deq;
  429. int i;
  430. struct xhci_segment *seg;
  431. /* DCBAA initialization */
  432. ctrl->dcbaa = (struct xhci_device_context_array *)
  433. xhci_malloc(sizeof(struct xhci_device_context_array));
  434. if (ctrl->dcbaa == NULL) {
  435. puts("unable to allocate DCBA\n");
  436. return -ENOMEM;
  437. }
  438. val_64 = (uintptr_t)ctrl->dcbaa;
  439. /* Set the pointer in DCBAA register */
  440. xhci_writeq(&hcor->or_dcbaap, val_64);
  441. /* Command ring control pointer register initialization */
  442. ctrl->cmd_ring = xhci_ring_alloc(1, true);
  443. /* Set the address in the Command Ring Control register */
  444. trb_64 = (uintptr_t)ctrl->cmd_ring->first_seg->trbs;
  445. val_64 = xhci_readq(&hcor->or_crcr);
  446. val_64 = (val_64 & (u64) CMD_RING_RSVD_BITS) |
  447. (trb_64 & (u64) ~CMD_RING_RSVD_BITS) |
  448. ctrl->cmd_ring->cycle_state;
  449. xhci_writeq(&hcor->or_crcr, val_64);
  450. /* write the address of db register */
  451. val = xhci_readl(&hccr->cr_dboff);
  452. val &= DBOFF_MASK;
  453. ctrl->dba = (struct xhci_doorbell_array *)((char *)hccr + val);
  454. /* write the address of runtime register */
  455. val = xhci_readl(&hccr->cr_rtsoff);
  456. val &= RTSOFF_MASK;
  457. ctrl->run_regs = (struct xhci_run_regs *)((char *)hccr + val);
  458. /* writting the address of ir_set structure */
  459. ctrl->ir_set = &ctrl->run_regs->ir_set[0];
  460. /* Event ring does not maintain link TRB */
  461. ctrl->event_ring = xhci_ring_alloc(ERST_NUM_SEGS, false);
  462. ctrl->erst.entries = (struct xhci_erst_entry *)
  463. xhci_malloc(sizeof(struct xhci_erst_entry) * ERST_NUM_SEGS);
  464. ctrl->erst.num_entries = ERST_NUM_SEGS;
  465. for (val = 0, seg = ctrl->event_ring->first_seg;
  466. val < ERST_NUM_SEGS;
  467. val++) {
  468. trb_64 = 0;
  469. trb_64 = (uintptr_t)seg->trbs;
  470. struct xhci_erst_entry *entry = &ctrl->erst.entries[val];
  471. xhci_writeq(&entry->seg_addr, trb_64);
  472. entry->seg_size = cpu_to_le32(TRBS_PER_SEGMENT);
  473. entry->rsvd = 0;
  474. seg = seg->next;
  475. }
  476. xhci_flush_cache((uintptr_t)ctrl->erst.entries,
  477. ERST_NUM_SEGS * sizeof(struct xhci_erst_entry));
  478. deq = (unsigned long)ctrl->event_ring->dequeue;
  479. /* Update HC event ring dequeue pointer */
  480. xhci_writeq(&ctrl->ir_set->erst_dequeue,
  481. (u64)deq & (u64)~ERST_PTR_MASK);
  482. /* set ERST count with the number of entries in the segment table */
  483. val = xhci_readl(&ctrl->ir_set->erst_size);
  484. val &= ERST_SIZE_MASK;
  485. val |= ERST_NUM_SEGS;
  486. xhci_writel(&ctrl->ir_set->erst_size, val);
  487. /* this is the event ring segment table pointer */
  488. val_64 = xhci_readq(&ctrl->ir_set->erst_base);
  489. val_64 &= ERST_PTR_MASK;
  490. val_64 |= ((uintptr_t)(ctrl->erst.entries) & ~ERST_PTR_MASK);
  491. xhci_writeq(&ctrl->ir_set->erst_base, val_64);
  492. /* set up the scratchpad buffer array and scratchpad buffers */
  493. xhci_scratchpad_alloc(ctrl);
  494. /* initializing the virtual devices to NULL */
  495. for (i = 0; i < MAX_HC_SLOTS; ++i)
  496. ctrl->devs[i] = NULL;
  497. /*
  498. * Just Zero'ing this register completely,
  499. * or some spurious Device Notification Events
  500. * might screw things here.
  501. */
  502. xhci_writel(&hcor->or_dnctrl, 0x0);
  503. return 0;
  504. }
  505. /**
  506. * Give the input control context for the passed container context
  507. *
  508. * @param ctx pointer to the context
  509. * @return pointer to the Input control context data
  510. */
  511. struct xhci_input_control_ctx
  512. *xhci_get_input_control_ctx(struct xhci_container_ctx *ctx)
  513. {
  514. BUG_ON(ctx->type != XHCI_CTX_TYPE_INPUT);
  515. return (struct xhci_input_control_ctx *)ctx->bytes;
  516. }
  517. /**
  518. * Give the slot context for the passed container context
  519. *
  520. * @param ctrl Host controller data structure
  521. * @param ctx pointer to the context
  522. * @return pointer to the slot control context data
  523. */
  524. struct xhci_slot_ctx *xhci_get_slot_ctx(struct xhci_ctrl *ctrl,
  525. struct xhci_container_ctx *ctx)
  526. {
  527. if (ctx->type == XHCI_CTX_TYPE_DEVICE)
  528. return (struct xhci_slot_ctx *)ctx->bytes;
  529. return (struct xhci_slot_ctx *)
  530. (ctx->bytes + CTX_SIZE(readl(&ctrl->hccr->cr_hccparams)));
  531. }
  532. /**
  533. * Gets the EP context from based on the ep_index
  534. *
  535. * @param ctrl Host controller data structure
  536. * @param ctx context container
  537. * @param ep_index index of the endpoint
  538. * @return pointer to the End point context
  539. */
  540. struct xhci_ep_ctx *xhci_get_ep_ctx(struct xhci_ctrl *ctrl,
  541. struct xhci_container_ctx *ctx,
  542. unsigned int ep_index)
  543. {
  544. /* increment ep index by offset of start of ep ctx array */
  545. ep_index++;
  546. if (ctx->type == XHCI_CTX_TYPE_INPUT)
  547. ep_index++;
  548. return (struct xhci_ep_ctx *)
  549. (ctx->bytes +
  550. (ep_index * CTX_SIZE(readl(&ctrl->hccr->cr_hccparams))));
  551. }
  552. /**
  553. * Copy output xhci_ep_ctx to the input xhci_ep_ctx copy.
  554. * Useful when you want to change one particular aspect of the endpoint
  555. * and then issue a configure endpoint command.
  556. *
  557. * @param ctrl Host controller data structure
  558. * @param in_ctx contains the input context
  559. * @param out_ctx contains the input context
  560. * @param ep_index index of the end point
  561. * @return none
  562. */
  563. void xhci_endpoint_copy(struct xhci_ctrl *ctrl,
  564. struct xhci_container_ctx *in_ctx,
  565. struct xhci_container_ctx *out_ctx,
  566. unsigned int ep_index)
  567. {
  568. struct xhci_ep_ctx *out_ep_ctx;
  569. struct xhci_ep_ctx *in_ep_ctx;
  570. out_ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
  571. in_ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  572. in_ep_ctx->ep_info = out_ep_ctx->ep_info;
  573. in_ep_ctx->ep_info2 = out_ep_ctx->ep_info2;
  574. in_ep_ctx->deq = out_ep_ctx->deq;
  575. in_ep_ctx->tx_info = out_ep_ctx->tx_info;
  576. }
  577. /**
  578. * Copy output xhci_slot_ctx to the input xhci_slot_ctx.
  579. * Useful when you want to change one particular aspect of the endpoint
  580. * and then issue a configure endpoint command.
  581. * Only the context entries field matters, but
  582. * we'll copy the whole thing anyway.
  583. *
  584. * @param ctrl Host controller data structure
  585. * @param in_ctx contains the inpout context
  586. * @param out_ctx contains the inpout context
  587. * @return none
  588. */
  589. void xhci_slot_copy(struct xhci_ctrl *ctrl, struct xhci_container_ctx *in_ctx,
  590. struct xhci_container_ctx *out_ctx)
  591. {
  592. struct xhci_slot_ctx *in_slot_ctx;
  593. struct xhci_slot_ctx *out_slot_ctx;
  594. in_slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  595. out_slot_ctx = xhci_get_slot_ctx(ctrl, out_ctx);
  596. in_slot_ctx->dev_info = out_slot_ctx->dev_info;
  597. in_slot_ctx->dev_info2 = out_slot_ctx->dev_info2;
  598. in_slot_ctx->tt_info = out_slot_ctx->tt_info;
  599. in_slot_ctx->dev_state = out_slot_ctx->dev_state;
  600. }
  601. /**
  602. * Setup an xHCI virtual device for a Set Address command
  603. *
  604. * @param udev pointer to the Device Data Structure
  605. * @return returns negative value on failure else 0 on success
  606. */
  607. void xhci_setup_addressable_virt_dev(struct xhci_ctrl *ctrl,
  608. struct usb_device *udev, int hop_portnr)
  609. {
  610. struct xhci_virt_device *virt_dev;
  611. struct xhci_ep_ctx *ep0_ctx;
  612. struct xhci_slot_ctx *slot_ctx;
  613. u32 port_num = 0;
  614. u64 trb_64 = 0;
  615. int slot_id = udev->slot_id;
  616. int speed = udev->speed;
  617. int route = 0;
  618. #ifdef CONFIG_DM_USB
  619. struct usb_device *dev = udev;
  620. struct usb_hub_device *hub;
  621. #endif
  622. virt_dev = ctrl->devs[slot_id];
  623. BUG_ON(!virt_dev);
  624. /* Extract the EP0 and Slot Ctrl */
  625. ep0_ctx = xhci_get_ep_ctx(ctrl, virt_dev->in_ctx, 0);
  626. slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->in_ctx);
  627. /* Only the control endpoint is valid - one endpoint context */
  628. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(1));
  629. #ifdef CONFIG_DM_USB
  630. /* Calculate the route string for this device */
  631. port_num = dev->portnr;
  632. while (!usb_hub_is_root_hub(dev->dev)) {
  633. hub = dev_get_uclass_priv(dev->dev);
  634. /*
  635. * Each hub in the topology is expected to have no more than
  636. * 15 ports in order for the route string of a device to be
  637. * unique. SuperSpeed hubs are restricted to only having 15
  638. * ports, but FS/LS/HS hubs are not. The xHCI specification
  639. * says that if the port number the device is greater than 15,
  640. * that portion of the route string shall be set to 15.
  641. */
  642. if (port_num > 15)
  643. port_num = 15;
  644. route |= port_num << (hub->hub_depth * 4);
  645. dev = dev_get_parent_priv(dev->dev);
  646. port_num = dev->portnr;
  647. dev = dev_get_parent_priv(dev->dev->parent);
  648. }
  649. debug("route string %x\n", route);
  650. #endif
  651. slot_ctx->dev_info |= route;
  652. switch (speed) {
  653. case USB_SPEED_SUPER:
  654. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_SS);
  655. break;
  656. case USB_SPEED_HIGH:
  657. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_HS);
  658. break;
  659. case USB_SPEED_FULL:
  660. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_FS);
  661. break;
  662. case USB_SPEED_LOW:
  663. slot_ctx->dev_info |= cpu_to_le32(SLOT_SPEED_LS);
  664. break;
  665. default:
  666. /* Speed was set earlier, this shouldn't happen. */
  667. BUG();
  668. }
  669. #ifdef CONFIG_DM_USB
  670. /* Set up TT fields to support FS/LS devices */
  671. if (speed == USB_SPEED_LOW || speed == USB_SPEED_FULL) {
  672. struct udevice *parent = udev->dev;
  673. dev = udev;
  674. do {
  675. port_num = dev->portnr;
  676. dev = dev_get_parent_priv(parent);
  677. if (usb_hub_is_root_hub(dev->dev))
  678. break;
  679. parent = dev->dev->parent;
  680. } while (dev->speed != USB_SPEED_HIGH);
  681. if (!usb_hub_is_root_hub(dev->dev)) {
  682. hub = dev_get_uclass_priv(dev->dev);
  683. if (hub->tt.multi)
  684. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  685. slot_ctx->tt_info |= cpu_to_le32(TT_PORT(port_num));
  686. slot_ctx->tt_info |= cpu_to_le32(TT_SLOT(dev->slot_id));
  687. }
  688. }
  689. #endif
  690. port_num = hop_portnr;
  691. debug("port_num = %d\n", port_num);
  692. slot_ctx->dev_info2 |=
  693. cpu_to_le32(((port_num & ROOT_HUB_PORT_MASK) <<
  694. ROOT_HUB_PORT_SHIFT));
  695. /* Step 4 - ring already allocated */
  696. /* Step 5 */
  697. ep0_ctx->ep_info2 = cpu_to_le32(CTRL_EP << EP_TYPE_SHIFT);
  698. debug("SPEED = %d\n", speed);
  699. switch (speed) {
  700. case USB_SPEED_SUPER:
  701. ep0_ctx->ep_info2 |= cpu_to_le32(((512 & MAX_PACKET_MASK) <<
  702. MAX_PACKET_SHIFT));
  703. debug("Setting Packet size = 512bytes\n");
  704. break;
  705. case USB_SPEED_HIGH:
  706. /* USB core guesses at a 64-byte max packet first for FS devices */
  707. case USB_SPEED_FULL:
  708. ep0_ctx->ep_info2 |= cpu_to_le32(((64 & MAX_PACKET_MASK) <<
  709. MAX_PACKET_SHIFT));
  710. debug("Setting Packet size = 64bytes\n");
  711. break;
  712. case USB_SPEED_LOW:
  713. ep0_ctx->ep_info2 |= cpu_to_le32(((8 & MAX_PACKET_MASK) <<
  714. MAX_PACKET_SHIFT));
  715. debug("Setting Packet size = 8bytes\n");
  716. break;
  717. default:
  718. /* New speed? */
  719. BUG();
  720. }
  721. /* EP 0 can handle "burst" sizes of 1, so Max Burst Size field is 0 */
  722. ep0_ctx->ep_info2 |=
  723. cpu_to_le32(((0 & MAX_BURST_MASK) << MAX_BURST_SHIFT) |
  724. ((3 & ERROR_COUNT_MASK) << ERROR_COUNT_SHIFT));
  725. trb_64 = (uintptr_t)virt_dev->eps[0].ring->first_seg->trbs;
  726. ep0_ctx->deq = cpu_to_le64(trb_64 | virt_dev->eps[0].ring->cycle_state);
  727. /*
  728. * xHCI spec 6.2.3:
  729. * software shall set 'Average TRB Length' to 8 for control endpoints.
  730. */
  731. ep0_ctx->tx_info = cpu_to_le32(EP_AVG_TRB_LENGTH(8));
  732. /* Steps 7 and 8 were done in xhci_alloc_virt_device() */
  733. xhci_flush_cache((uintptr_t)ep0_ctx, sizeof(struct xhci_ep_ctx));
  734. xhci_flush_cache((uintptr_t)slot_ctx, sizeof(struct xhci_slot_ctx));
  735. }