xhci-keystone.c 5.6 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB 3.0 DRD Controller
  4. *
  5. * (C) Copyright 2012-2014
  6. * Texas Instruments Incorporated, <www.ti.com>
  7. */
  8. #include <common.h>
  9. #include <watchdog.h>
  10. #include <usb.h>
  11. #include <asm/arch/psc_defs.h>
  12. #include <asm/io.h>
  13. #include <linux/usb/dwc3.h>
  14. #include <asm/arch/xhci-keystone.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include "xhci.h"
  18. struct kdwc3_irq_regs {
  19. u32 revision; /* 0x000 */
  20. u32 rsvd0[3];
  21. u32 sysconfig; /* 0x010 */
  22. u32 rsvd1[1];
  23. u32 irq_eoi;
  24. u32 rsvd2[1];
  25. struct {
  26. u32 raw_status;
  27. u32 status;
  28. u32 enable_set;
  29. u32 enable_clr;
  30. } irqs[16];
  31. };
  32. struct keystone_xhci {
  33. struct xhci_hccr *hcd;
  34. struct dwc3 *dwc3_reg;
  35. struct xhci_hcor *hcor;
  36. struct kdwc3_irq_regs *usbss;
  37. struct keystone_xhci_phy *phy;
  38. };
  39. struct keystone_xhci keystone;
  40. static void keystone_xhci_phy_set(struct keystone_xhci_phy *phy)
  41. {
  42. u32 val;
  43. /*
  44. * VBUSVLDEXTSEL has a default value of 1 in BootCfg but shouldn't.
  45. * It should always be cleared because our USB PHY has an onchip VBUS
  46. * analog comparator.
  47. */
  48. val = readl(&phy->phy_clock);
  49. /* quit selecting the vbusvldextsel by default! */
  50. val &= ~USB3_PHY_OTG_VBUSVLDECTSEL;
  51. writel(val, &phy->phy_clock);
  52. }
  53. static void keystone_xhci_phy_unset(struct keystone_xhci_phy *phy)
  54. {
  55. u32 val;
  56. /* Disable the PHY REFCLK clock gate */
  57. val = readl(&phy->phy_clock);
  58. val &= ~USB3_PHY_REF_SSP_EN;
  59. writel(val, &phy->phy_clock);
  60. }
  61. static int keystone_xhci_core_init(struct dwc3 *dwc3_reg)
  62. {
  63. int ret;
  64. ret = dwc3_core_init(dwc3_reg);
  65. if (ret) {
  66. debug("failed to initialize core\n");
  67. return -EINVAL;
  68. }
  69. /* We are hard-coding DWC3 core to Host Mode */
  70. dwc3_set_mode(dwc3_reg, DWC3_GCTL_PRTCAP_HOST);
  71. return 0;
  72. }
  73. int xhci_hcd_init(int index,
  74. struct xhci_hccr **ret_hccr, struct xhci_hcor **ret_hcor)
  75. {
  76. u32 val;
  77. int ret;
  78. struct xhci_hccr *hcd;
  79. struct xhci_hcor *hcor;
  80. struct kdwc3_irq_regs *usbss;
  81. struct keystone_xhci_phy *phy;
  82. usbss = (struct kdwc3_irq_regs *)CONFIG_USB_SS_BASE;
  83. phy = (struct keystone_xhci_phy *)CONFIG_DEV_USB_PHY_BASE;
  84. /* Enable the PHY REFCLK clock gate with phy_ref_ssp_en = 1 */
  85. val = readl(&(phy->phy_clock));
  86. val |= USB3_PHY_REF_SSP_EN;
  87. writel(val, &phy->phy_clock);
  88. mdelay(100);
  89. /* Release USB from reset */
  90. ret = psc_enable_module(KS2_LPSC_USB);
  91. if (ret) {
  92. puts("Cannot enable USB module");
  93. return -1;
  94. }
  95. mdelay(100);
  96. /* Initialize usb phy */
  97. keystone_xhci_phy_set(phy);
  98. /* soft reset usbss */
  99. writel(1, &usbss->sysconfig);
  100. while (readl(&usbss->sysconfig) & 1)
  101. ;
  102. val = readl(&usbss->revision);
  103. debug("usbss revision %x\n", val);
  104. /* Initialize usb core */
  105. hcd = (struct xhci_hccr *)CONFIG_USB_HOST_XHCI_BASE;
  106. keystone.dwc3_reg = (struct dwc3 *)(CONFIG_USB_HOST_XHCI_BASE +
  107. DWC3_REG_OFFSET);
  108. keystone_xhci_core_init(keystone.dwc3_reg);
  109. /* set register addresses */
  110. hcor = (struct xhci_hcor *)((uint32_t)hcd +
  111. HC_LENGTH(readl(&hcd->cr_capbase)));
  112. debug("Keystone2-xhci: init hccr %08x and hcor %08x hc_length %d\n",
  113. (u32)hcd, (u32)hcor,
  114. (u32)HC_LENGTH(xhci_readl(&hcd->cr_capbase)));
  115. keystone.usbss = usbss;
  116. keystone.phy = phy;
  117. keystone.hcd = hcd;
  118. keystone.hcor = hcor;
  119. *ret_hccr = hcd;
  120. *ret_hcor = hcor;
  121. return 0;
  122. }
  123. static int keystone_xhci_phy_suspend(void)
  124. {
  125. int loop_cnt = 0;
  126. struct xhci_hcor *hcor;
  127. uint32_t *portsc_1 = NULL;
  128. uint32_t *portsc_2 = NULL;
  129. u32 val, usb2_pls, usb3_pls, event_q;
  130. struct dwc3 *dwc3_reg = keystone.dwc3_reg;
  131. /* set register addresses */
  132. hcor = keystone.hcor;
  133. /* Bypass Scrambling and Set Shorter Training sequence for simulation */
  134. val = DWC3_GCTL_PWRDNSCALE(0x4b0) | DWC3_GCTL_PRTCAPDIR(0x2);
  135. writel(val, &dwc3_reg->g_ctl);
  136. /* GUSB2PHYCFG */
  137. val = readl(&dwc3_reg->g_usb2phycfg[0]);
  138. /* assert bit 6 (SusPhy) */
  139. val |= DWC3_GUSB2PHYCFG_SUSPHY;
  140. writel(val, &dwc3_reg->g_usb2phycfg[0]);
  141. /* GUSB3PIPECTL */
  142. val = readl(&dwc3_reg->g_usb3pipectl[0]);
  143. /*
  144. * assert bit 29 to allow PHY to go to suspend when idle
  145. * and cause the USB3 SS PHY to enter suspend mode
  146. */
  147. val |= (BIT(29) | DWC3_GUSB3PIPECTL_SUSPHY);
  148. writel(val, &dwc3_reg->g_usb3pipectl[0]);
  149. /*
  150. * Steps necessary to allow controller to suspend even when
  151. * VBUS is HIGH:
  152. * - Init DCFG[2:0] (DevSpd) to: 1=FS
  153. * - Init GEVNTADR0 to point to an eventQ
  154. * - Init GEVNTSIZ0 to 0x0100 to specify the size of the eventQ
  155. * - Init DCTL::Run_nStop = 1
  156. */
  157. writel(0x00020001, &dwc3_reg->d_cfg);
  158. /* TODO: local2global( (Uint32) eventQ )? */
  159. writel((u32)&event_q, &dwc3_reg->g_evnt_buf[0].g_evntadrlo);
  160. writel(0, &dwc3_reg->g_evnt_buf[0].g_evntadrhi);
  161. writel(0x4, &dwc3_reg->g_evnt_buf[0].g_evntsiz);
  162. /* Run */
  163. writel(DWC3_DCTL_RUN_STOP, &dwc3_reg->d_ctl);
  164. mdelay(100);
  165. /* Wait for USB2 & USB3 PORTSC::PortLinkState to indicate suspend */
  166. portsc_1 = (uint32_t *)(&hcor->portregs[0].or_portsc);
  167. portsc_2 = (uint32_t *)(&hcor->portregs[1].or_portsc);
  168. usb2_pls = 0;
  169. usb3_pls = 0;
  170. do {
  171. ++loop_cnt;
  172. usb2_pls = (readl(portsc_1) & PORT_PLS_MASK) >> 5;
  173. usb3_pls = (readl(portsc_2) & PORT_PLS_MASK) >> 5;
  174. } while (((usb2_pls != 0x4) || (usb3_pls != 0x4)) && loop_cnt < 1000);
  175. if (usb2_pls != 0x4 || usb3_pls != 0x4) {
  176. debug("USB suspend failed - PLS USB2=%02x, USB3=%02x\n",
  177. usb2_pls, usb3_pls);
  178. return -1;
  179. }
  180. debug("USB2 and USB3 PLS - Disabled, loop_cnt=%d\n", loop_cnt);
  181. return 0;
  182. }
  183. void xhci_hcd_stop(int index)
  184. {
  185. /* Disable USB */
  186. if (keystone_xhci_phy_suspend())
  187. return;
  188. if (psc_disable_module(KS2_LPSC_USB)) {
  189. debug("PSC disable module USB failed!\n");
  190. return;
  191. }
  192. /* Disable PHY */
  193. keystone_xhci_phy_unset(keystone.phy);
  194. /* memset(&keystone, 0, sizeof(struct keystone_xhci)); */
  195. debug("xhci_hcd_stop OK.\n");
  196. }