r8a66597.h 22 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * R8A66597 HCD (Host Controller Driver) for u-boot
  4. *
  5. * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  6. */
  7. #ifndef __R8A66597_H__
  8. #define __R8A66597_H__
  9. #define SYSCFG0 0x00
  10. #define SYSCFG1 0x02
  11. #define SYSSTS0 0x04
  12. #define SYSSTS1 0x06
  13. #define DVSTCTR0 0x08
  14. #define DVSTCTR1 0x0A
  15. #define TESTMODE 0x0C
  16. #define PINCFG 0x0E
  17. #define DMA0CFG 0x10
  18. #define DMA1CFG 0x12
  19. #define CFIFO 0x14
  20. #define D0FIFO 0x18
  21. #define D1FIFO 0x1C
  22. #define CFIFOSEL 0x20
  23. #define CFIFOCTR 0x22
  24. #define CFIFOSIE 0x24
  25. #define D0FIFOSEL 0x28
  26. #define D0FIFOCTR 0x2A
  27. #define D1FIFOSEL 0x2C
  28. #define D1FIFOCTR 0x2E
  29. #define INTENB0 0x30
  30. #define INTENB1 0x32
  31. #define INTENB2 0x34
  32. #define BRDYENB 0x36
  33. #define NRDYENB 0x38
  34. #define BEMPENB 0x3A
  35. #define SOFCFG 0x3C
  36. #define INTSTS0 0x40
  37. #define INTSTS1 0x42
  38. #define INTSTS2 0x44
  39. #define BRDYSTS 0x46
  40. #define NRDYSTS 0x48
  41. #define BEMPSTS 0x4A
  42. #define FRMNUM 0x4C
  43. #define UFRMNUM 0x4E
  44. #define USBADDR 0x50
  45. #define USBREQ 0x54
  46. #define USBVAL 0x56
  47. #define USBINDX 0x58
  48. #define USBLENG 0x5A
  49. #define DCPCFG 0x5C
  50. #define DCPMAXP 0x5E
  51. #define DCPCTR 0x60
  52. #define PIPESEL 0x64
  53. #define PIPECFG 0x68
  54. #define PIPEBUF 0x6A
  55. #define PIPEMAXP 0x6C
  56. #define PIPEPERI 0x6E
  57. #define PIPE1CTR 0x70
  58. #define PIPE2CTR 0x72
  59. #define PIPE3CTR 0x74
  60. #define PIPE4CTR 0x76
  61. #define PIPE5CTR 0x78
  62. #define PIPE6CTR 0x7A
  63. #define PIPE7CTR 0x7C
  64. #define PIPE8CTR 0x7E
  65. #define PIPE9CTR 0x80
  66. #define PIPE1TRE 0x90
  67. #define PIPE1TRN 0x92
  68. #define PIPE2TRE 0x94
  69. #define PIPE2TRN 0x96
  70. #define PIPE3TRE 0x98
  71. #define PIPE3TRN 0x9A
  72. #define PIPE4TRE 0x9C
  73. #define PIPE4TRN 0x9E
  74. #define PIPE5TRE 0xA0
  75. #define PIPE5TRN 0xA2
  76. #define DEVADD0 0xD0
  77. #define DEVADD1 0xD2
  78. #define DEVADD2 0xD4
  79. #define DEVADD3 0xD6
  80. #define DEVADD4 0xD8
  81. #define DEVADD5 0xDA
  82. #define DEVADD6 0xDC
  83. #define DEVADD7 0xDE
  84. #define DEVADD8 0xE0
  85. #define DEVADD9 0xE2
  86. #define DEVADDA 0xE4
  87. #define SUSPMODE0 0x102 /* RZ/A only */
  88. /* System Configuration Control Register */
  89. #if !defined(CONFIG_RZA_USB)
  90. #define XTAL 0xC000 /* b15-14: Crystal selection */
  91. #define XTAL48 0x8000 /* 48MHz */
  92. #define XTAL24 0x4000 /* 24MHz */
  93. #define XTAL12 0x0000 /* 12MHz */
  94. #define XCKE 0x2000 /* b13: External clock enable */
  95. #define PLLC 0x0800 /* b11: PLL control */
  96. #define SCKE 0x0400 /* b10: USB clock enable */
  97. #define PCSDIS 0x0200 /* b9: not CS wakeup */
  98. #define LPSME 0x0100 /* b8: Low power sleep mode */
  99. #endif
  100. #define HSE 0x0080 /* b7: Hi-speed enable */
  101. #define DCFM 0x0040 /* b6: Controller function select */
  102. #define DRPD 0x0020 /* b5: D+/- pull down control */
  103. #define DPRPU 0x0010 /* b4: D+ pull up control */
  104. #if defined(CONFIG_RZA_USB)
  105. #define XTAL 0x0004 /* b2: Crystal selection */
  106. #define XTAL12 0x0004 /* 12MHz */
  107. #define XTAL48 0x0000 /* 48MHz */
  108. #define UPLLE 0x0002 /* b1: internal PLL control */
  109. #endif
  110. #define USBE 0x0001 /* b0: USB module operation enable */
  111. /* System Configuration Status Register */
  112. #define OVCBIT 0x8000 /* b15-14: Over-current bit */
  113. #define OVCMON 0xC000 /* b15-14: Over-current monitor */
  114. #define SOFEA 0x0020 /* b5: SOF monitor */
  115. #define IDMON 0x0004 /* b3: ID-pin monitor */
  116. #define LNST 0x0003 /* b1-0: D+, D- line status */
  117. #define SE1 0x0003 /* SE1 */
  118. #define FS_KSTS 0x0002 /* Full-Speed K State */
  119. #define FS_JSTS 0x0001 /* Full-Speed J State */
  120. #define LS_JSTS 0x0002 /* Low-Speed J State */
  121. #define LS_KSTS 0x0001 /* Low-Speed K State */
  122. #define SE0 0x0000 /* SE0 */
  123. /* Device State Control Register */
  124. #define EXTLP0 0x0400 /* b10: External port */
  125. #define VBOUT 0x0200 /* b9: VBUS output */
  126. #define WKUP 0x0100 /* b8: Remote wakeup */
  127. #define RWUPE 0x0080 /* b7: Remote wakeup sense */
  128. #define USBRST 0x0040 /* b6: USB reset enable */
  129. #define RESUME 0x0020 /* b5: Resume enable */
  130. #define UACT 0x0010 /* b4: USB bus enable */
  131. #define RHST 0x0007 /* b1-0: Reset handshake status */
  132. #define HSPROC 0x0004 /* HS handshake is processing */
  133. #define HSMODE 0x0003 /* Hi-Speed mode */
  134. #define FSMODE 0x0002 /* Full-Speed mode */
  135. #define LSMODE 0x0001 /* Low-Speed mode */
  136. #define UNDECID 0x0000 /* Undecided */
  137. /* Test Mode Register */
  138. #define UTST 0x000F /* b3-0: Test select */
  139. #define H_TST_PACKET 0x000C /* HOST TEST Packet */
  140. #define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
  141. #define H_TST_K 0x000A /* HOST TEST K */
  142. #define H_TST_J 0x0009 /* HOST TEST J */
  143. #define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
  144. #define P_TST_PACKET 0x0004 /* PERI TEST Packet */
  145. #define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
  146. #define P_TST_K 0x0002 /* PERI TEST K */
  147. #define P_TST_J 0x0001 /* PERI TEST J */
  148. #define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
  149. /* Data Pin Configuration Register */
  150. #define LDRV 0x8000 /* b15: Drive Current Adjust */
  151. #define VIF1 0x0000 /* VIF = 1.8V */
  152. #define VIF3 0x8000 /* VIF = 3.3V */
  153. #define INTA 0x0001 /* b1: USB INT-pin active */
  154. /* DMAx Pin Configuration Register */
  155. #define DREQA 0x4000 /* b14: Dreq active select */
  156. #define BURST 0x2000 /* b13: Burst mode */
  157. #define DACKA 0x0400 /* b10: Dack active select */
  158. #define DFORM 0x0380 /* b9-7: DMA mode select */
  159. #define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
  160. #define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
  161. #define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
  162. #define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
  163. #define DENDA 0x0040 /* b6: Dend active select */
  164. #define PKTM 0x0020 /* b5: Packet mode */
  165. #define DENDE 0x0010 /* b4: Dend enable */
  166. #define OBUS 0x0004 /* b2: OUTbus mode */
  167. /* CFIFO/DxFIFO Port Select Register */
  168. #define RCNT 0x8000 /* b15: Read count mode */
  169. #define REW 0x4000 /* b14: Buffer rewind */
  170. #define DCLRM 0x2000 /* b13: DMA buffer clear mode */
  171. #define DREQE 0x1000 /* b12: DREQ output enable */
  172. #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
  173. #define MBW 0x0800
  174. #else
  175. #if !defined(CONFIG_RZA_USB)
  176. #define MBW 0x0400 /* b10: Maximum bit width for FIFO access */
  177. #else
  178. #define MBW 0x0800 /* b10: Maximum bit width for FIFO access */
  179. #endif
  180. #endif
  181. #define MBW_8 0x0000 /* 8bit */
  182. #define MBW_16 0x0400 /* 16bit */
  183. #define MBW_32 0x0800 /* 32bit */
  184. #define BIGEND 0x0100 /* b8: Big endian mode */
  185. #define BYTE_LITTLE 0x0000 /* little dendian */
  186. #define BYTE_BIG 0x0100 /* big endifan */
  187. #define ISEL 0x0020 /* b5: DCP FIFO port direction select */
  188. #define CURPIPE 0x000F /* b2-0: PIPE select */
  189. /* CFIFO/DxFIFO Port Control Register */
  190. #define BVAL 0x8000 /* b15: Buffer valid flag */
  191. #define BCLR 0x4000 /* b14: Buffer clear */
  192. #define FRDY 0x2000 /* b13: FIFO ready */
  193. #define DTLN 0x0FFF /* b11-0: FIFO received data length */
  194. /* Interrupt Enable Register 0 */
  195. #define VBSE 0x8000 /* b15: VBUS interrupt */
  196. #define RSME 0x4000 /* b14: Resume interrupt */
  197. #define SOFE 0x2000 /* b13: Frame update interrupt */
  198. #define DVSE 0x1000 /* b12: Device state transition interrupt */
  199. #define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
  200. #define BEMPE 0x0400 /* b10: Buffer empty interrupt */
  201. #define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
  202. #define BRDYE 0x0100 /* b8: Buffer ready interrupt */
  203. /* Interrupt Enable Register 1 */
  204. #define OVRCRE 0x8000 /* b15: Over-current interrupt */
  205. #define BCHGE 0x4000 /* b14: USB us chenge interrupt */
  206. #define DTCHE 0x1000 /* b12: Detach sense interrupt */
  207. #define ATTCHE 0x0800 /* b11: Attach sense interrupt */
  208. #define EOFERRE 0x0040 /* b6: EOF error interrupt */
  209. #define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
  210. #define SACKE 0x0010 /* b4: SETUP ACK interrupt */
  211. /* BRDY Interrupt Enable/Status Register */
  212. #define BRDY9 0x0200 /* b9: PIPE9 */
  213. #define BRDY8 0x0100 /* b8: PIPE8 */
  214. #define BRDY7 0x0080 /* b7: PIPE7 */
  215. #define BRDY6 0x0040 /* b6: PIPE6 */
  216. #define BRDY5 0x0020 /* b5: PIPE5 */
  217. #define BRDY4 0x0010 /* b4: PIPE4 */
  218. #define BRDY3 0x0008 /* b3: PIPE3 */
  219. #define BRDY2 0x0004 /* b2: PIPE2 */
  220. #define BRDY1 0x0002 /* b1: PIPE1 */
  221. #define BRDY0 0x0001 /* b1: PIPE0 */
  222. /* NRDY Interrupt Enable/Status Register */
  223. #define NRDY9 0x0200 /* b9: PIPE9 */
  224. #define NRDY8 0x0100 /* b8: PIPE8 */
  225. #define NRDY7 0x0080 /* b7: PIPE7 */
  226. #define NRDY6 0x0040 /* b6: PIPE6 */
  227. #define NRDY5 0x0020 /* b5: PIPE5 */
  228. #define NRDY4 0x0010 /* b4: PIPE4 */
  229. #define NRDY3 0x0008 /* b3: PIPE3 */
  230. #define NRDY2 0x0004 /* b2: PIPE2 */
  231. #define NRDY1 0x0002 /* b1: PIPE1 */
  232. #define NRDY0 0x0001 /* b1: PIPE0 */
  233. /* BEMP Interrupt Enable/Status Register */
  234. #define BEMP9 0x0200 /* b9: PIPE9 */
  235. #define BEMP8 0x0100 /* b8: PIPE8 */
  236. #define BEMP7 0x0080 /* b7: PIPE7 */
  237. #define BEMP6 0x0040 /* b6: PIPE6 */
  238. #define BEMP5 0x0020 /* b5: PIPE5 */
  239. #define BEMP4 0x0010 /* b4: PIPE4 */
  240. #define BEMP3 0x0008 /* b3: PIPE3 */
  241. #define BEMP2 0x0004 /* b2: PIPE2 */
  242. #define BEMP1 0x0002 /* b1: PIPE1 */
  243. #define BEMP0 0x0001 /* b0: PIPE0 */
  244. /* SOF Pin Configuration Register */
  245. #define TRNENSEL 0x0100 /* b8: Select transaction enable period */
  246. #define BRDYM 0x0040 /* b6: BRDY clear timing */
  247. #define INTL 0x0020 /* b5: Interrupt sense select */
  248. #define EDGESTS 0x0010 /* b4: */
  249. #define SOFMODE 0x000C /* b3-2: SOF pin select */
  250. #define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
  251. #define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
  252. #define SOF_DISABLE 0x0000 /* SOF OUT Disable */
  253. /* Interrupt Status Register 0 */
  254. #define VBINT 0x8000 /* b15: VBUS interrupt */
  255. #define RESM 0x4000 /* b14: Resume interrupt */
  256. #define SOFR 0x2000 /* b13: SOF frame update interrupt */
  257. #define DVST 0x1000 /* b12: Device state transition interrupt */
  258. #define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
  259. #define BEMP 0x0400 /* b10: Buffer empty interrupt */
  260. #define NRDY 0x0200 /* b9: Buffer not ready interrupt */
  261. #define BRDY 0x0100 /* b8: Buffer ready interrupt */
  262. #define VBSTS 0x0080 /* b7: VBUS input port */
  263. #define DVSQ 0x0070 /* b6-4: Device state */
  264. #define DS_SPD_CNFG 0x0070 /* Suspend Configured */
  265. #define DS_SPD_ADDR 0x0060 /* Suspend Address */
  266. #define DS_SPD_DFLT 0x0050 /* Suspend Default */
  267. #define DS_SPD_POWR 0x0040 /* Suspend Powered */
  268. #define DS_SUSP 0x0040 /* Suspend */
  269. #define DS_CNFG 0x0030 /* Configured */
  270. #define DS_ADDS 0x0020 /* Address */
  271. #define DS_DFLT 0x0010 /* Default */
  272. #define DS_POWR 0x0000 /* Powered */
  273. #define DVSQS 0x0030 /* b5-4: Device state */
  274. #define VALID 0x0008 /* b3: Setup packet detected flag */
  275. #define CTSQ 0x0007 /* b2-0: Control transfer stage */
  276. #define CS_SQER 0x0006 /* Sequence error */
  277. #define CS_WRND 0x0005 /* Control write nodata status stage */
  278. #define CS_WRSS 0x0004 /* Control write status stage */
  279. #define CS_WRDS 0x0003 /* Control write data stage */
  280. #define CS_RDSS 0x0002 /* Control read status stage */
  281. #define CS_RDDS 0x0001 /* Control read data stage */
  282. #define CS_IDST 0x0000 /* Idle or setup stage */
  283. /* Interrupt Status Register 1 */
  284. #define OVRCR 0x8000 /* b15: Over-current interrupt */
  285. #define BCHG 0x4000 /* b14: USB bus chenge interrupt */
  286. #define DTCH 0x1000 /* b12: Detach sense interrupt */
  287. #define ATTCH 0x0800 /* b11: Attach sense interrupt */
  288. #define EOFERR 0x0040 /* b6: EOF-error interrupt */
  289. #define SIGN 0x0020 /* b5: Setup ignore interrupt */
  290. #define SACK 0x0010 /* b4: Setup acknowledge interrupt */
  291. /* Frame Number Register */
  292. #define OVRN 0x8000 /* b15: Overrun error */
  293. #define CRCE 0x4000 /* b14: Received data error */
  294. #define FRNM 0x07FF /* b10-0: Frame number */
  295. /* Micro Frame Number Register */
  296. #define UFRNM 0x0007 /* b2-0: Micro frame number */
  297. /* Default Control Pipe Maxpacket Size Register */
  298. /* Pipe Maxpacket Size Register */
  299. #define DEVSEL 0xF000 /* b15-14: Device address select */
  300. #define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
  301. /* Default Control Pipe Control Register */
  302. #define BSTS 0x8000 /* b15: Buffer status */
  303. #define SUREQ 0x4000 /* b14: Send USB request */
  304. #define CSCLR 0x2000 /* b13: complete-split status clear */
  305. #define CSSTS 0x1000 /* b12: complete-split status */
  306. #define SUREQCLR 0x0800 /* b11: stop setup request */
  307. #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
  308. #define SQSET 0x0080 /* b7: Sequence toggle bit set */
  309. #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
  310. #define PBUSY 0x0020 /* b5: pipe busy */
  311. #define PINGE 0x0010 /* b4: ping enable */
  312. #define CCPL 0x0004 /* b2: Enable control transfer complete */
  313. #define PID 0x0003 /* b1-0: Response PID */
  314. #define PID_STALL11 0x0003 /* STALL */
  315. #define PID_STALL 0x0002 /* STALL */
  316. #define PID_BUF 0x0001 /* BUF */
  317. #define PID_NAK 0x0000 /* NAK */
  318. /* Pipe Window Select Register */
  319. #define PIPENM 0x0007 /* b2-0: Pipe select */
  320. /* Pipe Configuration Register */
  321. #define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
  322. #define R8A66597_ISO 0xC000 /* Isochronous */
  323. #define R8A66597_INT 0x8000 /* Interrupt */
  324. #define R8A66597_BULK 0x4000 /* Bulk */
  325. #define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
  326. #define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
  327. #define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
  328. #define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
  329. #define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
  330. #define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
  331. /* Pipe Buffer Configuration Register */
  332. #define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
  333. #define BUFNMB 0x007F /* b6-0: Pipe buffer number */
  334. #define PIPE0BUF 256
  335. #define PIPExBUF 64
  336. /* Pipe Maxpacket Size Register */
  337. #define MXPS 0x07FF /* b10-0: Maxpacket size */
  338. /* Pipe Cycle Configuration Register */
  339. #define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
  340. #define IITV 0x0007 /* b2-0: Isochronous interval */
  341. /* Pipex Control Register */
  342. #define BSTS 0x8000 /* b15: Buffer status */
  343. #define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
  344. #define CSCLR 0x2000 /* b13: complete-split status clear */
  345. #define CSSTS 0x1000 /* b12: complete-split status */
  346. #define ATREPM 0x0400 /* b10: Auto repeat mode */
  347. #define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
  348. #define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
  349. #define SQSET 0x0080 /* b7: Sequence toggle bit set */
  350. #define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
  351. #define PBUSY 0x0020 /* b5: pipe busy */
  352. #define PID 0x0003 /* b1-0: Response PID */
  353. /* PIPExTRE */
  354. #define TRENB 0x0200 /* b9: Transaction counter enable */
  355. #define TRCLR 0x0100 /* b8: Transaction counter clear */
  356. /* PIPExTRN */
  357. #define TRNCNT 0xFFFF /* b15-0: Transaction counter */
  358. /* DEVADDx */
  359. #define UPPHUB 0x7800
  360. #define HUBPORT 0x0700
  361. #define USBSPD 0x00C0
  362. #define RTPORT 0x0001
  363. /* Suspend Mode Register */
  364. #define SUSPM 0x4000 /* b14: Suspend */
  365. #define R8A66597_MAX_NUM_PIPE 10
  366. #define R8A66597_BUF_BSIZE 8
  367. #define R8A66597_MAX_DEVICE 10
  368. #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597)
  369. #define R8A66597_MAX_ROOT_HUB 1
  370. #else
  371. #define R8A66597_MAX_ROOT_HUB 2
  372. #endif
  373. #define R8A66597_MAX_SAMPLING 5
  374. #define R8A66597_RH_POLL_TIME 10
  375. #define BULK_IN_PIPENUM 3
  376. #define BULK_IN_BUFNUM 8
  377. #define BULK_OUT_PIPENUM 4
  378. #define BULK_OUT_BUFNUM 40
  379. #define check_bulk_or_isoc(pipenum) ((pipenum >= 1 && pipenum <= 5))
  380. #define check_interrupt(pipenum) ((pipenum >= 6 && pipenum <= 9))
  381. #define make_devsel(addr) (addr << 12)
  382. struct r8a66597 {
  383. unsigned long reg;
  384. unsigned short pipe_config; /* bit field */
  385. unsigned short port_status;
  386. unsigned short port_change;
  387. u16 speed; /* HSMODE or FSMODE or LSMODE */
  388. unsigned char rh_devnum;
  389. };
  390. static inline u16 r8a66597_read(struct r8a66597 *r8a66597, unsigned long offset)
  391. {
  392. return inw(r8a66597->reg + offset);
  393. }
  394. static inline void r8a66597_read_fifo(struct r8a66597 *r8a66597,
  395. unsigned long offset, void *buf,
  396. int len)
  397. {
  398. int i;
  399. #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
  400. unsigned long fifoaddr = r8a66597->reg + offset;
  401. unsigned long count;
  402. unsigned long *p = buf;
  403. count = len / 4;
  404. for (i = 0; i < count; i++)
  405. p[i] = inl(r8a66597->reg + offset);
  406. if (len & 0x00000003) {
  407. unsigned long tmp = inl(fifoaddr);
  408. memcpy((unsigned char *)buf + count * 4, &tmp, len & 0x03);
  409. }
  410. #else
  411. unsigned short *p = buf;
  412. len = (len + 1) / 2;
  413. for (i = 0; i < len; i++)
  414. p[i] = inw(r8a66597->reg + offset);
  415. #endif
  416. }
  417. static inline void r8a66597_write(struct r8a66597 *r8a66597, u16 val,
  418. unsigned long offset)
  419. {
  420. outw(val, r8a66597->reg + offset);
  421. }
  422. static inline void r8a66597_write_fifo(struct r8a66597 *r8a66597,
  423. unsigned long offset, void *buf,
  424. int len)
  425. {
  426. int i;
  427. unsigned long fifoaddr = r8a66597->reg + offset;
  428. #if defined(CONFIG_SUPERH_ON_CHIP_R8A66597) || defined(CONFIG_RZA_USB)
  429. unsigned long count;
  430. unsigned char *pb;
  431. unsigned long *p = buf;
  432. count = len / 4;
  433. for (i = 0; i < count; i++)
  434. outl(p[i], fifoaddr);
  435. if (len & 0x00000003) {
  436. pb = (unsigned char *)buf + count * 4;
  437. for (i = 0; i < (len & 0x00000003); i++) {
  438. if (r8a66597_read(r8a66597, CFIFOSEL) & BIGEND)
  439. outb(pb[i], fifoaddr + i);
  440. else
  441. outb(pb[i], fifoaddr + 3 - i);
  442. }
  443. }
  444. #else
  445. int odd = len & 0x0001;
  446. unsigned short *p = buf;
  447. len = len / 2;
  448. for (i = 0; i < len; i++)
  449. outw(p[i], fifoaddr);
  450. if (odd) {
  451. unsigned char *pb = (unsigned char *)(buf + len);
  452. outb(*pb, fifoaddr);
  453. }
  454. #endif
  455. }
  456. static inline void r8a66597_mdfy(struct r8a66597 *r8a66597,
  457. u16 val, u16 pat, unsigned long offset)
  458. {
  459. u16 tmp;
  460. tmp = r8a66597_read(r8a66597, offset);
  461. tmp = tmp & (~pat);
  462. tmp = tmp | val;
  463. r8a66597_write(r8a66597, tmp, offset);
  464. }
  465. #define r8a66597_bclr(r8a66597, val, offset) \
  466. r8a66597_mdfy(r8a66597, 0, val, offset)
  467. #define r8a66597_bset(r8a66597, val, offset) \
  468. r8a66597_mdfy(r8a66597, val, 0, offset)
  469. static inline unsigned long get_syscfg_reg(int port)
  470. {
  471. return port == 0 ? SYSCFG0 : SYSCFG1;
  472. }
  473. static inline unsigned long get_syssts_reg(int port)
  474. {
  475. return port == 0 ? SYSSTS0 : SYSSTS1;
  476. }
  477. static inline unsigned long get_dvstctr_reg(int port)
  478. {
  479. return port == 0 ? DVSTCTR0 : DVSTCTR1;
  480. }
  481. static inline unsigned long get_dmacfg_reg(int port)
  482. {
  483. return port == 0 ? DMA0CFG : DMA1CFG;
  484. }
  485. static inline unsigned long get_intenb_reg(int port)
  486. {
  487. return port == 0 ? INTENB1 : INTENB2;
  488. }
  489. static inline unsigned long get_intsts_reg(int port)
  490. {
  491. return port == 0 ? INTSTS1 : INTSTS2;
  492. }
  493. static inline u16 get_rh_usb_speed(struct r8a66597 *r8a66597, int port)
  494. {
  495. unsigned long dvstctr_reg = get_dvstctr_reg(port);
  496. return r8a66597_read(r8a66597, dvstctr_reg) & RHST;
  497. }
  498. static inline void r8a66597_port_power(struct r8a66597 *r8a66597, int port,
  499. int power)
  500. {
  501. unsigned long dvstctr_reg = get_dvstctr_reg(port);
  502. if (power)
  503. r8a66597_bset(r8a66597, VBOUT, dvstctr_reg);
  504. else
  505. r8a66597_bclr(r8a66597, VBOUT, dvstctr_reg);
  506. }
  507. #define get_pipectr_addr(pipenum) (PIPE1CTR + (pipenum - 1) * 2)
  508. #define get_pipetre_addr(pipenum) (PIPE1TRE + (pipenum - 1) * 4)
  509. #define get_pipetrn_addr(pipenum) (PIPE1TRN + (pipenum - 1) * 4)
  510. #define get_devadd_addr(address) (DEVADD0 + address * 2)
  511. /* USB HUB CONSTANTS (not OHCI-specific; see hub.h, based on usb_ohci.h) */
  512. /* destination of request */
  513. #define RH_INTERFACE 0x01
  514. #define RH_ENDPOINT 0x02
  515. #define RH_OTHER 0x03
  516. #define RH_CLASS 0x20
  517. #define RH_VENDOR 0x40
  518. /* Requests: bRequest << 8 | bmRequestType */
  519. #define RH_GET_STATUS 0x0080
  520. #define RH_CLEAR_FEATURE 0x0100
  521. #define RH_SET_FEATURE 0x0300
  522. #define RH_SET_ADDRESS 0x0500
  523. #define RH_GET_DESCRIPTOR 0x0680
  524. #define RH_SET_DESCRIPTOR 0x0700
  525. #define RH_GET_CONFIGURATION 0x0880
  526. #define RH_SET_CONFIGURATION 0x0900
  527. #define RH_GET_STATE 0x0280
  528. #define RH_GET_INTERFACE 0x0A80
  529. #define RH_SET_INTERFACE 0x0B00
  530. #define RH_SYNC_FRAME 0x0C80
  531. /* Our Vendor Specific Request */
  532. #define RH_SET_EP 0x2000
  533. /* Hub port features */
  534. #define RH_PORT_CONNECTION 0x00
  535. #define RH_PORT_ENABLE 0x01
  536. #define RH_PORT_SUSPEND 0x02
  537. #define RH_PORT_OVER_CURRENT 0x03
  538. #define RH_PORT_RESET 0x04
  539. #define RH_PORT_POWER 0x08
  540. #define RH_PORT_LOW_SPEED 0x09
  541. #define RH_C_PORT_CONNECTION 0x10
  542. #define RH_C_PORT_ENABLE 0x11
  543. #define RH_C_PORT_SUSPEND 0x12
  544. #define RH_C_PORT_OVER_CURRENT 0x13
  545. #define RH_C_PORT_RESET 0x14
  546. /* Hub features */
  547. #define RH_C_HUB_LOCAL_POWER 0x00
  548. #define RH_C_HUB_OVER_CURRENT 0x01
  549. #define RH_DEVICE_REMOTE_WAKEUP 0x00
  550. #define RH_ENDPOINT_STALL 0x01
  551. #define RH_ACK 0x01
  552. #define RH_REQ_ERR -1
  553. #define RH_NACK 0x00
  554. /* OHCI ROOT HUB REGISTER MASKS */
  555. /* roothub.portstatus [i] bits */
  556. #define RH_PS_CCS 0x00000001 /* current connect status */
  557. #define RH_PS_PES 0x00000002 /* port enable status*/
  558. #define RH_PS_PSS 0x00000004 /* port suspend status */
  559. #define RH_PS_POCI 0x00000008 /* port over current indicator */
  560. #define RH_PS_PRS 0x00000010 /* port reset status */
  561. #define RH_PS_PPS 0x00000100 /* port power status */
  562. #define RH_PS_LSDA 0x00000200 /* low speed device attached */
  563. #define RH_PS_CSC 0x00010000 /* connect status change */
  564. #define RH_PS_PESC 0x00020000 /* port enable status change */
  565. #define RH_PS_PSSC 0x00040000 /* port suspend status change */
  566. #define RH_PS_OCIC 0x00080000 /* over current indicator change */
  567. #define RH_PS_PRSC 0x00100000 /* port reset status change */
  568. /* roothub.status bits */
  569. #define RH_HS_LPS 0x00000001 /* local power status */
  570. #define RH_HS_OCI 0x00000002 /* over current indicator */
  571. #define RH_HS_DRWE 0x00008000 /* device remote wakeup enable */
  572. #define RH_HS_LPSC 0x00010000 /* local power status change */
  573. #define RH_HS_OCIC 0x00020000 /* over current indicator change */
  574. #define RH_HS_CRWE 0x80000000 /* clear remote wakeup enable */
  575. /* roothub.b masks */
  576. #define RH_B_DR 0x0000ffff /* device removable flags */
  577. #define RH_B_PPCM 0xffff0000 /* port power control mask */
  578. /* roothub.a masks */
  579. #define RH_A_NDP (0xff << 0) /* number of downstream ports */
  580. #define RH_A_PSM (1 << 8) /* power switching mode */
  581. #define RH_A_NPS (1 << 9) /* no power switching */
  582. #define RH_A_DT (1 << 10) /* device type (mbz) */
  583. #define RH_A_OCPM (1 << 11) /* over current protection mode */
  584. #define RH_A_NOCP (1 << 12) /* no over current protection */
  585. #define RH_A_POTPGT (0xff << 24) /* power on to power good time */
  586. #endif /* __R8A66597_H__ */