ehci-rmobile.c 3.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * EHCI HCD (Host Controller Driver) for USB.
  4. *
  5. * Copyright (C) 2013,2014 Renesas Electronics Corporation
  6. * Copyright (C) 2014 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
  7. */
  8. #include <common.h>
  9. #include <asm/io.h>
  10. #include <asm/arch/ehci-rmobile.h>
  11. #include "ehci.h"
  12. #if defined(CONFIG_R8A7740)
  13. static u32 usb_base_address[] = {
  14. 0xC6700000
  15. };
  16. #elif defined(CONFIG_R8A7790)
  17. static u32 usb_base_address[] = {
  18. 0xEE080000, /* USB0 (EHCI) */
  19. 0xEE0A0000, /* USB1 */
  20. 0xEE0C0000, /* USB2 */
  21. };
  22. #elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \
  23. defined(CONFIG_R8A7794)
  24. static u32 usb_base_address[] = {
  25. 0xEE080000, /* USB0 (EHCI) */
  26. 0xEE0C0000, /* USB1 */
  27. };
  28. #else
  29. #error rmobile EHCI USB driver not supported on this platform
  30. #endif
  31. int ehci_hcd_stop(int index)
  32. {
  33. int i;
  34. u32 base;
  35. struct ahbcom_pci_bridge *ahbcom_pci;
  36. base = usb_base_address[index];
  37. ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
  38. writel(0, &ahbcom_pci->ahb_bus_ctr);
  39. /* reset ehci */
  40. setbits_le32(base + EHCI_USBCMD, CMD_RESET);
  41. for (i = 100; i > 0; i--) {
  42. if (!(readl(base + EHCI_USBCMD) & CMD_RESET))
  43. break;
  44. udelay(100);
  45. }
  46. if (!i)
  47. printf("error : ehci(%d) reset failed.\n", index);
  48. if (index == (ARRAY_SIZE(usb_base_address) - 1))
  49. setbits_le32(SMSTPCR7, SMSTPCR703);
  50. return 0;
  51. }
  52. int ehci_hcd_init(int index, enum usb_init_type init,
  53. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  54. {
  55. u32 base;
  56. u32 phys_base;
  57. struct rmobile_ehci_reg *rehci;
  58. struct ahbcom_pci_bridge *ahbcom_pci;
  59. struct ahbconf_pci_bridge *ahbconf_pci;
  60. struct ahb_pciconf *ahb_pciconf_ohci;
  61. struct ahb_pciconf *ahb_pciconf_ehci;
  62. uint32_t cap_base;
  63. base = usb_base_address[index];
  64. phys_base = base;
  65. if (index == 0)
  66. clrbits_le32(SMSTPCR7, SMSTPCR703);
  67. rehci = (struct rmobile_ehci_reg *)(base + EHCI_OFFSET);
  68. ahbcom_pci = (struct ahbcom_pci_bridge *)(base + AHBPCI_OFFSET);
  69. ahbconf_pci =
  70. (struct ahbconf_pci_bridge *)(base + PCI_CONF_AHBPCI_OFFSET);
  71. ahb_pciconf_ohci = (struct ahb_pciconf *)(base + PCI_CONF_OHCI_OFFSET);
  72. ahb_pciconf_ehci = (struct ahb_pciconf *)(base + PCI_CONF_EHCI_OFFSET);
  73. /* Clock & Reset & Direct Power Down */
  74. clrsetbits_le32(&ahbcom_pci->usbctr,
  75. (DIRPD | PCICLK_MASK | USBH_RST), USBCTR_WIN_SIZE_1GB);
  76. clrbits_le32(&ahbcom_pci->usbctr, PLL_RST);
  77. /* AHB-PCI Bridge Communication Registers */
  78. writel(AHB_BUS_CTR_INIT, &ahbcom_pci->ahb_bus_ctr);
  79. writel((CONFIG_SYS_SDRAM_BASE & 0xf0000000) | PCIAHB_WIN_PREFETCH,
  80. &ahbcom_pci->pciahb_win1_ctr);
  81. writel(0xf0000000 | PCIAHB_WIN_PREFETCH,
  82. &ahbcom_pci->pciahb_win2_ctr);
  83. writel(phys_base | PCIWIN2_PCICMD, &ahbcom_pci->ahbpci_win2_ctr);
  84. setbits_le32(&ahbcom_pci->pci_arbiter_ctr,
  85. PCIBP_MODE | PCIREQ1 | PCIREQ0);
  86. /* PCI Configuration Registers for AHBPCI */
  87. writel(PCIWIN1_PCICMD | AHB_CFG_AHBPCI,
  88. &ahbcom_pci->ahbpci_win1_ctr);
  89. writel(phys_base + AHBPCI_OFFSET, &ahbconf_pci->basead);
  90. writel(CONFIG_SYS_SDRAM_BASE & 0xf0000000, &ahbconf_pci->win1_basead);
  91. writel(0xf0000000, &ahbconf_pci->win2_basead);
  92. writel(SERREN | PERREN | MASTEREN | MEMEN,
  93. &ahbconf_pci->cmnd_sts);
  94. /* PCI Configuration Registers for EHCI */
  95. writel(PCIWIN1_PCICMD | AHB_CFG_HOST, &ahbcom_pci->ahbpci_win1_ctr);
  96. writel(phys_base + OHCI_OFFSET, &ahb_pciconf_ohci->basead);
  97. writel(phys_base + EHCI_OFFSET, &ahb_pciconf_ehci->basead);
  98. writel(SERREN | PERREN | MASTEREN | MEMEN,
  99. &ahb_pciconf_ohci->cmnd_sts);
  100. writel(SERREN | PERREN | MASTEREN | MEMEN,
  101. &ahb_pciconf_ehci->cmnd_sts);
  102. /* Enable PCI interrupt */
  103. setbits_le32(&ahbcom_pci->pci_int_enable,
  104. USBH_PMEEN | USBH_INTBEN | USBH_INTAEN);
  105. *hccr = (struct ehci_hccr *)((uint32_t)&rehci->hciversion);
  106. cap_base = ehci_readl(&(*hccr)->cr_capbase);
  107. *hcor = (struct ehci_hcor *)((uint32_t)*hccr + HC_LENGTH(cap_base));
  108. return 0;
  109. }