ehci-omap.c 7.4 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2011 Ilya Yanok, Emcraft Systems
  4. * (C) Copyright 2004-2008
  5. * Texas Instruments, <www.ti.com>
  6. *
  7. * Derived from Beagle Board code by
  8. * Sunil Kumar <sunilsaini05@gmail.com>
  9. * Shashi Ranjan <shashiranjanmca05@gmail.com>
  10. *
  11. */
  12. #include <common.h>
  13. #include <usb.h>
  14. #include <usb/ulpi.h>
  15. #include <errno.h>
  16. #include <asm/io.h>
  17. #include <asm/gpio.h>
  18. #include <asm/arch/ehci.h>
  19. #include <asm/ehci-omap.h>
  20. #include "ehci.h"
  21. static struct omap_uhh *const uhh = (struct omap_uhh *)OMAP_UHH_BASE;
  22. static struct omap_usbtll *const usbtll = (struct omap_usbtll *)OMAP_USBTLL_BASE;
  23. static struct omap_ehci *const ehci = (struct omap_ehci *)OMAP_EHCI_BASE;
  24. static int omap_uhh_reset(void)
  25. {
  26. int timeout = 0;
  27. u32 rev;
  28. rev = readl(&uhh->rev);
  29. /* Soft RESET */
  30. writel(OMAP_UHH_SYSCONFIG_SOFTRESET, &uhh->sysc);
  31. switch (rev) {
  32. case OMAP_USBHS_REV1:
  33. /* Wait for soft RESET to complete */
  34. while (!(readl(&uhh->syss) & 0x1)) {
  35. if (timeout > 100) {
  36. printf("%s: RESET timeout\n", __func__);
  37. return -1;
  38. }
  39. udelay(10);
  40. timeout++;
  41. }
  42. /* Set No-Idle, No-Standby */
  43. writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
  44. break;
  45. default: /* Rev. 2 onwards */
  46. udelay(2); /* Need to wait before accessing SYSCONFIG back */
  47. /* Wait for soft RESET to complete */
  48. while ((readl(&uhh->sysc) & 0x1)) {
  49. if (timeout > 100) {
  50. printf("%s: RESET timeout\n", __func__);
  51. return -1;
  52. }
  53. udelay(10);
  54. timeout++;
  55. }
  56. writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
  57. break;
  58. }
  59. return 0;
  60. }
  61. static int omap_ehci_tll_reset(void)
  62. {
  63. unsigned long init = get_timer(0);
  64. /* perform TLL soft reset, and wait until reset is complete */
  65. writel(OMAP_USBTLL_SYSCONFIG_SOFTRESET, &usbtll->sysc);
  66. /* Wait for TLL reset to complete */
  67. while (!(readl(&usbtll->syss) & OMAP_USBTLL_SYSSTATUS_RESETDONE))
  68. if (get_timer(init) > CONFIG_SYS_HZ) {
  69. debug("OMAP EHCI error: timeout resetting TLL\n");
  70. return -EL3RST;
  71. }
  72. return 0;
  73. }
  74. static void omap_usbhs_hsic_init(int port)
  75. {
  76. unsigned int reg;
  77. /* Enable channels now */
  78. reg = readl(&usbtll->channel_conf + port);
  79. setbits_le32(&reg, (OMAP_TLL_CHANNEL_CONF_CHANMODE_TRANSPARENT_UTMI
  80. | OMAP_TLL_CHANNEL_CONF_ULPINOBITSTUFF
  81. | OMAP_TLL_CHANNEL_CONF_DRVVBUS
  82. | OMAP_TLL_CHANNEL_CONF_CHRGVBUS
  83. | OMAP_TLL_CHANNEL_CONF_CHANEN));
  84. writel(reg, &usbtll->channel_conf + port);
  85. }
  86. #ifdef CONFIG_USB_ULPI
  87. static void omap_ehci_soft_phy_reset(int port)
  88. {
  89. struct ulpi_viewport ulpi_vp;
  90. ulpi_vp.viewport_addr = (u32)&ehci->insreg05_utmi_ulpi;
  91. ulpi_vp.port_num = port;
  92. ulpi_reset(&ulpi_vp);
  93. }
  94. #else
  95. static void omap_ehci_soft_phy_reset(int port)
  96. {
  97. return;
  98. }
  99. #endif
  100. #if defined(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO) || \
  101. defined(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO) || \
  102. defined(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO)
  103. /* controls PHY(s) reset signal(s) */
  104. static inline void omap_ehci_phy_reset(int on, int delay)
  105. {
  106. /*
  107. * Refer ISSUE1:
  108. * Hold the PHY in RESET for enough time till
  109. * PHY is settled and ready
  110. */
  111. if (delay && !on)
  112. udelay(delay);
  113. #ifdef CONFIG_OMAP_EHCI_PHY1_RESET_GPIO
  114. gpio_request(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, "USB PHY1 reset");
  115. gpio_direction_output(CONFIG_OMAP_EHCI_PHY1_RESET_GPIO, !on);
  116. #endif
  117. #ifdef CONFIG_OMAP_EHCI_PHY2_RESET_GPIO
  118. gpio_request(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, "USB PHY2 reset");
  119. gpio_direction_output(CONFIG_OMAP_EHCI_PHY2_RESET_GPIO, !on);
  120. #endif
  121. #ifdef CONFIG_OMAP_EHCI_PHY3_RESET_GPIO
  122. gpio_request(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, "USB PHY3 reset");
  123. gpio_direction_output(CONFIG_OMAP_EHCI_PHY3_RESET_GPIO, !on);
  124. #endif
  125. /* Hold the PHY in RESET for enough time till DIR is high */
  126. /* Refer: ISSUE1 */
  127. if (delay && on)
  128. udelay(delay);
  129. }
  130. #else
  131. #define omap_ehci_phy_reset(on, delay) do {} while (0)
  132. #endif
  133. /* Reset is needed otherwise the kernel-driver will throw an error. */
  134. int omap_ehci_hcd_stop(void)
  135. {
  136. debug("Resetting OMAP EHCI\n");
  137. omap_ehci_phy_reset(1, 0);
  138. if (omap_uhh_reset() < 0)
  139. return -1;
  140. if (omap_ehci_tll_reset() < 0)
  141. return -1;
  142. return 0;
  143. }
  144. /*
  145. * Initialize the OMAP EHCI controller and PHY.
  146. * Based on "drivers/usb/host/ehci-omap.c" from Linux 3.1
  147. * See there for additional Copyrights.
  148. */
  149. int omap_ehci_hcd_init(int index, struct omap_usbhs_board_data *usbhs_pdata,
  150. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  151. {
  152. int ret;
  153. unsigned int i, reg = 0, rev = 0;
  154. debug("Initializing OMAP EHCI\n");
  155. ret = board_usb_init(index, USB_INIT_HOST);
  156. if (ret < 0)
  157. return ret;
  158. /* Put the PHY in RESET */
  159. omap_ehci_phy_reset(1, 10);
  160. ret = omap_uhh_reset();
  161. if (ret < 0)
  162. return ret;
  163. ret = omap_ehci_tll_reset();
  164. if (ret)
  165. return ret;
  166. writel(OMAP_USBTLL_SYSCONFIG_ENAWAKEUP |
  167. OMAP_USBTLL_SYSCONFIG_SIDLEMODE |
  168. OMAP_USBTLL_SYSCONFIG_CACTIVITY, &usbtll->sysc);
  169. /* Put UHH in NoIdle/NoStandby mode */
  170. writel(OMAP_UHH_SYSCONFIG_VAL, &uhh->sysc);
  171. /* setup ULPI bypass and burst configurations */
  172. clrsetbits_le32(&reg, OMAP_UHH_HOSTCONFIG_INCRX_ALIGN_EN,
  173. (OMAP_UHH_HOSTCONFIG_INCR4_BURST_EN |
  174. OMAP_UHH_HOSTCONFIG_INCR8_BURST_EN |
  175. OMAP_UHH_HOSTCONFIG_INCR16_BURST_EN));
  176. rev = readl(&uhh->rev);
  177. if (rev == OMAP_USBHS_REV1) {
  178. if (is_ehci_phy_mode(usbhs_pdata->port_mode[0]))
  179. clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
  180. else
  181. setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P1_BYPASS);
  182. if (is_ehci_phy_mode(usbhs_pdata->port_mode[1]))
  183. clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
  184. else
  185. setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P2_BYPASS);
  186. if (is_ehci_phy_mode(usbhs_pdata->port_mode[2]))
  187. clrbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
  188. else
  189. setbits_le32(&reg, OMAP_UHH_HOSTCONFIG_ULPI_P3_BYPASS);
  190. } else if (rev == OMAP_USBHS_REV2) {
  191. clrsetbits_le32(&reg, (OMAP_P1_MODE_CLEAR | OMAP_P2_MODE_CLEAR),
  192. OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
  193. /* Clear port mode fields for PHY mode */
  194. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
  195. setbits_le32(&reg, OMAP_P1_MODE_HSIC);
  196. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
  197. setbits_le32(&reg, OMAP_P2_MODE_HSIC);
  198. } else if (rev == OMAP_USBHS_REV2_1) {
  199. clrsetbits_le32(&reg,
  200. (OMAP_P1_MODE_CLEAR |
  201. OMAP_P2_MODE_CLEAR |
  202. OMAP_P3_MODE_CLEAR),
  203. OMAP4_UHH_HOSTCONFIG_APP_START_CLK);
  204. /* Clear port mode fields for PHY mode */
  205. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[0]))
  206. setbits_le32(&reg, OMAP_P1_MODE_HSIC);
  207. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[1]))
  208. setbits_le32(&reg, OMAP_P2_MODE_HSIC);
  209. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[2]))
  210. setbits_le32(&reg, OMAP_P3_MODE_HSIC);
  211. }
  212. debug("OMAP UHH_REVISION 0x%x\n", rev);
  213. writel(reg, &uhh->hostconfig);
  214. for (i = 0; i < OMAP_HS_USB_PORTS; i++)
  215. if (is_ehci_hsic_mode(usbhs_pdata->port_mode[i]))
  216. omap_usbhs_hsic_init(i);
  217. omap_ehci_phy_reset(0, 10);
  218. /*
  219. * An undocumented "feature" in the OMAP3 EHCI controller,
  220. * causes suspended ports to be taken out of suspend when
  221. * the USBCMD.Run/Stop bit is cleared (for example when
  222. * we do ehci_bus_suspend).
  223. * This breaks suspend-resume if the root-hub is allowed
  224. * to suspend. Writing 1 to this undocumented register bit
  225. * disables this feature and restores normal behavior.
  226. */
  227. writel(EHCI_INSNREG04_DISABLE_UNSUSPEND, &ehci->insreg04);
  228. for (i = 0; i < OMAP_HS_USB_PORTS; i++)
  229. if (is_ehci_phy_mode(usbhs_pdata->port_mode[i]))
  230. omap_ehci_soft_phy_reset(i);
  231. *hccr = (struct ehci_hccr *)(OMAP_EHCI_BASE);
  232. *hcor = (struct ehci_hcor *)(OMAP_EHCI_BASE + 0x10);
  233. debug("OMAP EHCI init done\n");
  234. return 0;
  235. }