ehci-mxc.c 6.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  4. */
  5. #include <common.h>
  6. #include <usb.h>
  7. #include <asm/io.h>
  8. #include <asm/arch/imx-regs.h>
  9. #include <usb/ehci-ci.h>
  10. #include <errno.h>
  11. #include "ehci.h"
  12. #define USBCTRL_OTGBASE_OFFSET 0x600
  13. #define MX25_OTG_SIC_SHIFT 29
  14. #define MX25_OTG_SIC_MASK (0x3 << MX25_OTG_SIC_SHIFT)
  15. #define MX25_OTG_PM_BIT (1 << 24)
  16. #define MX25_OTG_PP_BIT (1 << 11)
  17. #define MX25_OTG_OCPOL_BIT (1 << 3)
  18. #define MX25_H1_SIC_SHIFT 21
  19. #define MX25_H1_SIC_MASK (0x3 << MX25_H1_SIC_SHIFT)
  20. #define MX25_H1_PP_BIT (1 << 18)
  21. #define MX25_H1_PM_BIT (1 << 16)
  22. #define MX25_H1_IPPUE_UP_BIT (1 << 7)
  23. #define MX25_H1_IPPUE_DOWN_BIT (1 << 6)
  24. #define MX25_H1_TLL_BIT (1 << 5)
  25. #define MX25_H1_USBTE_BIT (1 << 4)
  26. #define MX25_H1_OCPOL_BIT (1 << 2)
  27. #define MX31_OTG_SIC_SHIFT 29
  28. #define MX31_OTG_SIC_MASK (0x3 << MX31_OTG_SIC_SHIFT)
  29. #define MX31_OTG_PM_BIT (1 << 24)
  30. #define MX31_H2_SIC_SHIFT 21
  31. #define MX31_H2_SIC_MASK (0x3 << MX31_H2_SIC_SHIFT)
  32. #define MX31_H2_PM_BIT (1 << 16)
  33. #define MX31_H2_DT_BIT (1 << 5)
  34. #define MX31_H1_SIC_SHIFT 13
  35. #define MX31_H1_SIC_MASK (0x3 << MX31_H1_SIC_SHIFT)
  36. #define MX31_H1_PM_BIT (1 << 8)
  37. #define MX31_H1_DT_BIT (1 << 4)
  38. #define MX35_OTG_SIC_SHIFT 29
  39. #define MX35_OTG_SIC_MASK (0x3 << MX35_OTG_SIC_SHIFT)
  40. #define MX35_OTG_PM_BIT (1 << 24)
  41. #define MX35_OTG_PP_BIT (1 << 11)
  42. #define MX35_OTG_OCPOL_BIT (1 << 3)
  43. #define MX35_H1_SIC_SHIFT 21
  44. #define MX35_H1_SIC_MASK (0x3 << MX35_H1_SIC_SHIFT)
  45. #define MX35_H1_PP_BIT (1 << 18)
  46. #define MX35_H1_PM_BIT (1 << 16)
  47. #define MX35_H1_IPPUE_UP_BIT (1 << 7)
  48. #define MX35_H1_IPPUE_DOWN_BIT (1 << 6)
  49. #define MX35_H1_TLL_BIT (1 << 5)
  50. #define MX35_H1_USBTE_BIT (1 << 4)
  51. #define MX35_H1_OCPOL_BIT (1 << 2)
  52. static int mxc_set_usbcontrol(int port, unsigned int flags)
  53. {
  54. unsigned int v;
  55. v = readl(IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
  56. #if defined(CONFIG_MX25)
  57. switch (port) {
  58. case 0: /* OTG port */
  59. v &= ~(MX25_OTG_SIC_MASK | MX25_OTG_PM_BIT | MX25_OTG_PP_BIT |
  60. MX25_OTG_OCPOL_BIT);
  61. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_OTG_SIC_SHIFT;
  62. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  63. v |= MX25_OTG_PM_BIT;
  64. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  65. v |= MX25_OTG_PP_BIT;
  66. if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  67. v |= MX25_OTG_OCPOL_BIT;
  68. break;
  69. case 1: /* H1 port */
  70. v &= ~(MX25_H1_SIC_MASK | MX25_H1_PM_BIT | MX25_H1_PP_BIT |
  71. MX25_H1_OCPOL_BIT | MX25_H1_TLL_BIT |
  72. MX25_H1_USBTE_BIT | MX25_H1_IPPUE_DOWN_BIT |
  73. MX25_H1_IPPUE_UP_BIT);
  74. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX25_H1_SIC_SHIFT;
  75. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  76. v |= MX25_H1_PM_BIT;
  77. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  78. v |= MX25_H1_PP_BIT;
  79. if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  80. v |= MX25_H1_OCPOL_BIT;
  81. if (!(flags & MXC_EHCI_TTL_ENABLED))
  82. v |= MX25_H1_TLL_BIT;
  83. if (flags & MXC_EHCI_INTERNAL_PHY)
  84. v |= MX25_H1_USBTE_BIT;
  85. if (flags & MXC_EHCI_IPPUE_DOWN)
  86. v |= MX25_H1_IPPUE_DOWN_BIT;
  87. if (flags & MXC_EHCI_IPPUE_UP)
  88. v |= MX25_H1_IPPUE_UP_BIT;
  89. break;
  90. default:
  91. return -EINVAL;
  92. }
  93. #elif defined(CONFIG_MX31)
  94. switch (port) {
  95. case 0: /* OTG port */
  96. v &= ~(MX31_OTG_SIC_MASK | MX31_OTG_PM_BIT);
  97. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_OTG_SIC_SHIFT;
  98. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  99. v |= MX31_OTG_PM_BIT;
  100. break;
  101. case 1: /* H1 port */
  102. v &= ~(MX31_H1_SIC_MASK | MX31_H1_PM_BIT | MX31_H1_DT_BIT);
  103. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H1_SIC_SHIFT;
  104. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  105. v |= MX31_H1_PM_BIT;
  106. if (!(flags & MXC_EHCI_TTL_ENABLED))
  107. v |= MX31_H1_DT_BIT;
  108. break;
  109. case 2: /* H2 port */
  110. v &= ~(MX31_H2_SIC_MASK | MX31_H2_PM_BIT | MX31_H2_DT_BIT);
  111. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX31_H2_SIC_SHIFT;
  112. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  113. v |= MX31_H2_PM_BIT;
  114. if (!(flags & MXC_EHCI_TTL_ENABLED))
  115. v |= MX31_H2_DT_BIT;
  116. break;
  117. default:
  118. return -EINVAL;
  119. }
  120. #elif defined(CONFIG_MX35)
  121. switch (port) {
  122. case 0: /* OTG port */
  123. v &= ~(MX35_OTG_SIC_MASK | MX35_OTG_PM_BIT | MX35_OTG_PP_BIT |
  124. MX35_OTG_OCPOL_BIT);
  125. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_OTG_SIC_SHIFT;
  126. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  127. v |= MX35_OTG_PM_BIT;
  128. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  129. v |= MX35_OTG_PP_BIT;
  130. if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  131. v |= MX35_OTG_OCPOL_BIT;
  132. break;
  133. case 1: /* H1 port */
  134. v &= ~(MX35_H1_SIC_MASK | MX35_H1_PM_BIT | MX35_H1_PP_BIT |
  135. MX35_H1_OCPOL_BIT | MX35_H1_TLL_BIT |
  136. MX35_H1_USBTE_BIT | MX35_H1_IPPUE_DOWN_BIT |
  137. MX35_H1_IPPUE_UP_BIT);
  138. v |= (flags & MXC_EHCI_INTERFACE_MASK) << MX35_H1_SIC_SHIFT;
  139. if (!(flags & MXC_EHCI_POWER_PINS_ENABLED))
  140. v |= MX35_H1_PM_BIT;
  141. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  142. v |= MX35_H1_PP_BIT;
  143. if (!(flags & MXC_EHCI_OC_PIN_ACTIVE_LOW))
  144. v |= MX35_H1_OCPOL_BIT;
  145. if (!(flags & MXC_EHCI_TTL_ENABLED))
  146. v |= MX35_H1_TLL_BIT;
  147. if (flags & MXC_EHCI_INTERNAL_PHY)
  148. v |= MX35_H1_USBTE_BIT;
  149. if (flags & MXC_EHCI_IPPUE_DOWN)
  150. v |= MX35_H1_IPPUE_DOWN_BIT;
  151. if (flags & MXC_EHCI_IPPUE_UP)
  152. v |= MX35_H1_IPPUE_UP_BIT;
  153. break;
  154. default:
  155. return -EINVAL;
  156. }
  157. #else
  158. #error MXC EHCI USB driver not supported on this platform
  159. #endif
  160. writel(v, IMX_USB_BASE + USBCTRL_OTGBASE_OFFSET);
  161. return 0;
  162. }
  163. int ehci_hcd_init(int index, enum usb_init_type init,
  164. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  165. {
  166. struct usb_ehci *ehci;
  167. #ifdef CONFIG_MX31
  168. struct clock_control_regs *sc_regs =
  169. (struct clock_control_regs *)CCM_BASE;
  170. __raw_readl(&sc_regs->ccmr);
  171. __raw_writel(__raw_readl(&sc_regs->ccmr) | (1 << 9), &sc_regs->ccmr) ;
  172. #endif
  173. udelay(80);
  174. ehci = (struct usb_ehci *)(IMX_USB_BASE +
  175. IMX_USB_PORT_OFFSET * CONFIG_MXC_USB_PORT);
  176. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  177. *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
  178. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  179. setbits_le32(&ehci->usbmode, CM_HOST);
  180. __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  181. mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
  182. #ifdef CONFIG_MX35
  183. /* Workaround for ENGcm11601 */
  184. __raw_writel(0, &ehci->sbuscfg);
  185. #endif
  186. udelay(10000);
  187. return 0;
  188. }
  189. /*
  190. * Destroy the appropriate control structures corresponding
  191. * the the EHCI host controller.
  192. */
  193. int ehci_hcd_stop(int index)
  194. {
  195. return 0;
  196. }