ehci-mx6.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  4. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <usb.h>
  8. #include <errno.h>
  9. #include <wait_bit.h>
  10. #include <linux/compiler.h>
  11. #include <usb/ehci-ci.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/imx-regs.h>
  14. #include <asm/arch/clock.h>
  15. #include <asm/mach-imx/iomux-v3.h>
  16. #include <asm/mach-imx/sys_proto.h>
  17. #include <dm.h>
  18. #include <asm/mach-types.h>
  19. #include <power/regulator.h>
  20. #include "ehci.h"
  21. DECLARE_GLOBAL_DATA_PTR;
  22. #define USB_OTGREGS_OFFSET 0x000
  23. #define USB_H1REGS_OFFSET 0x200
  24. #define USB_H2REGS_OFFSET 0x400
  25. #define USB_H3REGS_OFFSET 0x600
  26. #define USB_OTHERREGS_OFFSET 0x800
  27. #define USB_H1_CTRL_OFFSET 0x04
  28. #define USBPHY_CTRL 0x00000030
  29. #define USBPHY_CTRL_SET 0x00000034
  30. #define USBPHY_CTRL_CLR 0x00000038
  31. #define USBPHY_CTRL_TOG 0x0000003c
  32. #define USBPHY_PWD 0x00000000
  33. #define USBPHY_CTRL_SFTRST 0x80000000
  34. #define USBPHY_CTRL_CLKGATE 0x40000000
  35. #define USBPHY_CTRL_ENUTMILEVEL3 0x00008000
  36. #define USBPHY_CTRL_ENUTMILEVEL2 0x00004000
  37. #define USBPHY_CTRL_OTG_ID 0x08000000
  38. #define ANADIG_USB2_CHRG_DETECT_EN_B 0x00100000
  39. #define ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B 0x00080000
  40. #define ANADIG_USB2_PLL_480_CTRL_BYPASS 0x00010000
  41. #define ANADIG_USB2_PLL_480_CTRL_ENABLE 0x00002000
  42. #define ANADIG_USB2_PLL_480_CTRL_POWER 0x00001000
  43. #define ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS 0x00000040
  44. #define USBNC_OFFSET 0x200
  45. #define USBNC_PHY_STATUS_OFFSET 0x23C
  46. #define USBNC_PHYSTATUS_ID_DIG (1 << 4) /* otg_id status */
  47. #define USBNC_PHYCFG2_ACAENB (1 << 4) /* otg_id detection enable */
  48. #define UCTRL_PWR_POL (1 << 9) /* OTG Polarity of Power Pin */
  49. #define UCTRL_OVER_CUR_POL (1 << 8) /* OTG Polarity of Overcurrent */
  50. #define UCTRL_OVER_CUR_DIS (1 << 7) /* Disable OTG Overcurrent Detection */
  51. /* USBCMD */
  52. #define UCMD_RUN_STOP (1 << 0) /* controller run/stop */
  53. #define UCMD_RESET (1 << 1) /* controller reset */
  54. #if defined(CONFIG_MX6)
  55. static const unsigned phy_bases[] = {
  56. USB_PHY0_BASE_ADDR,
  57. USB_PHY1_BASE_ADDR,
  58. };
  59. static void usb_internal_phy_clock_gate(int index, int on)
  60. {
  61. void __iomem *phy_reg;
  62. if (index >= ARRAY_SIZE(phy_bases))
  63. return;
  64. phy_reg = (void __iomem *)phy_bases[index];
  65. phy_reg += on ? USBPHY_CTRL_CLR : USBPHY_CTRL_SET;
  66. writel(USBPHY_CTRL_CLKGATE, phy_reg);
  67. }
  68. static void usb_power_config(int index)
  69. {
  70. struct anatop_regs __iomem *anatop =
  71. (struct anatop_regs __iomem *)ANATOP_BASE_ADDR;
  72. void __iomem *chrg_detect;
  73. void __iomem *pll_480_ctrl_clr;
  74. void __iomem *pll_480_ctrl_set;
  75. switch (index) {
  76. case 0:
  77. chrg_detect = &anatop->usb1_chrg_detect;
  78. pll_480_ctrl_clr = &anatop->usb1_pll_480_ctrl_clr;
  79. pll_480_ctrl_set = &anatop->usb1_pll_480_ctrl_set;
  80. break;
  81. case 1:
  82. chrg_detect = &anatop->usb2_chrg_detect;
  83. pll_480_ctrl_clr = &anatop->usb2_pll_480_ctrl_clr;
  84. pll_480_ctrl_set = &anatop->usb2_pll_480_ctrl_set;
  85. break;
  86. default:
  87. return;
  88. }
  89. /*
  90. * Some phy and power's special controls
  91. * 1. The external charger detector needs to be disabled
  92. * or the signal at DP will be poor
  93. * 2. The PLL's power and output to usb
  94. * is totally controlled by IC, so the Software only needs
  95. * to enable them at initializtion.
  96. */
  97. writel(ANADIG_USB2_CHRG_DETECT_EN_B |
  98. ANADIG_USB2_CHRG_DETECT_CHK_CHRG_B,
  99. chrg_detect);
  100. writel(ANADIG_USB2_PLL_480_CTRL_BYPASS,
  101. pll_480_ctrl_clr);
  102. writel(ANADIG_USB2_PLL_480_CTRL_ENABLE |
  103. ANADIG_USB2_PLL_480_CTRL_POWER |
  104. ANADIG_USB2_PLL_480_CTRL_EN_USB_CLKS,
  105. pll_480_ctrl_set);
  106. }
  107. /* Return 0 : host node, <>0 : device mode */
  108. static int usb_phy_enable(int index, struct usb_ehci *ehci)
  109. {
  110. void __iomem *phy_reg;
  111. void __iomem *phy_ctrl;
  112. void __iomem *usb_cmd;
  113. int ret;
  114. if (index >= ARRAY_SIZE(phy_bases))
  115. return 0;
  116. phy_reg = (void __iomem *)phy_bases[index];
  117. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  118. usb_cmd = (void __iomem *)&ehci->usbcmd;
  119. /* Stop then Reset */
  120. clrbits_le32(usb_cmd, UCMD_RUN_STOP);
  121. ret = wait_for_bit_le32(usb_cmd, UCMD_RUN_STOP, false, 10000, false);
  122. if (ret)
  123. return ret;
  124. setbits_le32(usb_cmd, UCMD_RESET);
  125. ret = wait_for_bit_le32(usb_cmd, UCMD_RESET, false, 10000, false);
  126. if (ret)
  127. return ret;
  128. /* Reset USBPHY module */
  129. setbits_le32(phy_ctrl, USBPHY_CTRL_SFTRST);
  130. udelay(10);
  131. /* Remove CLKGATE and SFTRST */
  132. clrbits_le32(phy_ctrl, USBPHY_CTRL_CLKGATE | USBPHY_CTRL_SFTRST);
  133. udelay(10);
  134. /* Power up the PHY */
  135. writel(0, phy_reg + USBPHY_PWD);
  136. /* enable FS/LS device */
  137. setbits_le32(phy_ctrl, USBPHY_CTRL_ENUTMILEVEL2 |
  138. USBPHY_CTRL_ENUTMILEVEL3);
  139. return 0;
  140. }
  141. int usb_phy_mode(int port)
  142. {
  143. void __iomem *phy_reg;
  144. void __iomem *phy_ctrl;
  145. u32 val;
  146. phy_reg = (void __iomem *)phy_bases[port];
  147. phy_ctrl = (void __iomem *)(phy_reg + USBPHY_CTRL);
  148. val = readl(phy_ctrl);
  149. if (val & USBPHY_CTRL_OTG_ID)
  150. return USB_INIT_DEVICE;
  151. else
  152. return USB_INIT_HOST;
  153. }
  154. /* Base address for this IP block is 0x02184800 */
  155. struct usbnc_regs {
  156. u32 ctrl[4]; /* otg/host1-3 */
  157. u32 uh2_hsic_ctrl;
  158. u32 uh3_hsic_ctrl;
  159. u32 otg_phy_ctrl_0;
  160. u32 uh1_phy_ctrl_0;
  161. };
  162. #elif defined(CONFIG_MX7)
  163. struct usbnc_regs {
  164. u32 ctrl1;
  165. u32 ctrl2;
  166. u32 reserve1[10];
  167. u32 phy_cfg1;
  168. u32 phy_cfg2;
  169. u32 reserve2;
  170. u32 phy_status;
  171. u32 reserve3[4];
  172. u32 adp_cfg1;
  173. u32 adp_cfg2;
  174. u32 adp_status;
  175. };
  176. static void usb_power_config(int index)
  177. {
  178. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  179. (0x10000 * index) + USBNC_OFFSET);
  180. void __iomem *phy_cfg2 = (void __iomem *)(&usbnc->phy_cfg2);
  181. void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
  182. /*
  183. * Clear the ACAENB to enable usb_otg_id detection,
  184. * otherwise it is the ACA detection enabled.
  185. */
  186. clrbits_le32(phy_cfg2, USBNC_PHYCFG2_ACAENB);
  187. /* Set power polarity to high active */
  188. #ifdef CONFIG_MXC_USB_OTG_HACTIVE
  189. setbits_le32(ctrl, UCTRL_PWR_POL);
  190. #else
  191. clrbits_le32(ctrl, UCTRL_PWR_POL);
  192. #endif
  193. }
  194. int usb_phy_mode(int port)
  195. {
  196. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  197. (0x10000 * port) + USBNC_OFFSET);
  198. void __iomem *status = (void __iomem *)(&usbnc->phy_status);
  199. u32 val;
  200. val = readl(status);
  201. if (val & USBNC_PHYSTATUS_ID_DIG)
  202. return USB_INIT_DEVICE;
  203. else
  204. return USB_INIT_HOST;
  205. }
  206. #endif
  207. static void usb_oc_config(int index)
  208. {
  209. #if defined(CONFIG_MX6)
  210. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  211. USB_OTHERREGS_OFFSET);
  212. void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl[index]);
  213. #elif defined(CONFIG_MX7)
  214. struct usbnc_regs *usbnc = (struct usbnc_regs *)(USB_BASE_ADDR +
  215. (0x10000 * index) + USBNC_OFFSET);
  216. void __iomem *ctrl = (void __iomem *)(&usbnc->ctrl1);
  217. #endif
  218. #if CONFIG_MACH_TYPE == MACH_TYPE_MX6Q_ARM2
  219. /* mx6qarm2 seems to required a different setting*/
  220. clrbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  221. #else
  222. setbits_le32(ctrl, UCTRL_OVER_CUR_POL);
  223. #endif
  224. setbits_le32(ctrl, UCTRL_OVER_CUR_DIS);
  225. }
  226. /**
  227. * board_usb_phy_mode - override usb phy mode
  228. * @port: usb host/otg port
  229. *
  230. * Target board specific, override usb_phy_mode.
  231. * When usb-otg is used as usb host port, iomux pad usb_otg_id can be
  232. * left disconnected in this case usb_phy_mode will not be able to identify
  233. * the phy mode that usb port is used.
  234. * Machine file overrides board_usb_phy_mode.
  235. *
  236. * Return: USB_INIT_DEVICE or USB_INIT_HOST
  237. */
  238. int __weak board_usb_phy_mode(int port)
  239. {
  240. return usb_phy_mode(port);
  241. }
  242. /**
  243. * board_ehci_hcd_init - set usb vbus voltage
  244. * @port: usb otg port
  245. *
  246. * Target board specific, setup iomux pad to setup supply vbus voltage
  247. * for usb otg port. Machine board file overrides board_ehci_hcd_init
  248. *
  249. * Return: 0 Success
  250. */
  251. int __weak board_ehci_hcd_init(int port)
  252. {
  253. return 0;
  254. }
  255. /**
  256. * board_ehci_power - enables/disables usb vbus voltage
  257. * @port: usb otg port
  258. * @on: on/off vbus voltage
  259. *
  260. * Enables/disables supply vbus voltage for usb otg port.
  261. * Machine board file overrides board_ehci_power
  262. *
  263. * Return: 0 Success
  264. */
  265. int __weak board_ehci_power(int port, int on)
  266. {
  267. return 0;
  268. }
  269. int ehci_mx6_common_init(struct usb_ehci *ehci, int index)
  270. {
  271. int ret;
  272. enable_usboh3_clk(1);
  273. mdelay(1);
  274. /* Do board specific initialization */
  275. ret = board_ehci_hcd_init(index);
  276. if (ret)
  277. return ret;
  278. usb_power_config(index);
  279. usb_oc_config(index);
  280. #if defined(CONFIG_MX6)
  281. usb_internal_phy_clock_gate(index, 1);
  282. usb_phy_enable(index, ehci);
  283. #endif
  284. return 0;
  285. }
  286. #ifndef CONFIG_DM_USB
  287. int ehci_hcd_init(int index, enum usb_init_type init,
  288. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  289. {
  290. enum usb_init_type type;
  291. #if defined(CONFIG_MX6)
  292. u32 controller_spacing = 0x200;
  293. #elif defined(CONFIG_MX7)
  294. u32 controller_spacing = 0x10000;
  295. #endif
  296. struct usb_ehci *ehci = (struct usb_ehci *)(USB_BASE_ADDR +
  297. (controller_spacing * index));
  298. int ret;
  299. if (index > 3)
  300. return -EINVAL;
  301. ret = ehci_mx6_common_init(ehci, index);
  302. if (ret)
  303. return ret;
  304. type = board_usb_phy_mode(index);
  305. if (hccr && hcor) {
  306. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  307. *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
  308. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  309. }
  310. if ((type == init) || (type == USB_INIT_DEVICE))
  311. board_ehci_power(index, (type == USB_INIT_DEVICE) ? 0 : 1);
  312. if (type != init)
  313. return -ENODEV;
  314. if (type == USB_INIT_DEVICE)
  315. return 0;
  316. setbits_le32(&ehci->usbmode, CM_HOST);
  317. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  318. setbits_le32(&ehci->portsc, USB_EN);
  319. mdelay(10);
  320. return 0;
  321. }
  322. int ehci_hcd_stop(int index)
  323. {
  324. return 0;
  325. }
  326. #else
  327. struct ehci_mx6_priv_data {
  328. struct ehci_ctrl ctrl;
  329. struct usb_ehci *ehci;
  330. struct udevice *vbus_supply;
  331. enum usb_init_type init_type;
  332. int portnr;
  333. };
  334. static int mx6_init_after_reset(struct ehci_ctrl *dev)
  335. {
  336. struct ehci_mx6_priv_data *priv = dev->priv;
  337. enum usb_init_type type = priv->init_type;
  338. struct usb_ehci *ehci = priv->ehci;
  339. int ret;
  340. ret = ehci_mx6_common_init(priv->ehci, priv->portnr);
  341. if (ret)
  342. return ret;
  343. if (priv->vbus_supply) {
  344. ret = regulator_set_enable(priv->vbus_supply,
  345. (type == USB_INIT_DEVICE) ?
  346. false : true);
  347. if (ret) {
  348. puts("Error enabling VBUS supply\n");
  349. return ret;
  350. }
  351. }
  352. if (type == USB_INIT_DEVICE)
  353. return 0;
  354. setbits_le32(&ehci->usbmode, CM_HOST);
  355. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  356. setbits_le32(&ehci->portsc, USB_EN);
  357. mdelay(10);
  358. return 0;
  359. }
  360. static const struct ehci_ops mx6_ehci_ops = {
  361. .init_after_reset = mx6_init_after_reset
  362. };
  363. static int ehci_usb_phy_mode(struct udevice *dev)
  364. {
  365. struct usb_platdata *plat = dev_get_platdata(dev);
  366. void *__iomem addr = (void *__iomem)devfdt_get_addr(dev);
  367. void *__iomem phy_ctrl, *__iomem phy_status;
  368. const void *blob = gd->fdt_blob;
  369. int offset = dev_of_offset(dev), phy_off;
  370. u32 val;
  371. /*
  372. * About fsl,usbphy, Refer to
  373. * Documentation/devicetree/bindings/usb/ci-hdrc-usb2.txt.
  374. */
  375. if (is_mx6()) {
  376. phy_off = fdtdec_lookup_phandle(blob,
  377. offset,
  378. "fsl,usbphy");
  379. if (phy_off < 0)
  380. return -EINVAL;
  381. addr = (void __iomem *)fdtdec_get_addr(blob, phy_off,
  382. "reg");
  383. if ((fdt_addr_t)addr == FDT_ADDR_T_NONE)
  384. return -EINVAL;
  385. phy_ctrl = (void __iomem *)(addr + USBPHY_CTRL);
  386. val = readl(phy_ctrl);
  387. if (val & USBPHY_CTRL_OTG_ID)
  388. plat->init_type = USB_INIT_DEVICE;
  389. else
  390. plat->init_type = USB_INIT_HOST;
  391. } else if (is_mx7()) {
  392. phy_status = (void __iomem *)(addr +
  393. USBNC_PHY_STATUS_OFFSET);
  394. val = readl(phy_status);
  395. if (val & USBNC_PHYSTATUS_ID_DIG)
  396. plat->init_type = USB_INIT_DEVICE;
  397. else
  398. plat->init_type = USB_INIT_HOST;
  399. } else {
  400. return -EINVAL;
  401. }
  402. return 0;
  403. }
  404. static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
  405. {
  406. struct usb_platdata *plat = dev_get_platdata(dev);
  407. const char *mode;
  408. mode = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "dr_mode", NULL);
  409. if (mode) {
  410. if (strcmp(mode, "peripheral") == 0)
  411. plat->init_type = USB_INIT_DEVICE;
  412. else if (strcmp(mode, "host") == 0)
  413. plat->init_type = USB_INIT_HOST;
  414. else if (strcmp(mode, "otg") == 0)
  415. return ehci_usb_phy_mode(dev);
  416. else
  417. return -EINVAL;
  418. return 0;
  419. }
  420. return ehci_usb_phy_mode(dev);
  421. }
  422. static int ehci_usb_probe(struct udevice *dev)
  423. {
  424. struct usb_platdata *plat = dev_get_platdata(dev);
  425. struct usb_ehci *ehci = (struct usb_ehci *)devfdt_get_addr(dev);
  426. struct ehci_mx6_priv_data *priv = dev_get_priv(dev);
  427. enum usb_init_type type = plat->init_type;
  428. struct ehci_hccr *hccr;
  429. struct ehci_hcor *hcor;
  430. int ret;
  431. priv->ehci = ehci;
  432. priv->portnr = dev->seq;
  433. priv->init_type = type;
  434. ret = device_get_supply_regulator(dev, "vbus-supply",
  435. &priv->vbus_supply);
  436. if (ret)
  437. debug("%s: No vbus supply\n", dev->name);
  438. ret = ehci_mx6_common_init(ehci, priv->portnr);
  439. if (ret)
  440. return ret;
  441. if (priv->vbus_supply) {
  442. ret = regulator_set_enable(priv->vbus_supply,
  443. (type == USB_INIT_DEVICE) ?
  444. false : true);
  445. if (ret) {
  446. puts("Error enabling VBUS supply\n");
  447. return ret;
  448. }
  449. }
  450. if (priv->init_type == USB_INIT_HOST) {
  451. setbits_le32(&ehci->usbmode, CM_HOST);
  452. writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  453. setbits_le32(&ehci->portsc, USB_EN);
  454. }
  455. mdelay(10);
  456. hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  457. hcor = (struct ehci_hcor *)((uint32_t)hccr +
  458. HC_LENGTH(ehci_readl(&(hccr)->cr_capbase)));
  459. return ehci_register(dev, hccr, hcor, &mx6_ehci_ops, 0, priv->init_type);
  460. }
  461. static const struct udevice_id mx6_usb_ids[] = {
  462. { .compatible = "fsl,imx27-usb" },
  463. { }
  464. };
  465. U_BOOT_DRIVER(usb_mx6) = {
  466. .name = "ehci_mx6",
  467. .id = UCLASS_USB,
  468. .of_match = mx6_usb_ids,
  469. .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
  470. .probe = ehci_usb_probe,
  471. .remove = ehci_deregister,
  472. .ops = &ehci_usb_ops,
  473. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  474. .priv_auto_alloc_size = sizeof(struct ehci_mx6_priv_data),
  475. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  476. };
  477. #endif