ehci-mx5.c 7.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2009 Daniel Mack <daniel@caiaq.de>
  4. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  5. */
  6. #include <common.h>
  7. #include <usb.h>
  8. #include <errno.h>
  9. #include <linux/compiler.h>
  10. #include <usb/ehci-ci.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include "ehci.h"
  15. #define MX5_USBOTHER_REGS_OFFSET 0x800
  16. #define MXC_OTG_OFFSET 0
  17. #define MXC_H1_OFFSET 0x200
  18. #define MXC_H2_OFFSET 0x400
  19. #define MXC_H3_OFFSET 0x600
  20. #define MXC_USBCTRL_OFFSET 0
  21. #define MXC_USB_PHY_CTR_FUNC_OFFSET 0x8
  22. #define MXC_USB_PHY_CTR_FUNC2_OFFSET 0xc
  23. #define MXC_USB_CTRL_1_OFFSET 0x10
  24. #define MXC_USBH2CTRL_OFFSET 0x14
  25. #define MXC_USBH3CTRL_OFFSET 0x18
  26. /* USB_CTRL */
  27. /* OTG wakeup intr enable */
  28. #define MXC_OTG_UCTRL_OWIE_BIT (1 << 27)
  29. /* OTG power mask */
  30. #define MXC_OTG_UCTRL_OPM_BIT (1 << 24)
  31. /* OTG power pin polarity */
  32. #define MXC_OTG_UCTRL_O_PWR_POL_BIT (1 << 24)
  33. /* Host1 ULPI interrupt enable */
  34. #define MXC_H1_UCTRL_H1UIE_BIT (1 << 12)
  35. /* HOST1 wakeup intr enable */
  36. #define MXC_H1_UCTRL_H1WIE_BIT (1 << 11)
  37. /* HOST1 power mask */
  38. #define MXC_H1_UCTRL_H1PM_BIT (1 << 8)
  39. /* HOST1 power pin polarity */
  40. #define MXC_H1_UCTRL_H1_PWR_POL_BIT (1 << 8)
  41. /* USB_PHY_CTRL_FUNC */
  42. /* OTG Polarity of Overcurrent */
  43. #define MXC_OTG_PHYCTRL_OC_POL_BIT (1 << 9)
  44. /* OTG Disable Overcurrent Event */
  45. #define MXC_OTG_PHYCTRL_OC_DIS_BIT (1 << 8)
  46. /* UH1 Polarity of Overcurrent */
  47. #define MXC_H1_OC_POL_BIT (1 << 6)
  48. /* UH1 Disable Overcurrent Event */
  49. #define MXC_H1_OC_DIS_BIT (1 << 5)
  50. /* OTG Power Pin Polarity */
  51. #define MXC_OTG_PHYCTRL_PWR_POL_BIT (1 << 3)
  52. /* USBH2CTRL */
  53. #define MXC_H2_UCTRL_H2_OC_POL_BIT (1 << 31)
  54. #define MXC_H2_UCTRL_H2_OC_DIS_BIT (1 << 30)
  55. #define MXC_H2_UCTRL_H2UIE_BIT (1 << 8)
  56. #define MXC_H2_UCTRL_H2WIE_BIT (1 << 7)
  57. #define MXC_H2_UCTRL_H2PM_BIT (1 << 4)
  58. #define MXC_H2_UCTRL_H2_PWR_POL_BIT (1 << 4)
  59. /* USBH3CTRL */
  60. #define MXC_H3_UCTRL_H3_OC_POL_BIT (1 << 31)
  61. #define MXC_H3_UCTRL_H3_OC_DIS_BIT (1 << 30)
  62. #define MXC_H3_UCTRL_H3UIE_BIT (1 << 8)
  63. #define MXC_H3_UCTRL_H3WIE_BIT (1 << 7)
  64. #define MXC_H3_UCTRL_H3_PWR_POL_BIT (1 << 4)
  65. /* USB_CTRL_1 */
  66. #define MXC_USB_CTRL_UH1_EXT_CLK_EN (1 << 25)
  67. int mxc_set_usbcontrol(int port, unsigned int flags)
  68. {
  69. unsigned int v;
  70. void __iomem *usb_base = (void __iomem *)OTG_BASE_ADDR;
  71. void __iomem *usbother_base;
  72. int ret = 0;
  73. usbother_base = usb_base + MX5_USBOTHER_REGS_OFFSET;
  74. switch (port) {
  75. case 0: /* OTG port */
  76. if (flags & MXC_EHCI_INTERNAL_PHY) {
  77. v = __raw_readl(usbother_base +
  78. MXC_USB_PHY_CTR_FUNC_OFFSET);
  79. if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  80. v |= MXC_OTG_PHYCTRL_OC_POL_BIT;
  81. else
  82. v &= ~MXC_OTG_PHYCTRL_OC_POL_BIT;
  83. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  84. /* OC/USBPWR is used */
  85. v &= ~MXC_OTG_PHYCTRL_OC_DIS_BIT;
  86. else
  87. /* OC/USBPWR is not used */
  88. v |= MXC_OTG_PHYCTRL_OC_DIS_BIT;
  89. #ifdef CONFIG_MX51
  90. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  91. v |= MXC_OTG_PHYCTRL_PWR_POL_BIT;
  92. else
  93. v &= ~MXC_OTG_PHYCTRL_PWR_POL_BIT;
  94. #endif
  95. __raw_writel(v, usbother_base +
  96. MXC_USB_PHY_CTR_FUNC_OFFSET);
  97. v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
  98. #ifdef CONFIG_MX51
  99. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  100. v &= ~MXC_OTG_UCTRL_OPM_BIT;
  101. else
  102. v |= MXC_OTG_UCTRL_OPM_BIT;
  103. #endif
  104. #ifdef CONFIG_MX53
  105. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  106. v |= MXC_OTG_UCTRL_O_PWR_POL_BIT;
  107. else
  108. v &= ~MXC_OTG_UCTRL_O_PWR_POL_BIT;
  109. #endif
  110. __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
  111. }
  112. break;
  113. case 1: /* Host 1 ULPI */
  114. #ifdef CONFIG_MX51
  115. /* The clock for the USBH1 ULPI port will come externally
  116. from the PHY. */
  117. v = __raw_readl(usbother_base + MXC_USB_CTRL_1_OFFSET);
  118. __raw_writel(v | MXC_USB_CTRL_UH1_EXT_CLK_EN, usbother_base +
  119. MXC_USB_CTRL_1_OFFSET);
  120. #endif
  121. v = __raw_readl(usbother_base + MXC_USBCTRL_OFFSET);
  122. #ifdef CONFIG_MX51
  123. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  124. v &= ~MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask unused */
  125. else
  126. v |= MXC_H1_UCTRL_H1PM_BIT; /* H1 power mask used */
  127. #endif
  128. #ifdef CONFIG_MX53
  129. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  130. v |= MXC_H1_UCTRL_H1_PWR_POL_BIT;
  131. else
  132. v &= ~MXC_H1_UCTRL_H1_PWR_POL_BIT;
  133. #endif
  134. __raw_writel(v, usbother_base + MXC_USBCTRL_OFFSET);
  135. v = __raw_readl(usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
  136. if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  137. v |= MXC_H1_OC_POL_BIT;
  138. else
  139. v &= ~MXC_H1_OC_POL_BIT;
  140. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  141. v &= ~MXC_H1_OC_DIS_BIT; /* OC is used */
  142. else
  143. v |= MXC_H1_OC_DIS_BIT; /* OC is not used */
  144. __raw_writel(v, usbother_base + MXC_USB_PHY_CTR_FUNC_OFFSET);
  145. break;
  146. case 2: /* Host 2 ULPI */
  147. v = __raw_readl(usbother_base + MXC_USBH2CTRL_OFFSET);
  148. #ifdef CONFIG_MX51
  149. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  150. v &= ~MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask unused */
  151. else
  152. v |= MXC_H2_UCTRL_H2PM_BIT; /* H2 power mask used */
  153. #endif
  154. #ifdef CONFIG_MX53
  155. if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  156. v |= MXC_H2_UCTRL_H2_OC_POL_BIT;
  157. else
  158. v &= ~MXC_H2_UCTRL_H2_OC_POL_BIT;
  159. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  160. v &= ~MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is used */
  161. else
  162. v |= MXC_H2_UCTRL_H2_OC_DIS_BIT; /* OC is not used */
  163. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  164. v |= MXC_H2_UCTRL_H2_PWR_POL_BIT;
  165. else
  166. v &= ~MXC_H2_UCTRL_H2_PWR_POL_BIT;
  167. #endif
  168. __raw_writel(v, usbother_base + MXC_USBH2CTRL_OFFSET);
  169. break;
  170. #ifdef CONFIG_MX53
  171. case 3: /* Host 3 ULPI */
  172. v = __raw_readl(usbother_base + MXC_USBH3CTRL_OFFSET);
  173. if (flags & MXC_EHCI_OC_PIN_ACTIVE_LOW)
  174. v |= MXC_H3_UCTRL_H3_OC_POL_BIT;
  175. else
  176. v &= ~MXC_H3_UCTRL_H3_OC_POL_BIT;
  177. if (flags & MXC_EHCI_POWER_PINS_ENABLED)
  178. v &= ~MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is used */
  179. else
  180. v |= MXC_H3_UCTRL_H3_OC_DIS_BIT; /* OC is not used */
  181. if (flags & MXC_EHCI_PWR_PIN_ACTIVE_HIGH)
  182. v |= MXC_H3_UCTRL_H3_PWR_POL_BIT;
  183. else
  184. v &= ~MXC_H3_UCTRL_H3_PWR_POL_BIT;
  185. __raw_writel(v, usbother_base + MXC_USBH3CTRL_OFFSET);
  186. break;
  187. #endif
  188. }
  189. return ret;
  190. }
  191. int __weak board_ehci_hcd_init(int port)
  192. {
  193. return 0;
  194. }
  195. void __weak board_ehci_hcd_postinit(struct usb_ehci *ehci, int port)
  196. {
  197. }
  198. __weak void mx5_ehci_powerup_fixup(struct ehci_ctrl *ctrl, uint32_t *status_reg,
  199. uint32_t *reg)
  200. {
  201. mdelay(50);
  202. }
  203. static const struct ehci_ops mx5_ehci_ops = {
  204. .powerup_fixup = mx5_ehci_powerup_fixup,
  205. };
  206. int ehci_hcd_init(int index, enum usb_init_type init,
  207. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  208. {
  209. struct usb_ehci *ehci;
  210. /* The only user for this is efikamx-usb */
  211. ehci_set_controller_priv(index, NULL, &mx5_ehci_ops);
  212. set_usboh3_clk();
  213. enable_usboh3_clk(true);
  214. set_usb_phy_clk();
  215. enable_usb_phy1_clk(true);
  216. enable_usb_phy2_clk(true);
  217. mdelay(1);
  218. /* Do board specific initialization */
  219. board_ehci_hcd_init(CONFIG_MXC_USB_PORT);
  220. ehci = (struct usb_ehci *)(OTG_BASE_ADDR +
  221. (0x200 * CONFIG_MXC_USB_PORT));
  222. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  223. *hcor = (struct ehci_hcor *)((uint32_t)*hccr +
  224. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  225. setbits_le32(&ehci->usbmode, CM_HOST);
  226. __raw_writel(CONFIG_MXC_USB_PORTSC, &ehci->portsc);
  227. setbits_le32(&ehci->portsc, USB_EN);
  228. mxc_set_usbcontrol(CONFIG_MXC_USB_PORT, CONFIG_MXC_USB_FLAGS);
  229. mdelay(10);
  230. /* Do board specific post-initialization */
  231. board_ehci_hcd_postinit(ehci, CONFIG_MXC_USB_PORT);
  232. return 0;
  233. }
  234. int ehci_hcd_stop(int index)
  235. {
  236. return 0;
  237. }