ehci-fsl.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009, 2011, 2016 Freescale Semiconductor, Inc.
  4. *
  5. * (C) Copyright 2008, Excito Elektronik i Sk=E5ne AB
  6. *
  7. * Author: Tor Krill tor@excito.com
  8. */
  9. #include <common.h>
  10. #include <pci.h>
  11. #include <usb.h>
  12. #include <asm/io.h>
  13. #include <usb/ehci-ci.h>
  14. #include <hwconfig.h>
  15. #include <fsl_usb.h>
  16. #include <fdt_support.h>
  17. #include <dm.h>
  18. #include "ehci.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  21. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  22. #endif
  23. #ifdef CONFIG_DM_USB
  24. struct ehci_fsl_priv {
  25. struct ehci_ctrl ehci;
  26. fdt_addr_t hcd_base;
  27. char *phy_type;
  28. };
  29. #endif
  30. static void set_txfifothresh(struct usb_ehci *, u32);
  31. #ifdef CONFIG_DM_USB
  32. static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
  33. struct ehci_hccr *hccr, struct ehci_hcor *hcor);
  34. #else
  35. static int ehci_fsl_init(int index, struct usb_ehci *ehci,
  36. struct ehci_hccr *hccr, struct ehci_hcor *hcor);
  37. #endif
  38. /* Check USB PHY clock valid */
  39. static int usb_phy_clk_valid(struct usb_ehci *ehci)
  40. {
  41. if (!((in_be32(&ehci->control) & PHY_CLK_VALID) ||
  42. in_be32(&ehci->prictrl))) {
  43. printf("USB PHY clock invalid!\n");
  44. return 0;
  45. } else {
  46. return 1;
  47. }
  48. }
  49. #ifdef CONFIG_DM_USB
  50. static int ehci_fsl_ofdata_to_platdata(struct udevice *dev)
  51. {
  52. struct ehci_fsl_priv *priv = dev_get_priv(dev);
  53. const void *prop;
  54. prop = fdt_getprop(gd->fdt_blob, dev_of_offset(dev), "phy_type",
  55. NULL);
  56. if (prop) {
  57. priv->phy_type = (char *)prop;
  58. debug("phy_type %s\n", priv->phy_type);
  59. }
  60. return 0;
  61. }
  62. static int ehci_fsl_init_after_reset(struct ehci_ctrl *ctrl)
  63. {
  64. struct usb_ehci *ehci = NULL;
  65. struct ehci_fsl_priv *priv = container_of(ctrl, struct ehci_fsl_priv,
  66. ehci);
  67. ehci = (struct usb_ehci *)priv->hcd_base;
  68. if (ehci_fsl_init(priv, ehci, priv->ehci.hccr, priv->ehci.hcor) < 0)
  69. return -ENXIO;
  70. return 0;
  71. }
  72. static const struct ehci_ops fsl_ehci_ops = {
  73. .init_after_reset = ehci_fsl_init_after_reset,
  74. };
  75. static int ehci_fsl_probe(struct udevice *dev)
  76. {
  77. struct ehci_fsl_priv *priv = dev_get_priv(dev);
  78. struct usb_ehci *ehci = NULL;
  79. struct ehci_hccr *hccr;
  80. struct ehci_hcor *hcor;
  81. /*
  82. * Get the base address for EHCI controller from the device node
  83. */
  84. priv->hcd_base = devfdt_get_addr(dev);
  85. if (priv->hcd_base == FDT_ADDR_T_NONE) {
  86. debug("Can't get the EHCI register base address\n");
  87. return -ENXIO;
  88. }
  89. ehci = (struct usb_ehci *)priv->hcd_base;
  90. hccr = (struct ehci_hccr *)(&ehci->caplength);
  91. hcor = (struct ehci_hcor *)
  92. ((void *)hccr + HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  93. if (ehci_fsl_init(priv, ehci, hccr, hcor) < 0)
  94. return -ENXIO;
  95. debug("ehci-fsl: init hccr %p and hcor %p hc_length %d\n",
  96. (void *)hccr, (void *)hcor,
  97. HC_LENGTH(ehci_readl(&hccr->cr_capbase)));
  98. return ehci_register(dev, hccr, hcor, &fsl_ehci_ops, 0, USB_INIT_HOST);
  99. }
  100. static const struct udevice_id ehci_usb_ids[] = {
  101. { .compatible = "fsl-usb2-mph", },
  102. { .compatible = "fsl-usb2-dr", },
  103. { }
  104. };
  105. U_BOOT_DRIVER(ehci_fsl) = {
  106. .name = "ehci_fsl",
  107. .id = UCLASS_USB,
  108. .of_match = ehci_usb_ids,
  109. .ofdata_to_platdata = ehci_fsl_ofdata_to_platdata,
  110. .probe = ehci_fsl_probe,
  111. .remove = ehci_deregister,
  112. .ops = &ehci_usb_ops,
  113. .platdata_auto_alloc_size = sizeof(struct usb_platdata),
  114. .priv_auto_alloc_size = sizeof(struct ehci_fsl_priv),
  115. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  116. };
  117. #else
  118. /*
  119. * Create the appropriate control structures to manage
  120. * a new EHCI host controller.
  121. *
  122. * Excerpts from linux ehci fsl driver.
  123. */
  124. int ehci_hcd_init(int index, enum usb_init_type init,
  125. struct ehci_hccr **hccr, struct ehci_hcor **hcor)
  126. {
  127. struct usb_ehci *ehci = NULL;
  128. switch (index) {
  129. case 0:
  130. ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB1_ADDR;
  131. break;
  132. case 1:
  133. ehci = (struct usb_ehci *)CONFIG_SYS_FSL_USB2_ADDR;
  134. break;
  135. default:
  136. printf("ERROR: wrong controller index!!\n");
  137. return -EINVAL;
  138. };
  139. *hccr = (struct ehci_hccr *)((uint32_t)&ehci->caplength);
  140. *hcor = (struct ehci_hcor *)((uint32_t) *hccr +
  141. HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));
  142. return ehci_fsl_init(index, ehci, *hccr, *hcor);
  143. }
  144. /*
  145. * Destroy the appropriate control structures corresponding
  146. * the the EHCI host controller.
  147. */
  148. int ehci_hcd_stop(int index)
  149. {
  150. return 0;
  151. }
  152. #endif
  153. #ifdef CONFIG_DM_USB
  154. static int ehci_fsl_init(struct ehci_fsl_priv *priv, struct usb_ehci *ehci,
  155. struct ehci_hccr *hccr, struct ehci_hcor *hcor)
  156. #else
  157. static int ehci_fsl_init(int index, struct usb_ehci *ehci,
  158. struct ehci_hccr *hccr, struct ehci_hcor *hcor)
  159. #endif
  160. {
  161. const char *phy_type = NULL;
  162. #ifndef CONFIG_DM_USB
  163. size_t len;
  164. char current_usb_controller[5];
  165. #endif
  166. #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  167. char usb_phy[5];
  168. usb_phy[0] = '\0';
  169. #endif
  170. if (has_erratum_a007075()) {
  171. /*
  172. * A 5ms delay is needed after applying soft-reset to the
  173. * controller to let external ULPI phy come out of reset.
  174. * This delay needs to be added before re-initializing
  175. * the controller after soft-resetting completes
  176. */
  177. mdelay(5);
  178. }
  179. /* Set to Host mode */
  180. setbits_le32(&ehci->usbmode, CM_HOST);
  181. out_be32(&ehci->snoop1, SNOOP_SIZE_2GB);
  182. out_be32(&ehci->snoop2, 0x80000000 | SNOOP_SIZE_2GB);
  183. /* Init phy */
  184. #ifdef CONFIG_DM_USB
  185. if (priv->phy_type)
  186. phy_type = priv->phy_type;
  187. #else
  188. memset(current_usb_controller, '\0', 5);
  189. snprintf(current_usb_controller, sizeof(current_usb_controller),
  190. "usb%d", index+1);
  191. if (hwconfig_sub(current_usb_controller, "phy_type"))
  192. phy_type = hwconfig_subarg(current_usb_controller,
  193. "phy_type", &len);
  194. #endif
  195. else
  196. phy_type = env_get("usb_phy_type");
  197. if (!phy_type) {
  198. #ifdef CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY
  199. /* if none specified assume internal UTMI */
  200. strcpy(usb_phy, "utmi");
  201. phy_type = usb_phy;
  202. #else
  203. printf("WARNING: USB phy type not defined !!\n");
  204. return -1;
  205. #endif
  206. }
  207. if (!strncmp(phy_type, "utmi", 4)) {
  208. #if defined(CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY)
  209. clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
  210. PHY_CLK_SEL_UTMI);
  211. clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
  212. UTMI_PHY_EN);
  213. udelay(1000); /* delay required for PHY Clk to appear */
  214. #endif
  215. out_le32(&(hcor)->or_portsc[0], PORT_PTS_UTMI);
  216. clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
  217. USB_EN);
  218. } else {
  219. clrsetbits_be32(&ehci->control, CONTROL_REGISTER_W1C_MASK,
  220. PHY_CLK_SEL_ULPI);
  221. clrsetbits_be32(&ehci->control, UTMI_PHY_EN |
  222. CONTROL_REGISTER_W1C_MASK, USB_EN);
  223. udelay(1000); /* delay required for PHY Clk to appear */
  224. if (!usb_phy_clk_valid(ehci))
  225. return -EINVAL;
  226. out_le32(&(hcor)->or_portsc[0], PORT_PTS_ULPI);
  227. }
  228. out_be32(&ehci->prictrl, 0x0000000c);
  229. out_be32(&ehci->age_cnt_limit, 0x00000040);
  230. out_be32(&ehci->sictrl, 0x00000001);
  231. in_le32(&ehci->usbmode);
  232. if (has_erratum_a007798())
  233. set_txfifothresh(ehci, TXFIFOTHRESH);
  234. if (has_erratum_a004477()) {
  235. /*
  236. * When reset is issued while any ULPI transaction is ongoing
  237. * then it may result to corruption of ULPI Function Control
  238. * Register which eventually causes phy clock to enter low
  239. * power mode which stops the clock. Thus delay is required
  240. * before reset to let ongoing ULPI transaction complete.
  241. */
  242. udelay(1);
  243. }
  244. return 0;
  245. }
  246. /*
  247. * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register
  248. * to counter DDR latencies in writing data into Tx buffer.
  249. * This prevents Tx buffer from getting underrun
  250. */
  251. static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh)
  252. {
  253. u32 cmd;
  254. cmd = ehci_readl(&ehci->txfilltuning);
  255. cmd &= ~TXFIFO_THRESH_MASK;
  256. cmd |= TXFIFO_THRESH(txfifo_thresh);
  257. ehci_writel(&ehci->txfilltuning, cmd);
  258. }