dwc2.c 34 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2012 Oleksandr Tymoshenko <gonzo@freebsd.org>
  4. * Copyright (C) 2014 Marek Vasut <marex@denx.de>
  5. */
  6. #include <common.h>
  7. #include <dm.h>
  8. #include <errno.h>
  9. #include <usb.h>
  10. #include <malloc.h>
  11. #include <memalign.h>
  12. #include <phys2bus.h>
  13. #include <usbroothubdes.h>
  14. #include <wait_bit.h>
  15. #include <asm/io.h>
  16. #include <power/regulator.h>
  17. #include "dwc2.h"
  18. /* Use only HC channel 0. */
  19. #define DWC2_HC_CHANNEL 0
  20. #define DWC2_STATUS_BUF_SIZE 64
  21. #define DWC2_DATA_BUF_SIZE (CONFIG_USB_DWC2_BUFFER_SIZE * 1024)
  22. #define MAX_DEVICE 16
  23. #define MAX_ENDPOINT 16
  24. struct dwc2_priv {
  25. #ifdef CONFIG_DM_USB
  26. uint8_t aligned_buffer[DWC2_DATA_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  27. uint8_t status_buffer[DWC2_STATUS_BUF_SIZE] __aligned(ARCH_DMA_MINALIGN);
  28. #ifdef CONFIG_DM_REGULATOR
  29. struct udevice *vbus_supply;
  30. #endif
  31. #else
  32. uint8_t *aligned_buffer;
  33. uint8_t *status_buffer;
  34. #endif
  35. u8 in_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  36. u8 out_data_toggle[MAX_DEVICE][MAX_ENDPOINT];
  37. struct dwc2_core_regs *regs;
  38. int root_hub_devnum;
  39. bool ext_vbus;
  40. /*
  41. * The hnp/srp capability must be disabled if the platform
  42. * does't support hnp/srp. Otherwise the force mode can't work.
  43. */
  44. bool hnp_srp_disable;
  45. bool oc_disable;
  46. };
  47. #ifndef CONFIG_DM_USB
  48. /* We need cacheline-aligned buffers for DMA transfers and dcache support */
  49. DEFINE_ALIGN_BUFFER(uint8_t, aligned_buffer_addr, DWC2_DATA_BUF_SIZE,
  50. ARCH_DMA_MINALIGN);
  51. DEFINE_ALIGN_BUFFER(uint8_t, status_buffer_addr, DWC2_STATUS_BUF_SIZE,
  52. ARCH_DMA_MINALIGN);
  53. static struct dwc2_priv local;
  54. #endif
  55. /*
  56. * DWC2 IP interface
  57. */
  58. /*
  59. * Initializes the FSLSPClkSel field of the HCFG register
  60. * depending on the PHY type.
  61. */
  62. static void init_fslspclksel(struct dwc2_core_regs *regs)
  63. {
  64. uint32_t phyclk;
  65. #if (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  66. phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
  67. #else
  68. /* High speed PHY running at full speed or high speed */
  69. phyclk = DWC2_HCFG_FSLSPCLKSEL_30_60_MHZ;
  70. #endif
  71. #ifdef CONFIG_DWC2_ULPI_FS_LS
  72. uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  73. uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  74. DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  75. uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  76. DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  77. if (hval == 2 && fval == 1)
  78. phyclk = DWC2_HCFG_FSLSPCLKSEL_48_MHZ; /* Full speed PHY */
  79. #endif
  80. clrsetbits_le32(&regs->host_regs.hcfg,
  81. DWC2_HCFG_FSLSPCLKSEL_MASK,
  82. phyclk << DWC2_HCFG_FSLSPCLKSEL_OFFSET);
  83. }
  84. /*
  85. * Flush a Tx FIFO.
  86. *
  87. * @param regs Programming view of DWC_otg controller.
  88. * @param num Tx FIFO to flush.
  89. */
  90. static void dwc_otg_flush_tx_fifo(struct dwc2_core_regs *regs, const int num)
  91. {
  92. int ret;
  93. writel(DWC2_GRSTCTL_TXFFLSH | (num << DWC2_GRSTCTL_TXFNUM_OFFSET),
  94. &regs->grstctl);
  95. ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_TXFFLSH,
  96. false, 1000, false);
  97. if (ret)
  98. dev_info(dev, "%s: Timeout!\n", __func__);
  99. /* Wait for 3 PHY Clocks */
  100. udelay(1);
  101. }
  102. /*
  103. * Flush Rx FIFO.
  104. *
  105. * @param regs Programming view of DWC_otg controller.
  106. */
  107. static void dwc_otg_flush_rx_fifo(struct dwc2_core_regs *regs)
  108. {
  109. int ret;
  110. writel(DWC2_GRSTCTL_RXFFLSH, &regs->grstctl);
  111. ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_RXFFLSH,
  112. false, 1000, false);
  113. if (ret)
  114. dev_info(dev, "%s: Timeout!\n", __func__);
  115. /* Wait for 3 PHY Clocks */
  116. udelay(1);
  117. }
  118. /*
  119. * Do core a soft reset of the core. Be careful with this because it
  120. * resets all the internal state machines of the core.
  121. */
  122. static void dwc_otg_core_reset(struct dwc2_core_regs *regs)
  123. {
  124. int ret;
  125. /* Wait for AHB master IDLE state. */
  126. ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_AHBIDLE,
  127. true, 1000, false);
  128. if (ret)
  129. dev_info(dev, "%s: Timeout!\n", __func__);
  130. /* Core Soft Reset */
  131. writel(DWC2_GRSTCTL_CSFTRST, &regs->grstctl);
  132. ret = wait_for_bit_le32(&regs->grstctl, DWC2_GRSTCTL_CSFTRST,
  133. false, 1000, false);
  134. if (ret)
  135. dev_info(dev, "%s: Timeout!\n", __func__);
  136. /*
  137. * Wait for core to come out of reset.
  138. * NOTE: This long sleep is _very_ important, otherwise the core will
  139. * not stay in host mode after a connector ID change!
  140. */
  141. mdelay(100);
  142. }
  143. #if defined(CONFIG_DM_USB) && defined(CONFIG_DM_REGULATOR)
  144. static int dwc_vbus_supply_init(struct udevice *dev)
  145. {
  146. struct dwc2_priv *priv = dev_get_priv(dev);
  147. int ret;
  148. ret = device_get_supply_regulator(dev, "vbus-supply",
  149. &priv->vbus_supply);
  150. if (ret) {
  151. debug("%s: No vbus supply\n", dev->name);
  152. return 0;
  153. }
  154. ret = regulator_set_enable(priv->vbus_supply, true);
  155. if (ret) {
  156. dev_err(dev, "Error enabling vbus supply\n");
  157. return ret;
  158. }
  159. return 0;
  160. }
  161. static int dwc_vbus_supply_exit(struct udevice *dev)
  162. {
  163. struct dwc2_priv *priv = dev_get_priv(dev);
  164. int ret;
  165. if (priv->vbus_supply) {
  166. ret = regulator_set_enable(priv->vbus_supply, false);
  167. if (ret) {
  168. dev_err(dev, "Error disabling vbus supply\n");
  169. return ret;
  170. }
  171. }
  172. return 0;
  173. }
  174. #else
  175. static int dwc_vbus_supply_init(struct udevice *dev)
  176. {
  177. return 0;
  178. }
  179. #if defined(CONFIG_DM_USB)
  180. static int dwc_vbus_supply_exit(struct udevice *dev)
  181. {
  182. return 0;
  183. }
  184. #endif
  185. #endif
  186. /*
  187. * This function initializes the DWC_otg controller registers for
  188. * host mode.
  189. *
  190. * This function flushes the Tx and Rx FIFOs and it flushes any entries in the
  191. * request queues. Host channels are reset to ensure that they are ready for
  192. * performing transfers.
  193. *
  194. * @param dev USB Device (NULL if driver model is not being used)
  195. * @param regs Programming view of DWC_otg controller
  196. *
  197. */
  198. static void dwc_otg_core_host_init(struct udevice *dev,
  199. struct dwc2_core_regs *regs)
  200. {
  201. uint32_t nptxfifosize = 0;
  202. uint32_t ptxfifosize = 0;
  203. uint32_t hprt0 = 0;
  204. int i, ret, num_channels;
  205. /* Restart the Phy Clock */
  206. writel(0, &regs->pcgcctl);
  207. /* Initialize Host Configuration Register */
  208. init_fslspclksel(regs);
  209. #ifdef CONFIG_DWC2_DFLT_SPEED_FULL
  210. setbits_le32(&regs->host_regs.hcfg, DWC2_HCFG_FSLSSUPP);
  211. #endif
  212. /* Configure data FIFO sizes */
  213. #ifdef CONFIG_DWC2_ENABLE_DYNAMIC_FIFO
  214. if (readl(&regs->ghwcfg2) & DWC2_HWCFG2_DYNAMIC_FIFO) {
  215. /* Rx FIFO */
  216. writel(CONFIG_DWC2_HOST_RX_FIFO_SIZE, &regs->grxfsiz);
  217. /* Non-periodic Tx FIFO */
  218. nptxfifosize |= CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE <<
  219. DWC2_FIFOSIZE_DEPTH_OFFSET;
  220. nptxfifosize |= CONFIG_DWC2_HOST_RX_FIFO_SIZE <<
  221. DWC2_FIFOSIZE_STARTADDR_OFFSET;
  222. writel(nptxfifosize, &regs->gnptxfsiz);
  223. /* Periodic Tx FIFO */
  224. ptxfifosize |= CONFIG_DWC2_HOST_PERIO_TX_FIFO_SIZE <<
  225. DWC2_FIFOSIZE_DEPTH_OFFSET;
  226. ptxfifosize |= (CONFIG_DWC2_HOST_RX_FIFO_SIZE +
  227. CONFIG_DWC2_HOST_NPERIO_TX_FIFO_SIZE) <<
  228. DWC2_FIFOSIZE_STARTADDR_OFFSET;
  229. writel(ptxfifosize, &regs->hptxfsiz);
  230. }
  231. #endif
  232. /* Clear Host Set HNP Enable in the OTG Control Register */
  233. clrbits_le32(&regs->gotgctl, DWC2_GOTGCTL_HSTSETHNPEN);
  234. /* Make sure the FIFOs are flushed. */
  235. dwc_otg_flush_tx_fifo(regs, 0x10); /* All Tx FIFOs */
  236. dwc_otg_flush_rx_fifo(regs);
  237. /* Flush out any leftover queued requests. */
  238. num_channels = readl(&regs->ghwcfg2);
  239. num_channels &= DWC2_HWCFG2_NUM_HOST_CHAN_MASK;
  240. num_channels >>= DWC2_HWCFG2_NUM_HOST_CHAN_OFFSET;
  241. num_channels += 1;
  242. for (i = 0; i < num_channels; i++)
  243. clrsetbits_le32(&regs->hc_regs[i].hcchar,
  244. DWC2_HCCHAR_CHEN | DWC2_HCCHAR_EPDIR,
  245. DWC2_HCCHAR_CHDIS);
  246. /* Halt all channels to put them into a known state. */
  247. for (i = 0; i < num_channels; i++) {
  248. clrsetbits_le32(&regs->hc_regs[i].hcchar,
  249. DWC2_HCCHAR_EPDIR,
  250. DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS);
  251. ret = wait_for_bit_le32(&regs->hc_regs[i].hcchar,
  252. DWC2_HCCHAR_CHEN, false, 1000, false);
  253. if (ret)
  254. dev_info("%s: Timeout!\n", __func__);
  255. }
  256. /* Turn on the vbus power. */
  257. if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST) {
  258. hprt0 = readl(&regs->hprt0);
  259. hprt0 &= ~(DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET);
  260. hprt0 &= ~(DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG);
  261. if (!(hprt0 & DWC2_HPRT0_PRTPWR)) {
  262. hprt0 |= DWC2_HPRT0_PRTPWR;
  263. writel(hprt0, &regs->hprt0);
  264. }
  265. }
  266. if (dev)
  267. dwc_vbus_supply_init(dev);
  268. }
  269. /*
  270. * This function initializes the DWC_otg controller registers and
  271. * prepares the core for device mode or host mode operation.
  272. *
  273. * @param regs Programming view of the DWC_otg controller
  274. */
  275. static void dwc_otg_core_init(struct dwc2_priv *priv)
  276. {
  277. struct dwc2_core_regs *regs = priv->regs;
  278. uint32_t ahbcfg = 0;
  279. uint32_t usbcfg = 0;
  280. uint8_t brst_sz = CONFIG_DWC2_DMA_BURST_SIZE;
  281. /* Common Initialization */
  282. usbcfg = readl(&regs->gusbcfg);
  283. /* Program the ULPI External VBUS bit if needed */
  284. if (priv->ext_vbus) {
  285. usbcfg |= DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
  286. if (!priv->oc_disable) {
  287. usbcfg |= DWC2_GUSBCFG_ULPI_INT_VBUS_INDICATOR |
  288. DWC2_GUSBCFG_INDICATOR_PASSTHROUGH;
  289. }
  290. } else {
  291. usbcfg &= ~DWC2_GUSBCFG_ULPI_EXT_VBUS_DRV;
  292. }
  293. /* Set external TS Dline pulsing */
  294. #ifdef CONFIG_DWC2_TS_DLINE
  295. usbcfg |= DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
  296. #else
  297. usbcfg &= ~DWC2_GUSBCFG_TERM_SEL_DL_PULSE;
  298. #endif
  299. writel(usbcfg, &regs->gusbcfg);
  300. /* Reset the Controller */
  301. dwc_otg_core_reset(regs);
  302. /*
  303. * This programming sequence needs to happen in FS mode before
  304. * any other programming occurs
  305. */
  306. #if defined(CONFIG_DWC2_DFLT_SPEED_FULL) && \
  307. (CONFIG_DWC2_PHY_TYPE == DWC2_PHY_TYPE_FS)
  308. /* If FS mode with FS PHY */
  309. setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_PHYSEL);
  310. /* Reset after a PHY select */
  311. dwc_otg_core_reset(regs);
  312. /*
  313. * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS.
  314. * Also do this on HNP Dev/Host mode switches (done in dev_init
  315. * and host_init).
  316. */
  317. if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
  318. init_fslspclksel(regs);
  319. #ifdef CONFIG_DWC2_I2C_ENABLE
  320. /* Program GUSBCFG.OtgUtmifsSel to I2C */
  321. setbits_le32(&regs->gusbcfg, DWC2_GUSBCFG_OTGUTMIFSSEL);
  322. /* Program GI2CCTL.I2CEn */
  323. clrsetbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN |
  324. DWC2_GI2CCTL_I2CDEVADDR_MASK,
  325. 1 << DWC2_GI2CCTL_I2CDEVADDR_OFFSET);
  326. setbits_le32(&regs->gi2cctl, DWC2_GI2CCTL_I2CEN);
  327. #endif
  328. #else
  329. /* High speed PHY. */
  330. /*
  331. * HS PHY parameters. These parameters are preserved during
  332. * soft reset so only program the first time. Do a soft reset
  333. * immediately after setting phyif.
  334. */
  335. usbcfg &= ~(DWC2_GUSBCFG_ULPI_UTMI_SEL | DWC2_GUSBCFG_PHYIF);
  336. usbcfg |= CONFIG_DWC2_PHY_TYPE << DWC2_GUSBCFG_ULPI_UTMI_SEL_OFFSET;
  337. if (usbcfg & DWC2_GUSBCFG_ULPI_UTMI_SEL) { /* ULPI interface */
  338. #ifdef CONFIG_DWC2_PHY_ULPI_DDR
  339. usbcfg |= DWC2_GUSBCFG_DDRSEL;
  340. #else
  341. usbcfg &= ~DWC2_GUSBCFG_DDRSEL;
  342. #endif
  343. } else { /* UTMI+ interface */
  344. #if (CONFIG_DWC2_UTMI_WIDTH == 16)
  345. usbcfg |= DWC2_GUSBCFG_PHYIF;
  346. #endif
  347. }
  348. writel(usbcfg, &regs->gusbcfg);
  349. /* Reset after setting the PHY parameters */
  350. dwc_otg_core_reset(regs);
  351. #endif
  352. usbcfg = readl(&regs->gusbcfg);
  353. usbcfg &= ~(DWC2_GUSBCFG_ULPI_FSLS | DWC2_GUSBCFG_ULPI_CLK_SUS_M);
  354. #ifdef CONFIG_DWC2_ULPI_FS_LS
  355. uint32_t hwcfg2 = readl(&regs->ghwcfg2);
  356. uint32_t hval = (ghwcfg2 & DWC2_HWCFG2_HS_PHY_TYPE_MASK) >>
  357. DWC2_HWCFG2_HS_PHY_TYPE_OFFSET;
  358. uint32_t fval = (ghwcfg2 & DWC2_HWCFG2_FS_PHY_TYPE_MASK) >>
  359. DWC2_HWCFG2_FS_PHY_TYPE_OFFSET;
  360. if (hval == 2 && fval == 1) {
  361. usbcfg |= DWC2_GUSBCFG_ULPI_FSLS;
  362. usbcfg |= DWC2_GUSBCFG_ULPI_CLK_SUS_M;
  363. }
  364. #endif
  365. if (priv->hnp_srp_disable)
  366. usbcfg |= DWC2_GUSBCFG_FORCEHOSTMODE;
  367. writel(usbcfg, &regs->gusbcfg);
  368. /* Program the GAHBCFG Register. */
  369. switch (readl(&regs->ghwcfg2) & DWC2_HWCFG2_ARCHITECTURE_MASK) {
  370. case DWC2_HWCFG2_ARCHITECTURE_SLAVE_ONLY:
  371. break;
  372. case DWC2_HWCFG2_ARCHITECTURE_EXT_DMA:
  373. while (brst_sz > 1) {
  374. ahbcfg |= ahbcfg + (1 << DWC2_GAHBCFG_HBURSTLEN_OFFSET);
  375. ahbcfg &= DWC2_GAHBCFG_HBURSTLEN_MASK;
  376. brst_sz >>= 1;
  377. }
  378. #ifdef CONFIG_DWC2_DMA_ENABLE
  379. ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
  380. #endif
  381. break;
  382. case DWC2_HWCFG2_ARCHITECTURE_INT_DMA:
  383. ahbcfg |= DWC2_GAHBCFG_HBURSTLEN_INCR4;
  384. #ifdef CONFIG_DWC2_DMA_ENABLE
  385. ahbcfg |= DWC2_GAHBCFG_DMAENABLE;
  386. #endif
  387. break;
  388. }
  389. writel(ahbcfg, &regs->gahbcfg);
  390. /* Program the capabilities in GUSBCFG Register */
  391. usbcfg = 0;
  392. if (!priv->hnp_srp_disable)
  393. usbcfg |= DWC2_GUSBCFG_HNPCAP | DWC2_GUSBCFG_SRPCAP;
  394. #ifdef CONFIG_DWC2_IC_USB_CAP
  395. usbcfg |= DWC2_GUSBCFG_IC_USB_CAP;
  396. #endif
  397. setbits_le32(&regs->gusbcfg, usbcfg);
  398. }
  399. /*
  400. * Prepares a host channel for transferring packets to/from a specific
  401. * endpoint. The HCCHARn register is set up with the characteristics specified
  402. * in _hc. Host channel interrupts that may need to be serviced while this
  403. * transfer is in progress are enabled.
  404. *
  405. * @param regs Programming view of DWC_otg controller
  406. * @param hc Information needed to initialize the host channel
  407. */
  408. static void dwc_otg_hc_init(struct dwc2_core_regs *regs, uint8_t hc_num,
  409. struct usb_device *dev, uint8_t dev_addr, uint8_t ep_num,
  410. uint8_t ep_is_in, uint8_t ep_type, uint16_t max_packet)
  411. {
  412. struct dwc2_hc_regs *hc_regs = &regs->hc_regs[hc_num];
  413. uint32_t hcchar = (dev_addr << DWC2_HCCHAR_DEVADDR_OFFSET) |
  414. (ep_num << DWC2_HCCHAR_EPNUM_OFFSET) |
  415. (ep_is_in << DWC2_HCCHAR_EPDIR_OFFSET) |
  416. (ep_type << DWC2_HCCHAR_EPTYPE_OFFSET) |
  417. (max_packet << DWC2_HCCHAR_MPS_OFFSET);
  418. if (dev->speed == USB_SPEED_LOW)
  419. hcchar |= DWC2_HCCHAR_LSPDDEV;
  420. /*
  421. * Program the HCCHARn register with the endpoint characteristics
  422. * for the current transfer.
  423. */
  424. writel(hcchar, &hc_regs->hcchar);
  425. /* Program the HCSPLIT register, default to no SPLIT */
  426. writel(0, &hc_regs->hcsplt);
  427. }
  428. static void dwc_otg_hc_init_split(struct dwc2_hc_regs *hc_regs,
  429. uint8_t hub_devnum, uint8_t hub_port)
  430. {
  431. uint32_t hcsplt = 0;
  432. hcsplt = DWC2_HCSPLT_SPLTENA;
  433. hcsplt |= hub_devnum << DWC2_HCSPLT_HUBADDR_OFFSET;
  434. hcsplt |= hub_port << DWC2_HCSPLT_PRTADDR_OFFSET;
  435. /* Program the HCSPLIT register for SPLITs */
  436. writel(hcsplt, &hc_regs->hcsplt);
  437. }
  438. /*
  439. * DWC2 to USB API interface
  440. */
  441. /* Direction: In ; Request: Status */
  442. static int dwc_otg_submit_rh_msg_in_status(struct dwc2_core_regs *regs,
  443. struct usb_device *dev, void *buffer,
  444. int txlen, struct devrequest *cmd)
  445. {
  446. uint32_t hprt0 = 0;
  447. uint32_t port_status = 0;
  448. uint32_t port_change = 0;
  449. int len = 0;
  450. int stat = 0;
  451. switch (cmd->requesttype & ~USB_DIR_IN) {
  452. case 0:
  453. *(uint16_t *)buffer = cpu_to_le16(1);
  454. len = 2;
  455. break;
  456. case USB_RECIP_INTERFACE:
  457. case USB_RECIP_ENDPOINT:
  458. *(uint16_t *)buffer = cpu_to_le16(0);
  459. len = 2;
  460. break;
  461. case USB_TYPE_CLASS:
  462. *(uint32_t *)buffer = cpu_to_le32(0);
  463. len = 4;
  464. break;
  465. case USB_RECIP_OTHER | USB_TYPE_CLASS:
  466. hprt0 = readl(&regs->hprt0);
  467. if (hprt0 & DWC2_HPRT0_PRTCONNSTS)
  468. port_status |= USB_PORT_STAT_CONNECTION;
  469. if (hprt0 & DWC2_HPRT0_PRTENA)
  470. port_status |= USB_PORT_STAT_ENABLE;
  471. if (hprt0 & DWC2_HPRT0_PRTSUSP)
  472. port_status |= USB_PORT_STAT_SUSPEND;
  473. if (hprt0 & DWC2_HPRT0_PRTOVRCURRACT)
  474. port_status |= USB_PORT_STAT_OVERCURRENT;
  475. if (hprt0 & DWC2_HPRT0_PRTRST)
  476. port_status |= USB_PORT_STAT_RESET;
  477. if (hprt0 & DWC2_HPRT0_PRTPWR)
  478. port_status |= USB_PORT_STAT_POWER;
  479. if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) == DWC2_HPRT0_PRTSPD_LOW)
  480. port_status |= USB_PORT_STAT_LOW_SPEED;
  481. else if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
  482. DWC2_HPRT0_PRTSPD_HIGH)
  483. port_status |= USB_PORT_STAT_HIGH_SPEED;
  484. if (hprt0 & DWC2_HPRT0_PRTENCHNG)
  485. port_change |= USB_PORT_STAT_C_ENABLE;
  486. if (hprt0 & DWC2_HPRT0_PRTCONNDET)
  487. port_change |= USB_PORT_STAT_C_CONNECTION;
  488. if (hprt0 & DWC2_HPRT0_PRTOVRCURRCHNG)
  489. port_change |= USB_PORT_STAT_C_OVERCURRENT;
  490. *(uint32_t *)buffer = cpu_to_le32(port_status |
  491. (port_change << 16));
  492. len = 4;
  493. break;
  494. default:
  495. puts("unsupported root hub command\n");
  496. stat = USB_ST_STALLED;
  497. }
  498. dev->act_len = min(len, txlen);
  499. dev->status = stat;
  500. return stat;
  501. }
  502. /* Direction: In ; Request: Descriptor */
  503. static int dwc_otg_submit_rh_msg_in_descriptor(struct usb_device *dev,
  504. void *buffer, int txlen,
  505. struct devrequest *cmd)
  506. {
  507. unsigned char data[32];
  508. uint32_t dsc;
  509. int len = 0;
  510. int stat = 0;
  511. uint16_t wValue = cpu_to_le16(cmd->value);
  512. uint16_t wLength = cpu_to_le16(cmd->length);
  513. switch (cmd->requesttype & ~USB_DIR_IN) {
  514. case 0:
  515. switch (wValue & 0xff00) {
  516. case 0x0100: /* device descriptor */
  517. len = min3(txlen, (int)sizeof(root_hub_dev_des), (int)wLength);
  518. memcpy(buffer, root_hub_dev_des, len);
  519. break;
  520. case 0x0200: /* configuration descriptor */
  521. len = min3(txlen, (int)sizeof(root_hub_config_des), (int)wLength);
  522. memcpy(buffer, root_hub_config_des, len);
  523. break;
  524. case 0x0300: /* string descriptors */
  525. switch (wValue & 0xff) {
  526. case 0x00:
  527. len = min3(txlen, (int)sizeof(root_hub_str_index0),
  528. (int)wLength);
  529. memcpy(buffer, root_hub_str_index0, len);
  530. break;
  531. case 0x01:
  532. len = min3(txlen, (int)sizeof(root_hub_str_index1),
  533. (int)wLength);
  534. memcpy(buffer, root_hub_str_index1, len);
  535. break;
  536. }
  537. break;
  538. default:
  539. stat = USB_ST_STALLED;
  540. }
  541. break;
  542. case USB_TYPE_CLASS:
  543. /* Root port config, set 1 port and nothing else. */
  544. dsc = 0x00000001;
  545. data[0] = 9; /* min length; */
  546. data[1] = 0x29;
  547. data[2] = dsc & RH_A_NDP;
  548. data[3] = 0;
  549. if (dsc & RH_A_PSM)
  550. data[3] |= 0x1;
  551. if (dsc & RH_A_NOCP)
  552. data[3] |= 0x10;
  553. else if (dsc & RH_A_OCPM)
  554. data[3] |= 0x8;
  555. /* corresponds to data[4-7] */
  556. data[5] = (dsc & RH_A_POTPGT) >> 24;
  557. data[7] = dsc & RH_B_DR;
  558. if (data[2] < 7) {
  559. data[8] = 0xff;
  560. } else {
  561. data[0] += 2;
  562. data[8] = (dsc & RH_B_DR) >> 8;
  563. data[9] = 0xff;
  564. data[10] = data[9];
  565. }
  566. len = min3(txlen, (int)data[0], (int)wLength);
  567. memcpy(buffer, data, len);
  568. break;
  569. default:
  570. puts("unsupported root hub command\n");
  571. stat = USB_ST_STALLED;
  572. }
  573. dev->act_len = min(len, txlen);
  574. dev->status = stat;
  575. return stat;
  576. }
  577. /* Direction: In ; Request: Configuration */
  578. static int dwc_otg_submit_rh_msg_in_configuration(struct usb_device *dev,
  579. void *buffer, int txlen,
  580. struct devrequest *cmd)
  581. {
  582. int len = 0;
  583. int stat = 0;
  584. switch (cmd->requesttype & ~USB_DIR_IN) {
  585. case 0:
  586. *(uint8_t *)buffer = 0x01;
  587. len = 1;
  588. break;
  589. default:
  590. puts("unsupported root hub command\n");
  591. stat = USB_ST_STALLED;
  592. }
  593. dev->act_len = min(len, txlen);
  594. dev->status = stat;
  595. return stat;
  596. }
  597. /* Direction: In */
  598. static int dwc_otg_submit_rh_msg_in(struct dwc2_priv *priv,
  599. struct usb_device *dev, void *buffer,
  600. int txlen, struct devrequest *cmd)
  601. {
  602. switch (cmd->request) {
  603. case USB_REQ_GET_STATUS:
  604. return dwc_otg_submit_rh_msg_in_status(priv->regs, dev, buffer,
  605. txlen, cmd);
  606. case USB_REQ_GET_DESCRIPTOR:
  607. return dwc_otg_submit_rh_msg_in_descriptor(dev, buffer,
  608. txlen, cmd);
  609. case USB_REQ_GET_CONFIGURATION:
  610. return dwc_otg_submit_rh_msg_in_configuration(dev, buffer,
  611. txlen, cmd);
  612. default:
  613. puts("unsupported root hub command\n");
  614. return USB_ST_STALLED;
  615. }
  616. }
  617. /* Direction: Out */
  618. static int dwc_otg_submit_rh_msg_out(struct dwc2_priv *priv,
  619. struct usb_device *dev,
  620. void *buffer, int txlen,
  621. struct devrequest *cmd)
  622. {
  623. struct dwc2_core_regs *regs = priv->regs;
  624. int len = 0;
  625. int stat = 0;
  626. uint16_t bmrtype_breq = cmd->requesttype | (cmd->request << 8);
  627. uint16_t wValue = cpu_to_le16(cmd->value);
  628. switch (bmrtype_breq & ~USB_DIR_IN) {
  629. case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_ENDPOINT:
  630. case (USB_REQ_CLEAR_FEATURE << 8) | USB_TYPE_CLASS:
  631. break;
  632. case (USB_REQ_CLEAR_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
  633. switch (wValue) {
  634. case USB_PORT_FEAT_C_CONNECTION:
  635. setbits_le32(&regs->hprt0, DWC2_HPRT0_PRTCONNDET);
  636. break;
  637. }
  638. break;
  639. case (USB_REQ_SET_FEATURE << 8) | USB_RECIP_OTHER | USB_TYPE_CLASS:
  640. switch (wValue) {
  641. case USB_PORT_FEAT_SUSPEND:
  642. break;
  643. case USB_PORT_FEAT_RESET:
  644. clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  645. DWC2_HPRT0_PRTCONNDET |
  646. DWC2_HPRT0_PRTENCHNG |
  647. DWC2_HPRT0_PRTOVRCURRCHNG,
  648. DWC2_HPRT0_PRTRST);
  649. mdelay(50);
  650. clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTRST);
  651. break;
  652. case USB_PORT_FEAT_POWER:
  653. clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  654. DWC2_HPRT0_PRTCONNDET |
  655. DWC2_HPRT0_PRTENCHNG |
  656. DWC2_HPRT0_PRTOVRCURRCHNG,
  657. DWC2_HPRT0_PRTRST);
  658. break;
  659. case USB_PORT_FEAT_ENABLE:
  660. break;
  661. }
  662. break;
  663. case (USB_REQ_SET_ADDRESS << 8):
  664. priv->root_hub_devnum = wValue;
  665. break;
  666. case (USB_REQ_SET_CONFIGURATION << 8):
  667. break;
  668. default:
  669. puts("unsupported root hub command\n");
  670. stat = USB_ST_STALLED;
  671. }
  672. len = min(len, txlen);
  673. dev->act_len = len;
  674. dev->status = stat;
  675. return stat;
  676. }
  677. static int dwc_otg_submit_rh_msg(struct dwc2_priv *priv, struct usb_device *dev,
  678. unsigned long pipe, void *buffer, int txlen,
  679. struct devrequest *cmd)
  680. {
  681. int stat = 0;
  682. if (usb_pipeint(pipe)) {
  683. puts("Root-Hub submit IRQ: NOT implemented\n");
  684. return 0;
  685. }
  686. if (cmd->requesttype & USB_DIR_IN)
  687. stat = dwc_otg_submit_rh_msg_in(priv, dev, buffer, txlen, cmd);
  688. else
  689. stat = dwc_otg_submit_rh_msg_out(priv, dev, buffer, txlen, cmd);
  690. mdelay(1);
  691. return stat;
  692. }
  693. int wait_for_chhltd(struct dwc2_hc_regs *hc_regs, uint32_t *sub, u8 *toggle)
  694. {
  695. int ret;
  696. uint32_t hcint, hctsiz;
  697. ret = wait_for_bit_le32(&hc_regs->hcint, DWC2_HCINT_CHHLTD, true,
  698. 2000, false);
  699. if (ret)
  700. return ret;
  701. hcint = readl(&hc_regs->hcint);
  702. hctsiz = readl(&hc_regs->hctsiz);
  703. *sub = (hctsiz & DWC2_HCTSIZ_XFERSIZE_MASK) >>
  704. DWC2_HCTSIZ_XFERSIZE_OFFSET;
  705. *toggle = (hctsiz & DWC2_HCTSIZ_PID_MASK) >> DWC2_HCTSIZ_PID_OFFSET;
  706. debug("%s: HCINT=%08x sub=%u toggle=%d\n", __func__, hcint, *sub,
  707. *toggle);
  708. if (hcint & DWC2_HCINT_XFERCOMP)
  709. return 0;
  710. if (hcint & (DWC2_HCINT_NAK | DWC2_HCINT_FRMOVRUN))
  711. return -EAGAIN;
  712. debug("%s: Error (HCINT=%08x)\n", __func__, hcint);
  713. return -EINVAL;
  714. }
  715. static int dwc2_eptype[] = {
  716. DWC2_HCCHAR_EPTYPE_ISOC,
  717. DWC2_HCCHAR_EPTYPE_INTR,
  718. DWC2_HCCHAR_EPTYPE_CONTROL,
  719. DWC2_HCCHAR_EPTYPE_BULK,
  720. };
  721. static int transfer_chunk(struct dwc2_hc_regs *hc_regs, void *aligned_buffer,
  722. u8 *pid, int in, void *buffer, int num_packets,
  723. int xfer_len, int *actual_len, int odd_frame)
  724. {
  725. int ret = 0;
  726. uint32_t sub;
  727. debug("%s: chunk: pid %d xfer_len %u pkts %u\n", __func__,
  728. *pid, xfer_len, num_packets);
  729. writel((xfer_len << DWC2_HCTSIZ_XFERSIZE_OFFSET) |
  730. (num_packets << DWC2_HCTSIZ_PKTCNT_OFFSET) |
  731. (*pid << DWC2_HCTSIZ_PID_OFFSET),
  732. &hc_regs->hctsiz);
  733. if (xfer_len) {
  734. if (in) {
  735. invalidate_dcache_range(
  736. (uintptr_t)aligned_buffer,
  737. (uintptr_t)aligned_buffer +
  738. roundup(xfer_len, ARCH_DMA_MINALIGN));
  739. } else {
  740. memcpy(aligned_buffer, buffer, xfer_len);
  741. flush_dcache_range(
  742. (uintptr_t)aligned_buffer,
  743. (uintptr_t)aligned_buffer +
  744. roundup(xfer_len, ARCH_DMA_MINALIGN));
  745. }
  746. }
  747. writel(phys_to_bus((unsigned long)aligned_buffer), &hc_regs->hcdma);
  748. /* Clear old interrupt conditions for this host channel. */
  749. writel(0x3fff, &hc_regs->hcint);
  750. /* Set host channel enable after all other setup is complete. */
  751. clrsetbits_le32(&hc_regs->hcchar, DWC2_HCCHAR_MULTICNT_MASK |
  752. DWC2_HCCHAR_CHEN | DWC2_HCCHAR_CHDIS |
  753. DWC2_HCCHAR_ODDFRM,
  754. (1 << DWC2_HCCHAR_MULTICNT_OFFSET) |
  755. (odd_frame << DWC2_HCCHAR_ODDFRM_OFFSET) |
  756. DWC2_HCCHAR_CHEN);
  757. ret = wait_for_chhltd(hc_regs, &sub, pid);
  758. if (ret < 0)
  759. return ret;
  760. if (in) {
  761. xfer_len -= sub;
  762. invalidate_dcache_range((unsigned long)aligned_buffer,
  763. (unsigned long)aligned_buffer +
  764. roundup(xfer_len, ARCH_DMA_MINALIGN));
  765. memcpy(buffer, aligned_buffer, xfer_len);
  766. }
  767. *actual_len = xfer_len;
  768. return ret;
  769. }
  770. int chunk_msg(struct dwc2_priv *priv, struct usb_device *dev,
  771. unsigned long pipe, u8 *pid, int in, void *buffer, int len)
  772. {
  773. struct dwc2_core_regs *regs = priv->regs;
  774. struct dwc2_hc_regs *hc_regs = &regs->hc_regs[DWC2_HC_CHANNEL];
  775. struct dwc2_host_regs *host_regs = &regs->host_regs;
  776. int devnum = usb_pipedevice(pipe);
  777. int ep = usb_pipeendpoint(pipe);
  778. int max = usb_maxpacket(dev, pipe);
  779. int eptype = dwc2_eptype[usb_pipetype(pipe)];
  780. int done = 0;
  781. int ret = 0;
  782. int do_split = 0;
  783. int complete_split = 0;
  784. uint32_t xfer_len;
  785. uint32_t num_packets;
  786. int stop_transfer = 0;
  787. uint32_t max_xfer_len;
  788. int ssplit_frame_num = 0;
  789. debug("%s: msg: pipe %lx pid %d in %d len %d\n", __func__, pipe, *pid,
  790. in, len);
  791. max_xfer_len = CONFIG_DWC2_MAX_PACKET_COUNT * max;
  792. if (max_xfer_len > CONFIG_DWC2_MAX_TRANSFER_SIZE)
  793. max_xfer_len = CONFIG_DWC2_MAX_TRANSFER_SIZE;
  794. if (max_xfer_len > DWC2_DATA_BUF_SIZE)
  795. max_xfer_len = DWC2_DATA_BUF_SIZE;
  796. /* Make sure that max_xfer_len is a multiple of max packet size. */
  797. num_packets = max_xfer_len / max;
  798. max_xfer_len = num_packets * max;
  799. /* Initialize channel */
  800. dwc_otg_hc_init(regs, DWC2_HC_CHANNEL, dev, devnum, ep, in,
  801. eptype, max);
  802. /* Check if the target is a FS/LS device behind a HS hub */
  803. if (dev->speed != USB_SPEED_HIGH) {
  804. uint8_t hub_addr;
  805. uint8_t hub_port;
  806. uint32_t hprt0 = readl(&regs->hprt0);
  807. if ((hprt0 & DWC2_HPRT0_PRTSPD_MASK) ==
  808. DWC2_HPRT0_PRTSPD_HIGH) {
  809. usb_find_usb2_hub_address_port(dev, &hub_addr,
  810. &hub_port);
  811. dwc_otg_hc_init_split(hc_regs, hub_addr, hub_port);
  812. do_split = 1;
  813. num_packets = 1;
  814. max_xfer_len = max;
  815. }
  816. }
  817. do {
  818. int actual_len = 0;
  819. uint32_t hcint;
  820. int odd_frame = 0;
  821. xfer_len = len - done;
  822. if (xfer_len > max_xfer_len)
  823. xfer_len = max_xfer_len;
  824. else if (xfer_len > max)
  825. num_packets = (xfer_len + max - 1) / max;
  826. else
  827. num_packets = 1;
  828. if (complete_split)
  829. setbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
  830. else if (do_split)
  831. clrbits_le32(&hc_regs->hcsplt, DWC2_HCSPLT_COMPSPLT);
  832. if (eptype == DWC2_HCCHAR_EPTYPE_INTR) {
  833. int uframe_num = readl(&host_regs->hfnum);
  834. if (!(uframe_num & 0x1))
  835. odd_frame = 1;
  836. }
  837. ret = transfer_chunk(hc_regs, priv->aligned_buffer, pid,
  838. in, (char *)buffer + done, num_packets,
  839. xfer_len, &actual_len, odd_frame);
  840. hcint = readl(&hc_regs->hcint);
  841. if (complete_split) {
  842. stop_transfer = 0;
  843. if (hcint & DWC2_HCINT_NYET) {
  844. ret = 0;
  845. int frame_num = DWC2_HFNUM_MAX_FRNUM &
  846. readl(&host_regs->hfnum);
  847. if (((frame_num - ssplit_frame_num) &
  848. DWC2_HFNUM_MAX_FRNUM) > 4)
  849. ret = -EAGAIN;
  850. } else
  851. complete_split = 0;
  852. } else if (do_split) {
  853. if (hcint & DWC2_HCINT_ACK) {
  854. ssplit_frame_num = DWC2_HFNUM_MAX_FRNUM &
  855. readl(&host_regs->hfnum);
  856. ret = 0;
  857. complete_split = 1;
  858. }
  859. }
  860. if (ret)
  861. break;
  862. if (actual_len < xfer_len)
  863. stop_transfer = 1;
  864. done += actual_len;
  865. /* Transactions are done when when either all data is transferred or
  866. * there is a short transfer. In case of a SPLIT make sure the CSPLIT
  867. * is executed.
  868. */
  869. } while (((done < len) && !stop_transfer) || complete_split);
  870. writel(0, &hc_regs->hcintmsk);
  871. writel(0xFFFFFFFF, &hc_regs->hcint);
  872. dev->status = 0;
  873. dev->act_len = done;
  874. return ret;
  875. }
  876. /* U-Boot USB transmission interface */
  877. int _submit_bulk_msg(struct dwc2_priv *priv, struct usb_device *dev,
  878. unsigned long pipe, void *buffer, int len)
  879. {
  880. int devnum = usb_pipedevice(pipe);
  881. int ep = usb_pipeendpoint(pipe);
  882. u8* pid;
  883. if ((devnum >= MAX_DEVICE) || (devnum == priv->root_hub_devnum)) {
  884. dev->status = 0;
  885. return -EINVAL;
  886. }
  887. if (usb_pipein(pipe))
  888. pid = &priv->in_data_toggle[devnum][ep];
  889. else
  890. pid = &priv->out_data_toggle[devnum][ep];
  891. return chunk_msg(priv, dev, pipe, pid, usb_pipein(pipe), buffer, len);
  892. }
  893. static int _submit_control_msg(struct dwc2_priv *priv, struct usb_device *dev,
  894. unsigned long pipe, void *buffer, int len,
  895. struct devrequest *setup)
  896. {
  897. int devnum = usb_pipedevice(pipe);
  898. int ret, act_len;
  899. u8 pid;
  900. /* For CONTROL endpoint pid should start with DATA1 */
  901. int status_direction;
  902. if (devnum == priv->root_hub_devnum) {
  903. dev->status = 0;
  904. dev->speed = USB_SPEED_HIGH;
  905. return dwc_otg_submit_rh_msg(priv, dev, pipe, buffer, len,
  906. setup);
  907. }
  908. /* SETUP stage */
  909. pid = DWC2_HC_PID_SETUP;
  910. do {
  911. ret = chunk_msg(priv, dev, pipe, &pid, 0, setup, 8);
  912. } while (ret == -EAGAIN);
  913. if (ret)
  914. return ret;
  915. /* DATA stage */
  916. act_len = 0;
  917. if (buffer) {
  918. pid = DWC2_HC_PID_DATA1;
  919. do {
  920. ret = chunk_msg(priv, dev, pipe, &pid, usb_pipein(pipe),
  921. buffer, len);
  922. act_len += dev->act_len;
  923. buffer += dev->act_len;
  924. len -= dev->act_len;
  925. } while (ret == -EAGAIN);
  926. if (ret)
  927. return ret;
  928. status_direction = usb_pipeout(pipe);
  929. } else {
  930. /* No-data CONTROL always ends with an IN transaction */
  931. status_direction = 1;
  932. }
  933. /* STATUS stage */
  934. pid = DWC2_HC_PID_DATA1;
  935. do {
  936. ret = chunk_msg(priv, dev, pipe, &pid, status_direction,
  937. priv->status_buffer, 0);
  938. } while (ret == -EAGAIN);
  939. if (ret)
  940. return ret;
  941. dev->act_len = act_len;
  942. return 0;
  943. }
  944. int _submit_int_msg(struct dwc2_priv *priv, struct usb_device *dev,
  945. unsigned long pipe, void *buffer, int len, int interval)
  946. {
  947. unsigned long timeout;
  948. int ret;
  949. /* FIXME: what is interval? */
  950. timeout = get_timer(0) + USB_TIMEOUT_MS(pipe);
  951. for (;;) {
  952. if (get_timer(0) > timeout) {
  953. dev_err(dev, "Timeout poll on interrupt endpoint\n");
  954. return -ETIMEDOUT;
  955. }
  956. ret = _submit_bulk_msg(priv, dev, pipe, buffer, len);
  957. if (ret != -EAGAIN)
  958. return ret;
  959. }
  960. }
  961. static int dwc2_init_common(struct udevice *dev, struct dwc2_priv *priv)
  962. {
  963. struct dwc2_core_regs *regs = priv->regs;
  964. uint32_t snpsid;
  965. int i, j;
  966. snpsid = readl(&regs->gsnpsid);
  967. dev_info(dev, "Core Release: %x.%03x\n",
  968. snpsid >> 12 & 0xf, snpsid & 0xfff);
  969. if ((snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_2xx &&
  970. (snpsid & DWC2_SNPSID_DEVID_MASK) != DWC2_SNPSID_DEVID_VER_3xx) {
  971. dev_info(dev, "SNPSID invalid (not DWC2 OTG device): %08x\n",
  972. snpsid);
  973. return -ENODEV;
  974. }
  975. #ifdef CONFIG_DWC2_PHY_ULPI_EXT_VBUS
  976. priv->ext_vbus = 1;
  977. #else
  978. priv->ext_vbus = 0;
  979. #endif
  980. dwc_otg_core_init(priv);
  981. dwc_otg_core_host_init(dev, regs);
  982. clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  983. DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
  984. DWC2_HPRT0_PRTOVRCURRCHNG,
  985. DWC2_HPRT0_PRTRST);
  986. mdelay(50);
  987. clrbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA | DWC2_HPRT0_PRTCONNDET |
  988. DWC2_HPRT0_PRTENCHNG | DWC2_HPRT0_PRTOVRCURRCHNG |
  989. DWC2_HPRT0_PRTRST);
  990. for (i = 0; i < MAX_DEVICE; i++) {
  991. for (j = 0; j < MAX_ENDPOINT; j++) {
  992. priv->in_data_toggle[i][j] = DWC2_HC_PID_DATA0;
  993. priv->out_data_toggle[i][j] = DWC2_HC_PID_DATA0;
  994. }
  995. }
  996. /*
  997. * Add a 1 second delay here. This gives the host controller
  998. * a bit time before the comminucation with the USB devices
  999. * is started (the bus is scanned) and fixes the USB detection
  1000. * problems with some problematic USB keys.
  1001. */
  1002. if (readl(&regs->gintsts) & DWC2_GINTSTS_CURMODE_HOST)
  1003. mdelay(1000);
  1004. return 0;
  1005. }
  1006. static void dwc2_uninit_common(struct dwc2_core_regs *regs)
  1007. {
  1008. /* Put everything in reset. */
  1009. clrsetbits_le32(&regs->hprt0, DWC2_HPRT0_PRTENA |
  1010. DWC2_HPRT0_PRTCONNDET | DWC2_HPRT0_PRTENCHNG |
  1011. DWC2_HPRT0_PRTOVRCURRCHNG,
  1012. DWC2_HPRT0_PRTRST);
  1013. }
  1014. #ifndef CONFIG_DM_USB
  1015. int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1016. int len, struct devrequest *setup)
  1017. {
  1018. return _submit_control_msg(&local, dev, pipe, buffer, len, setup);
  1019. }
  1020. int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1021. int len)
  1022. {
  1023. return _submit_bulk_msg(&local, dev, pipe, buffer, len);
  1024. }
  1025. int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
  1026. int len, int interval)
  1027. {
  1028. return _submit_int_msg(&local, dev, pipe, buffer, len, interval);
  1029. }
  1030. /* U-Boot USB control interface */
  1031. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1032. {
  1033. struct dwc2_priv *priv = &local;
  1034. memset(priv, '\0', sizeof(*priv));
  1035. priv->root_hub_devnum = 0;
  1036. priv->regs = (struct dwc2_core_regs *)CONFIG_USB_DWC2_REG_ADDR;
  1037. priv->aligned_buffer = aligned_buffer_addr;
  1038. priv->status_buffer = status_buffer_addr;
  1039. /* board-dependant init */
  1040. if (board_usb_init(index, USB_INIT_HOST))
  1041. return -1;
  1042. return dwc2_init_common(NULL, priv);
  1043. }
  1044. int usb_lowlevel_stop(int index)
  1045. {
  1046. dwc2_uninit_common(local.regs);
  1047. return 0;
  1048. }
  1049. #endif
  1050. #ifdef CONFIG_DM_USB
  1051. static int dwc2_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1052. unsigned long pipe, void *buffer, int length,
  1053. struct devrequest *setup)
  1054. {
  1055. struct dwc2_priv *priv = dev_get_priv(dev);
  1056. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1057. dev->name, udev, udev->dev->name, udev->portnr);
  1058. return _submit_control_msg(priv, udev, pipe, buffer, length, setup);
  1059. }
  1060. static int dwc2_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1061. unsigned long pipe, void *buffer, int length)
  1062. {
  1063. struct dwc2_priv *priv = dev_get_priv(dev);
  1064. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1065. return _submit_bulk_msg(priv, udev, pipe, buffer, length);
  1066. }
  1067. static int dwc2_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1068. unsigned long pipe, void *buffer, int length,
  1069. int interval)
  1070. {
  1071. struct dwc2_priv *priv = dev_get_priv(dev);
  1072. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1073. return _submit_int_msg(priv, udev, pipe, buffer, length, interval);
  1074. }
  1075. static int dwc2_usb_ofdata_to_platdata(struct udevice *dev)
  1076. {
  1077. struct dwc2_priv *priv = dev_get_priv(dev);
  1078. fdt_addr_t addr;
  1079. addr = dev_read_addr(dev);
  1080. if (addr == FDT_ADDR_T_NONE)
  1081. return -EINVAL;
  1082. priv->regs = (struct dwc2_core_regs *)addr;
  1083. priv->oc_disable = dev_read_bool(dev, "disable-over-current");
  1084. priv->hnp_srp_disable = dev_read_bool(dev, "hnp-srp-disable");
  1085. return 0;
  1086. }
  1087. static int dwc2_usb_probe(struct udevice *dev)
  1088. {
  1089. struct dwc2_priv *priv = dev_get_priv(dev);
  1090. struct usb_bus_priv *bus_priv = dev_get_uclass_priv(dev);
  1091. bus_priv->desc_before_addr = true;
  1092. return dwc2_init_common(dev, priv);
  1093. }
  1094. static int dwc2_usb_remove(struct udevice *dev)
  1095. {
  1096. struct dwc2_priv *priv = dev_get_priv(dev);
  1097. int ret;
  1098. ret = dwc_vbus_supply_exit(dev);
  1099. if (ret)
  1100. return ret;
  1101. dwc2_uninit_common(priv->regs);
  1102. return 0;
  1103. }
  1104. struct dm_usb_ops dwc2_usb_ops = {
  1105. .control = dwc2_submit_control_msg,
  1106. .bulk = dwc2_submit_bulk_msg,
  1107. .interrupt = dwc2_submit_int_msg,
  1108. };
  1109. static const struct udevice_id dwc2_usb_ids[] = {
  1110. { .compatible = "brcm,bcm2835-usb" },
  1111. { .compatible = "snps,dwc2" },
  1112. { }
  1113. };
  1114. U_BOOT_DRIVER(usb_dwc2) = {
  1115. .name = "dwc2_usb",
  1116. .id = UCLASS_USB,
  1117. .of_match = dwc2_usb_ids,
  1118. .ofdata_to_platdata = dwc2_usb_ofdata_to_platdata,
  1119. .probe = dwc2_usb_probe,
  1120. .remove = dwc2_usb_remove,
  1121. .ops = &dwc2_usb_ops,
  1122. .priv_auto_alloc_size = sizeof(struct dwc2_priv),
  1123. .flags = DM_FLAG_ALLOC_PRIV_DMA,
  1124. };
  1125. #endif