board_f.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2002-2006
  5. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  6. *
  7. * (C) Copyright 2002
  8. * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
  9. * Marius Groeger <mgroeger@sysgo.de>
  10. */
  11. #include <common.h>
  12. #include <console.h>
  13. #include <environment.h>
  14. #include <dm.h>
  15. #include <fdtdec.h>
  16. #include <fs.h>
  17. #include <i2c.h>
  18. #include <initcall.h>
  19. #include <malloc.h>
  20. #include <mapmem.h>
  21. #include <os.h>
  22. #include <post.h>
  23. #include <relocate.h>
  24. #include <spi.h>
  25. #include <status_led.h>
  26. #include <timer.h>
  27. #include <trace.h>
  28. #include <video.h>
  29. #include <watchdog.h>
  30. #ifdef CONFIG_MACH_TYPE
  31. #include <asm/mach-types.h>
  32. #endif
  33. #if defined(CONFIG_MP) && defined(CONFIG_PPC)
  34. #include <asm/mp.h>
  35. #endif
  36. #include <asm/io.h>
  37. #include <asm/sections.h>
  38. #include <dm/root.h>
  39. #include <linux/errno.h>
  40. /*
  41. * Pointer to initial global data area
  42. *
  43. * Here we initialize it if needed.
  44. */
  45. #ifdef XTRN_DECLARE_GLOBAL_DATA_PTR
  46. #undef XTRN_DECLARE_GLOBAL_DATA_PTR
  47. #define XTRN_DECLARE_GLOBAL_DATA_PTR /* empty = allocate here */
  48. DECLARE_GLOBAL_DATA_PTR = (gd_t *)(CONFIG_SYS_INIT_GD_ADDR);
  49. #else
  50. DECLARE_GLOBAL_DATA_PTR;
  51. #endif
  52. /*
  53. * TODO(sjg@chromium.org): IMO this code should be
  54. * refactored to a single function, something like:
  55. *
  56. * void led_set_state(enum led_colour_t colour, int on);
  57. */
  58. /************************************************************************
  59. * Coloured LED functionality
  60. ************************************************************************
  61. * May be supplied by boards if desired
  62. */
  63. __weak void coloured_LED_init(void) {}
  64. __weak void red_led_on(void) {}
  65. __weak void red_led_off(void) {}
  66. __weak void green_led_on(void) {}
  67. __weak void green_led_off(void) {}
  68. __weak void yellow_led_on(void) {}
  69. __weak void yellow_led_off(void) {}
  70. __weak void blue_led_on(void) {}
  71. __weak void blue_led_off(void) {}
  72. /*
  73. * Why is gd allocated a register? Prior to reloc it might be better to
  74. * just pass it around to each function in this file?
  75. *
  76. * After reloc one could argue that it is hardly used and doesn't need
  77. * to be in a register. Or if it is it should perhaps hold pointers to all
  78. * global data for all modules, so that post-reloc we can avoid the massive
  79. * literal pool we get on ARM. Or perhaps just encourage each module to use
  80. * a structure...
  81. */
  82. #if defined(CONFIG_WATCHDOG) || defined(CONFIG_HW_WATCHDOG)
  83. static int init_func_watchdog_init(void)
  84. {
  85. # if defined(CONFIG_HW_WATCHDOG) && \
  86. (defined(CONFIG_M68K) || defined(CONFIG_MICROBLAZE) || \
  87. defined(CONFIG_SH) || defined(CONFIG_AT91SAM9_WATCHDOG) || \
  88. defined(CONFIG_DESIGNWARE_WATCHDOG) || \
  89. defined(CONFIG_IMX_WATCHDOG))
  90. hw_watchdog_init();
  91. puts(" Watchdog enabled\n");
  92. # endif
  93. WATCHDOG_RESET();
  94. return 0;
  95. }
  96. int init_func_watchdog_reset(void)
  97. {
  98. WATCHDOG_RESET();
  99. return 0;
  100. }
  101. #endif /* CONFIG_WATCHDOG */
  102. __weak void board_add_ram_info(int use_default)
  103. {
  104. /* please define platform specific board_add_ram_info() */
  105. }
  106. static int init_baud_rate(void)
  107. {
  108. gd->baudrate = env_get_ulong("baudrate", 10, CONFIG_BAUDRATE);
  109. return 0;
  110. }
  111. static int display_text_info(void)
  112. {
  113. #if !defined(CONFIG_SANDBOX) && !defined(CONFIG_EFI_APP)
  114. ulong bss_start, bss_end, text_base;
  115. bss_start = (ulong)&__bss_start;
  116. bss_end = (ulong)&__bss_end;
  117. #ifdef CONFIG_SYS_TEXT_BASE
  118. text_base = CONFIG_SYS_TEXT_BASE;
  119. #else
  120. text_base = CONFIG_SYS_MONITOR_BASE;
  121. #endif
  122. debug("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n",
  123. text_base, bss_start, bss_end);
  124. #endif
  125. return 0;
  126. }
  127. static int announce_dram_init(void)
  128. {
  129. puts("DRAM: ");
  130. return 0;
  131. }
  132. static int show_dram_config(void)
  133. {
  134. unsigned long long size;
  135. #ifdef CONFIG_NR_DRAM_BANKS
  136. int i;
  137. debug("\nRAM Configuration:\n");
  138. for (i = size = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
  139. size += gd->bd->bi_dram[i].size;
  140. debug("Bank #%d: %llx ", i,
  141. (unsigned long long)(gd->bd->bi_dram[i].start));
  142. #ifdef DEBUG
  143. print_size(gd->bd->bi_dram[i].size, "\n");
  144. #endif
  145. }
  146. debug("\nDRAM: ");
  147. #else
  148. size = gd->ram_size;
  149. #endif
  150. print_size(size, "");
  151. board_add_ram_info(0);
  152. putc('\n');
  153. return 0;
  154. }
  155. __weak int dram_init_banksize(void)
  156. {
  157. #if defined(CONFIG_NR_DRAM_BANKS) && defined(CONFIG_SYS_SDRAM_BASE)
  158. gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
  159. gd->bd->bi_dram[0].size = get_effective_memsize();
  160. #endif
  161. return 0;
  162. }
  163. #if defined(CONFIG_SYS_I2C)
  164. static int init_func_i2c(void)
  165. {
  166. puts("I2C: ");
  167. #ifdef CONFIG_SYS_I2C
  168. i2c_init_all();
  169. #else
  170. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  171. #endif
  172. puts("ready\n");
  173. return 0;
  174. }
  175. #endif
  176. #if defined(CONFIG_VID)
  177. __weak int init_func_vid(void)
  178. {
  179. return 0;
  180. }
  181. #endif
  182. #if defined(CONFIG_HARD_SPI)
  183. static int init_func_spi(void)
  184. {
  185. puts("SPI: ");
  186. spi_init();
  187. puts("ready\n");
  188. return 0;
  189. }
  190. #endif
  191. static int setup_mon_len(void)
  192. {
  193. #if defined(__ARM__) || defined(__MICROBLAZE__)
  194. gd->mon_len = (ulong)&__bss_end - (ulong)_start;
  195. #elif defined(CONFIG_SANDBOX) || defined(CONFIG_EFI_APP)
  196. gd->mon_len = (ulong)&_end - (ulong)_init;
  197. #elif defined(CONFIG_NIOS2) || defined(CONFIG_XTENSA)
  198. gd->mon_len = CONFIG_SYS_MONITOR_LEN;
  199. #elif defined(CONFIG_NDS32) || defined(CONFIG_SH) || defined(CONFIG_RISCV)
  200. gd->mon_len = (ulong)(&__bss_end) - (ulong)(&_start);
  201. #elif defined(CONFIG_SYS_MONITOR_BASE)
  202. /* TODO: use (ulong)&__bss_end - (ulong)&__text_start; ? */
  203. gd->mon_len = (ulong)&__bss_end - CONFIG_SYS_MONITOR_BASE;
  204. #endif
  205. return 0;
  206. }
  207. __weak int arch_cpu_init(void)
  208. {
  209. return 0;
  210. }
  211. __weak int mach_cpu_init(void)
  212. {
  213. return 0;
  214. }
  215. /* Get the top of usable RAM */
  216. __weak ulong board_get_usable_ram_top(ulong total_size)
  217. {
  218. #ifdef CONFIG_SYS_SDRAM_BASE
  219. /*
  220. * Detect whether we have so much RAM that it goes past the end of our
  221. * 32-bit address space. If so, clip the usable RAM so it doesn't.
  222. */
  223. if (gd->ram_top < CONFIG_SYS_SDRAM_BASE)
  224. /*
  225. * Will wrap back to top of 32-bit space when reservations
  226. * are made.
  227. */
  228. return 0;
  229. #endif
  230. return gd->ram_top;
  231. }
  232. static int setup_dest_addr(void)
  233. {
  234. debug("Monitor len: %08lX\n", gd->mon_len);
  235. /*
  236. * Ram is setup, size stored in gd !!
  237. */
  238. debug("Ram size: %08lX\n", (ulong)gd->ram_size);
  239. #if defined(CONFIG_SYS_MEM_TOP_HIDE)
  240. /*
  241. * Subtract specified amount of memory to hide so that it won't
  242. * get "touched" at all by U-Boot. By fixing up gd->ram_size
  243. * the Linux kernel should now get passed the now "corrected"
  244. * memory size and won't touch it either. This should work
  245. * for arch/ppc and arch/powerpc. Only Linux board ports in
  246. * arch/powerpc with bootwrapper support, that recalculate the
  247. * memory size from the SDRAM controller setup will have to
  248. * get fixed.
  249. */
  250. gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE;
  251. #endif
  252. #ifdef CONFIG_SYS_SDRAM_BASE
  253. gd->ram_top = CONFIG_SYS_SDRAM_BASE;
  254. #endif
  255. gd->ram_top += get_effective_memsize();
  256. gd->ram_top = board_get_usable_ram_top(gd->mon_len);
  257. gd->relocaddr = gd->ram_top;
  258. debug("Ram top: %08lX\n", (ulong)gd->ram_top);
  259. #if defined(CONFIG_MP) && (defined(CONFIG_MPC86xx) || defined(CONFIG_E500))
  260. /*
  261. * We need to make sure the location we intend to put secondary core
  262. * boot code is reserved and not used by any part of u-boot
  263. */
  264. if (gd->relocaddr > determine_mp_bootpg(NULL)) {
  265. gd->relocaddr = determine_mp_bootpg(NULL);
  266. debug("Reserving MP boot page to %08lx\n", gd->relocaddr);
  267. }
  268. #endif
  269. return 0;
  270. }
  271. #ifdef CONFIG_PRAM
  272. /* reserve protected RAM */
  273. static int reserve_pram(void)
  274. {
  275. ulong reg;
  276. reg = env_get_ulong("pram", 10, CONFIG_PRAM);
  277. gd->relocaddr -= (reg << 10); /* size is in kB */
  278. debug("Reserving %ldk for protected RAM at %08lx\n", reg,
  279. gd->relocaddr);
  280. return 0;
  281. }
  282. #endif /* CONFIG_PRAM */
  283. /* Round memory pointer down to next 4 kB limit */
  284. static int reserve_round_4k(void)
  285. {
  286. gd->relocaddr &= ~(4096 - 1);
  287. return 0;
  288. }
  289. #ifdef CONFIG_ARM
  290. __weak int reserve_mmu(void)
  291. {
  292. #if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
  293. /* reserve TLB table */
  294. gd->arch.tlb_size = PGTABLE_SIZE;
  295. gd->relocaddr -= gd->arch.tlb_size;
  296. /* round down to next 64 kB limit */
  297. gd->relocaddr &= ~(0x10000 - 1);
  298. gd->arch.tlb_addr = gd->relocaddr;
  299. debug("TLB table from %08lx to %08lx\n", gd->arch.tlb_addr,
  300. gd->arch.tlb_addr + gd->arch.tlb_size);
  301. #ifdef CONFIG_SYS_MEM_RESERVE_SECURE
  302. /*
  303. * Record allocated tlb_addr in case gd->tlb_addr to be overwritten
  304. * with location within secure ram.
  305. */
  306. gd->arch.tlb_allocated = gd->arch.tlb_addr;
  307. #endif
  308. #endif
  309. return 0;
  310. }
  311. #endif
  312. static int reserve_video(void)
  313. {
  314. #ifdef CONFIG_DM_VIDEO
  315. ulong addr;
  316. int ret;
  317. addr = gd->relocaddr;
  318. ret = video_reserve(&addr);
  319. if (ret)
  320. return ret;
  321. gd->relocaddr = addr;
  322. #elif defined(CONFIG_LCD)
  323. # ifdef CONFIG_FB_ADDR
  324. gd->fb_base = CONFIG_FB_ADDR;
  325. # else
  326. /* reserve memory for LCD display (always full pages) */
  327. gd->relocaddr = lcd_setmem(gd->relocaddr);
  328. gd->fb_base = gd->relocaddr;
  329. # endif /* CONFIG_FB_ADDR */
  330. #elif defined(CONFIG_VIDEO) && \
  331. (!defined(CONFIG_PPC)) && \
  332. !defined(CONFIG_ARM) && !defined(CONFIG_X86) && \
  333. !defined(CONFIG_M68K)
  334. /* reserve memory for video display (always full pages) */
  335. gd->relocaddr = video_setmem(gd->relocaddr);
  336. gd->fb_base = gd->relocaddr;
  337. #endif
  338. return 0;
  339. }
  340. static int reserve_trace(void)
  341. {
  342. #ifdef CONFIG_TRACE
  343. gd->relocaddr -= CONFIG_TRACE_BUFFER_SIZE;
  344. gd->trace_buff = map_sysmem(gd->relocaddr, CONFIG_TRACE_BUFFER_SIZE);
  345. debug("Reserving %dk for trace data at: %08lx\n",
  346. CONFIG_TRACE_BUFFER_SIZE >> 10, gd->relocaddr);
  347. #endif
  348. return 0;
  349. }
  350. static int reserve_uboot(void)
  351. {
  352. /*
  353. * reserve memory for U-Boot code, data & bss
  354. * round down to next 4 kB limit
  355. */
  356. gd->relocaddr -= gd->mon_len;
  357. gd->relocaddr &= ~(4096 - 1);
  358. #if defined(CONFIG_E500) || defined(CONFIG_MIPS)
  359. /* round down to next 64 kB limit so that IVPR stays aligned */
  360. gd->relocaddr &= ~(65536 - 1);
  361. #endif
  362. debug("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10,
  363. gd->relocaddr);
  364. gd->start_addr_sp = gd->relocaddr;
  365. return 0;
  366. }
  367. /* reserve memory for malloc() area */
  368. static int reserve_malloc(void)
  369. {
  370. gd->start_addr_sp = gd->start_addr_sp - TOTAL_MALLOC_LEN;
  371. debug("Reserving %dk for malloc() at: %08lx\n",
  372. TOTAL_MALLOC_LEN >> 10, gd->start_addr_sp);
  373. return 0;
  374. }
  375. /* (permanently) allocate a Board Info struct */
  376. static int reserve_board(void)
  377. {
  378. if (!gd->bd) {
  379. gd->start_addr_sp -= sizeof(bd_t);
  380. gd->bd = (bd_t *)map_sysmem(gd->start_addr_sp, sizeof(bd_t));
  381. memset(gd->bd, '\0', sizeof(bd_t));
  382. debug("Reserving %zu Bytes for Board Info at: %08lx\n",
  383. sizeof(bd_t), gd->start_addr_sp);
  384. }
  385. return 0;
  386. }
  387. static int setup_machine(void)
  388. {
  389. #ifdef CONFIG_MACH_TYPE
  390. gd->bd->bi_arch_number = CONFIG_MACH_TYPE; /* board id for Linux */
  391. #endif
  392. return 0;
  393. }
  394. static int reserve_global_data(void)
  395. {
  396. gd->start_addr_sp -= sizeof(gd_t);
  397. gd->new_gd = (gd_t *)map_sysmem(gd->start_addr_sp, sizeof(gd_t));
  398. debug("Reserving %zu Bytes for Global Data at: %08lx\n",
  399. sizeof(gd_t), gd->start_addr_sp);
  400. return 0;
  401. }
  402. static int reserve_fdt(void)
  403. {
  404. #ifndef CONFIG_OF_EMBED
  405. /*
  406. * If the device tree is sitting immediately above our image then we
  407. * must relocate it. If it is embedded in the data section, then it
  408. * will be relocated with other data.
  409. */
  410. if (gd->fdt_blob) {
  411. gd->fdt_size = ALIGN(fdt_totalsize(gd->fdt_blob) + 0x1000, 32);
  412. gd->start_addr_sp -= gd->fdt_size;
  413. gd->new_fdt = map_sysmem(gd->start_addr_sp, gd->fdt_size);
  414. debug("Reserving %lu Bytes for FDT at: %08lx\n",
  415. gd->fdt_size, gd->start_addr_sp);
  416. }
  417. #endif
  418. return 0;
  419. }
  420. static int reserve_bootstage(void)
  421. {
  422. #ifdef CONFIG_BOOTSTAGE
  423. int size = bootstage_get_size();
  424. gd->start_addr_sp -= size;
  425. gd->new_bootstage = map_sysmem(gd->start_addr_sp, size);
  426. debug("Reserving %#x Bytes for bootstage at: %08lx\n", size,
  427. gd->start_addr_sp);
  428. #endif
  429. return 0;
  430. }
  431. __weak int arch_reserve_stacks(void)
  432. {
  433. return 0;
  434. }
  435. static int reserve_stacks(void)
  436. {
  437. /* make stack pointer 16-byte aligned */
  438. gd->start_addr_sp -= 16;
  439. gd->start_addr_sp &= ~0xf;
  440. /*
  441. * let the architecture-specific code tailor gd->start_addr_sp and
  442. * gd->irq_sp
  443. */
  444. return arch_reserve_stacks();
  445. }
  446. static int display_new_sp(void)
  447. {
  448. debug("New Stack Pointer is: %08lx\n", gd->start_addr_sp);
  449. return 0;
  450. }
  451. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  452. defined(CONFIG_SH)
  453. static int setup_board_part1(void)
  454. {
  455. bd_t *bd = gd->bd;
  456. /*
  457. * Save local variables to board info struct
  458. */
  459. bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of memory */
  460. bd->bi_memsize = gd->ram_size; /* size in bytes */
  461. #ifdef CONFIG_SYS_SRAM_BASE
  462. bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM */
  463. bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM */
  464. #endif
  465. #if defined(CONFIG_E500) || defined(CONFIG_MPC86xx)
  466. bd->bi_immr_base = CONFIG_SYS_IMMR; /* base of IMMR register */
  467. #endif
  468. #if defined(CONFIG_M68K)
  469. bd->bi_mbar_base = CONFIG_SYS_MBAR; /* base of internal registers */
  470. #endif
  471. #if defined(CONFIG_MPC83xx)
  472. bd->bi_immrbar = CONFIG_SYS_IMMR;
  473. #endif
  474. return 0;
  475. }
  476. #endif
  477. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  478. static int setup_board_part2(void)
  479. {
  480. bd_t *bd = gd->bd;
  481. bd->bi_intfreq = gd->cpu_clk; /* Internal Freq, in Hz */
  482. bd->bi_busfreq = gd->bus_clk; /* Bus Freq, in Hz */
  483. #if defined(CONFIG_CPM2)
  484. bd->bi_cpmfreq = gd->arch.cpm_clk;
  485. bd->bi_brgfreq = gd->arch.brg_clk;
  486. bd->bi_sccfreq = gd->arch.scc_clk;
  487. bd->bi_vco = gd->arch.vco_out;
  488. #endif /* CONFIG_CPM2 */
  489. #if defined(CONFIG_M68K) && defined(CONFIG_PCI)
  490. bd->bi_pcifreq = gd->pci_clk;
  491. #endif
  492. #if defined(CONFIG_EXTRA_CLOCK)
  493. bd->bi_inpfreq = gd->arch.inp_clk; /* input Freq in Hz */
  494. bd->bi_vcofreq = gd->arch.vco_clk; /* vco Freq in Hz */
  495. bd->bi_flbfreq = gd->arch.flb_clk; /* flexbus Freq in Hz */
  496. #endif
  497. return 0;
  498. }
  499. #endif
  500. #ifdef CONFIG_POST
  501. static int init_post(void)
  502. {
  503. post_bootmode_init();
  504. post_run(NULL, POST_ROM | post_bootmode_get(0));
  505. return 0;
  506. }
  507. #endif
  508. static int reloc_fdt(void)
  509. {
  510. #ifndef CONFIG_OF_EMBED
  511. if (gd->flags & GD_FLG_SKIP_RELOC)
  512. return 0;
  513. if (gd->new_fdt) {
  514. memcpy(gd->new_fdt, gd->fdt_blob, gd->fdt_size);
  515. gd->fdt_blob = gd->new_fdt;
  516. }
  517. #endif
  518. return 0;
  519. }
  520. static int reloc_bootstage(void)
  521. {
  522. #ifdef CONFIG_BOOTSTAGE
  523. if (gd->flags & GD_FLG_SKIP_RELOC)
  524. return 0;
  525. if (gd->new_bootstage) {
  526. int size = bootstage_get_size();
  527. debug("Copying bootstage from %p to %p, size %x\n",
  528. gd->bootstage, gd->new_bootstage, size);
  529. memcpy(gd->new_bootstage, gd->bootstage, size);
  530. gd->bootstage = gd->new_bootstage;
  531. }
  532. #endif
  533. return 0;
  534. }
  535. static int setup_reloc(void)
  536. {
  537. if (gd->flags & GD_FLG_SKIP_RELOC) {
  538. debug("Skipping relocation due to flag\n");
  539. return 0;
  540. }
  541. #ifdef CONFIG_SYS_TEXT_BASE
  542. #ifdef ARM
  543. gd->reloc_off = gd->relocaddr - (unsigned long)__image_copy_start;
  544. #elif defined(CONFIG_M68K)
  545. /*
  546. * On all ColdFire arch cpu, monitor code starts always
  547. * just after the default vector table location, so at 0x400
  548. */
  549. gd->reloc_off = gd->relocaddr - (CONFIG_SYS_TEXT_BASE + 0x400);
  550. #else
  551. gd->reloc_off = gd->relocaddr - CONFIG_SYS_TEXT_BASE;
  552. #endif
  553. #endif
  554. memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
  555. debug("Relocation Offset is: %08lx\n", gd->reloc_off);
  556. debug("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
  557. gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
  558. gd->start_addr_sp);
  559. return 0;
  560. }
  561. #ifdef CONFIG_OF_BOARD_FIXUP
  562. static int fix_fdt(void)
  563. {
  564. return board_fix_fdt((void *)gd->fdt_blob);
  565. }
  566. #endif
  567. /* ARM calls relocate_code from its crt0.S */
  568. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  569. !CONFIG_IS_ENABLED(X86_64)
  570. static int jump_to_copy(void)
  571. {
  572. if (gd->flags & GD_FLG_SKIP_RELOC)
  573. return 0;
  574. /*
  575. * x86 is special, but in a nice way. It uses a trampoline which
  576. * enables the dcache if possible.
  577. *
  578. * For now, other archs use relocate_code(), which is implemented
  579. * similarly for all archs. When we do generic relocation, hopefully
  580. * we can make all archs enable the dcache prior to relocation.
  581. */
  582. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  583. /*
  584. * SDRAM and console are now initialised. The final stack can now
  585. * be setup in SDRAM. Code execution will continue in Flash, but
  586. * with the stack in SDRAM and Global Data in temporary memory
  587. * (CPU cache)
  588. */
  589. arch_setup_gd(gd->new_gd);
  590. board_init_f_r_trampoline(gd->start_addr_sp);
  591. #else
  592. relocate_code(gd->start_addr_sp, gd->new_gd, gd->relocaddr);
  593. #endif
  594. return 0;
  595. }
  596. #endif
  597. /* Record the board_init_f() bootstage (after arch_cpu_init()) */
  598. static int initf_bootstage(void)
  599. {
  600. bool from_spl = IS_ENABLED(CONFIG_SPL_BOOTSTAGE) &&
  601. IS_ENABLED(CONFIG_BOOTSTAGE_STASH);
  602. int ret;
  603. ret = bootstage_init(!from_spl);
  604. if (ret)
  605. return ret;
  606. if (from_spl) {
  607. const void *stash = map_sysmem(CONFIG_BOOTSTAGE_STASH_ADDR,
  608. CONFIG_BOOTSTAGE_STASH_SIZE);
  609. ret = bootstage_unstash(stash, CONFIG_BOOTSTAGE_STASH_SIZE);
  610. if (ret && ret != -ENOENT) {
  611. debug("Failed to unstash bootstage: err=%d\n", ret);
  612. return ret;
  613. }
  614. }
  615. bootstage_mark_name(BOOTSTAGE_ID_START_UBOOT_F, "board_init_f");
  616. return 0;
  617. }
  618. static int initf_console_record(void)
  619. {
  620. #if defined(CONFIG_CONSOLE_RECORD) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  621. return console_record_init();
  622. #else
  623. return 0;
  624. #endif
  625. }
  626. static int initf_dm(void)
  627. {
  628. #if defined(CONFIG_DM) && CONFIG_VAL(SYS_MALLOC_F_LEN)
  629. int ret;
  630. bootstage_start(BOOTSTATE_ID_ACCUM_DM_F, "dm_f");
  631. ret = dm_init_and_scan(true);
  632. bootstage_accum(BOOTSTATE_ID_ACCUM_DM_F);
  633. if (ret)
  634. return ret;
  635. #endif
  636. #ifdef CONFIG_TIMER_EARLY
  637. ret = dm_timer_init();
  638. if (ret)
  639. return ret;
  640. #endif
  641. return 0;
  642. }
  643. /* Architecture-specific memory reservation */
  644. __weak int reserve_arch(void)
  645. {
  646. return 0;
  647. }
  648. __weak int arch_cpu_init_dm(void)
  649. {
  650. return 0;
  651. }
  652. static const init_fnc_t init_sequence_f[] = {
  653. setup_mon_len,
  654. #ifdef CONFIG_OF_CONTROL
  655. fdtdec_setup,
  656. #endif
  657. #ifdef CONFIG_TRACE
  658. trace_early_init,
  659. #endif
  660. initf_malloc,
  661. log_init,
  662. initf_bootstage, /* uses its own timer, so does not need DM */
  663. initf_console_record,
  664. #if defined(CONFIG_HAVE_FSP)
  665. arch_fsp_init,
  666. #endif
  667. arch_cpu_init, /* basic arch cpu dependent setup */
  668. mach_cpu_init, /* SoC/machine dependent CPU setup */
  669. initf_dm,
  670. arch_cpu_init_dm,
  671. #if defined(CONFIG_BOARD_EARLY_INIT_F)
  672. board_early_init_f,
  673. #endif
  674. #if defined(CONFIG_PPC) || defined(CONFIG_SYS_FSL_CLK) || defined(CONFIG_M68K)
  675. /* get CPU and bus clocks according to the environment variable */
  676. get_clocks, /* get CPU and bus clocks (etc.) */
  677. #endif
  678. #if !defined(CONFIG_M68K)
  679. timer_init, /* initialize timer */
  680. #endif
  681. #if defined(CONFIG_BOARD_POSTCLK_INIT)
  682. board_postclk_init,
  683. #endif
  684. env_init, /* initialize environment */
  685. init_baud_rate, /* initialze baudrate settings */
  686. serial_init, /* serial communications setup */
  687. console_init_f, /* stage 1 init of console */
  688. display_options, /* say that we are here */
  689. display_text_info, /* show debugging info if required */
  690. #if defined(CONFIG_PPC) || defined(CONFIG_SH) || defined(CONFIG_X86)
  691. checkcpu,
  692. #endif
  693. #if defined(CONFIG_DISPLAY_CPUINFO)
  694. print_cpuinfo, /* display cpu info (and speed) */
  695. #endif
  696. #if defined(CONFIG_DTB_RESELECT)
  697. embedded_dtb_select,
  698. #endif
  699. #if defined(CONFIG_DISPLAY_BOARDINFO)
  700. show_board_info,
  701. #endif
  702. INIT_FUNC_WATCHDOG_INIT
  703. #if defined(CONFIG_MISC_INIT_F)
  704. misc_init_f,
  705. #endif
  706. INIT_FUNC_WATCHDOG_RESET
  707. #if defined(CONFIG_SYS_I2C)
  708. init_func_i2c,
  709. #endif
  710. #if defined(CONFIG_VID) && !defined(CONFIG_SPL)
  711. init_func_vid,
  712. #endif
  713. #if defined(CONFIG_HARD_SPI)
  714. init_func_spi,
  715. #endif
  716. announce_dram_init,
  717. dram_init, /* configure available RAM banks */
  718. #ifdef CONFIG_POST
  719. post_init_f,
  720. #endif
  721. INIT_FUNC_WATCHDOG_RESET
  722. #if defined(CONFIG_SYS_DRAM_TEST)
  723. testdram,
  724. #endif /* CONFIG_SYS_DRAM_TEST */
  725. INIT_FUNC_WATCHDOG_RESET
  726. #ifdef CONFIG_POST
  727. init_post,
  728. #endif
  729. INIT_FUNC_WATCHDOG_RESET
  730. /*
  731. * Now that we have DRAM mapped and working, we can
  732. * relocate the code and continue running from DRAM.
  733. *
  734. * Reserve memory at end of RAM for (top down in that order):
  735. * - area that won't get touched by U-Boot and Linux (optional)
  736. * - kernel log buffer
  737. * - protected RAM
  738. * - LCD framebuffer
  739. * - monitor code
  740. * - board info struct
  741. */
  742. setup_dest_addr,
  743. #ifdef CONFIG_PRAM
  744. reserve_pram,
  745. #endif
  746. reserve_round_4k,
  747. #ifdef CONFIG_ARM
  748. reserve_mmu,
  749. #endif
  750. reserve_video,
  751. reserve_trace,
  752. reserve_uboot,
  753. reserve_malloc,
  754. reserve_board,
  755. setup_machine,
  756. reserve_global_data,
  757. reserve_fdt,
  758. reserve_bootstage,
  759. reserve_arch,
  760. reserve_stacks,
  761. dram_init_banksize,
  762. show_dram_config,
  763. #if defined(CONFIG_M68K) || defined(CONFIG_MIPS) || defined(CONFIG_PPC) || \
  764. defined(CONFIG_SH)
  765. setup_board_part1,
  766. #endif
  767. #if defined(CONFIG_PPC) || defined(CONFIG_M68K)
  768. INIT_FUNC_WATCHDOG_RESET
  769. setup_board_part2,
  770. #endif
  771. display_new_sp,
  772. #ifdef CONFIG_OF_BOARD_FIXUP
  773. fix_fdt,
  774. #endif
  775. INIT_FUNC_WATCHDOG_RESET
  776. reloc_fdt,
  777. reloc_bootstage,
  778. setup_reloc,
  779. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  780. copy_uboot_to_ram,
  781. do_elf_reloc_fixups,
  782. clear_bss,
  783. #endif
  784. #if defined(CONFIG_XTENSA)
  785. clear_bss,
  786. #endif
  787. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  788. !CONFIG_IS_ENABLED(X86_64)
  789. jump_to_copy,
  790. #endif
  791. NULL,
  792. };
  793. void board_init_f(ulong boot_flags)
  794. {
  795. gd->flags = boot_flags;
  796. gd->have_console = 0;
  797. if (initcall_run_list(init_sequence_f))
  798. hang();
  799. #if !defined(CONFIG_ARM) && !defined(CONFIG_SANDBOX) && \
  800. !defined(CONFIG_EFI_APP) && !CONFIG_IS_ENABLED(X86_64) && \
  801. !defined(CONFIG_ARC)
  802. /* NOTREACHED - jump_to_copy() does not return */
  803. hang();
  804. #endif
  805. }
  806. #if defined(CONFIG_X86) || defined(CONFIG_ARC)
  807. /*
  808. * For now this code is only used on x86.
  809. *
  810. * init_sequence_f_r is the list of init functions which are run when
  811. * U-Boot is executing from Flash with a semi-limited 'C' environment.
  812. * The following limitations must be considered when implementing an
  813. * '_f_r' function:
  814. * - 'static' variables are read-only
  815. * - Global Data (gd->xxx) is read/write
  816. *
  817. * The '_f_r' sequence must, as a minimum, copy U-Boot to RAM (if
  818. * supported). It _should_, if possible, copy global data to RAM and
  819. * initialise the CPU caches (to speed up the relocation process)
  820. *
  821. * NOTE: At present only x86 uses this route, but it is intended that
  822. * all archs will move to this when generic relocation is implemented.
  823. */
  824. static const init_fnc_t init_sequence_f_r[] = {
  825. #if !CONFIG_IS_ENABLED(X86_64)
  826. init_cache_f_r,
  827. #endif
  828. NULL,
  829. };
  830. void board_init_f_r(void)
  831. {
  832. if (initcall_run_list(init_sequence_f_r))
  833. hang();
  834. /*
  835. * The pre-relocation drivers may be using memory that has now gone
  836. * away. Mark serial as unavailable - this will fall back to the debug
  837. * UART if available.
  838. *
  839. * Do the same with log drivers since the memory may not be available.
  840. */
  841. gd->flags &= ~(GD_FLG_SERIAL_READY | GD_FLG_LOG_READY);
  842. #ifdef CONFIG_TIMER
  843. gd->timer = NULL;
  844. #endif
  845. /*
  846. * U-Boot has been copied into SDRAM, the BSS has been cleared etc.
  847. * Transfer execution from Flash to RAM by calculating the address
  848. * of the in-RAM copy of board_init_r() and calling it
  849. */
  850. (board_init_r + gd->reloc_off)((gd_t *)gd, gd->relocaddr);
  851. /* NOTREACHED - board_init_r() does not return */
  852. hang();
  853. }
  854. #endif /* CONFIG_X86 */