board.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2012 Michal Simek <monstr@monstr.eu>
  4. * (C) Copyright 2013 - 2018 Xilinx, Inc.
  5. */
  6. #include <common.h>
  7. #include <dm/uclass.h>
  8. #include <fdtdec.h>
  9. #include <fpga.h>
  10. #include <mmc.h>
  11. #include <wdt.h>
  12. #include <zynqpl.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <asm/arch/ps7_init_gpl.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  18. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  19. static xilinx_desc fpga;
  20. /* It can be done differently */
  21. static xilinx_desc fpga007s = XILINX_XC7Z007S_DESC(0x7);
  22. static xilinx_desc fpga010 = XILINX_XC7Z010_DESC(0x10);
  23. static xilinx_desc fpga012s = XILINX_XC7Z012S_DESC(0x12);
  24. static xilinx_desc fpga014s = XILINX_XC7Z014S_DESC(0x14);
  25. static xilinx_desc fpga015 = XILINX_XC7Z015_DESC(0x15);
  26. static xilinx_desc fpga020 = XILINX_XC7Z020_DESC(0x20);
  27. static xilinx_desc fpga030 = XILINX_XC7Z030_DESC(0x30);
  28. static xilinx_desc fpga035 = XILINX_XC7Z035_DESC(0x35);
  29. static xilinx_desc fpga045 = XILINX_XC7Z045_DESC(0x45);
  30. static xilinx_desc fpga100 = XILINX_XC7Z100_DESC(0x100);
  31. #endif
  32. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  33. static struct udevice *watchdog_dev;
  34. #endif
  35. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_BOARD_EARLY_INIT_F)
  36. int board_early_init_f(void)
  37. {
  38. # if defined(CONFIG_WDT)
  39. /* bss is not cleared at time when watchdog_reset() is called */
  40. watchdog_dev = NULL;
  41. # endif
  42. return 0;
  43. }
  44. #endif
  45. int board_init(void)
  46. {
  47. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  48. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  49. u32 idcode;
  50. idcode = zynq_slcr_get_idcode();
  51. switch (idcode) {
  52. case XILINX_ZYNQ_7007S:
  53. fpga = fpga007s;
  54. break;
  55. case XILINX_ZYNQ_7010:
  56. fpga = fpga010;
  57. break;
  58. case XILINX_ZYNQ_7012S:
  59. fpga = fpga012s;
  60. break;
  61. case XILINX_ZYNQ_7014S:
  62. fpga = fpga014s;
  63. break;
  64. case XILINX_ZYNQ_7015:
  65. fpga = fpga015;
  66. break;
  67. case XILINX_ZYNQ_7020:
  68. fpga = fpga020;
  69. break;
  70. case XILINX_ZYNQ_7030:
  71. fpga = fpga030;
  72. break;
  73. case XILINX_ZYNQ_7035:
  74. fpga = fpga035;
  75. break;
  76. case XILINX_ZYNQ_7045:
  77. fpga = fpga045;
  78. break;
  79. case XILINX_ZYNQ_7100:
  80. fpga = fpga100;
  81. break;
  82. }
  83. #endif
  84. #if !defined(CONFIG_SPL_BUILD) && defined(CONFIG_WDT)
  85. if (uclass_get_device(UCLASS_WDT, 0, &watchdog_dev)) {
  86. puts("Watchdog: Not found!\n");
  87. } else {
  88. wdt_start(watchdog_dev, 0, 0);
  89. puts("Watchdog: Started\n");
  90. }
  91. # endif
  92. #if (defined(CONFIG_FPGA) && !defined(CONFIG_SPL_BUILD)) || \
  93. (defined(CONFIG_SPL_FPGA_SUPPORT) && defined(CONFIG_SPL_BUILD))
  94. fpga_init();
  95. fpga_add(fpga_xilinx, &fpga);
  96. #endif
  97. return 0;
  98. }
  99. int board_late_init(void)
  100. {
  101. switch ((zynq_slcr_get_boot_mode()) & ZYNQ_BM_MASK) {
  102. case ZYNQ_BM_QSPI:
  103. env_set("modeboot", "qspiboot");
  104. break;
  105. case ZYNQ_BM_NAND:
  106. env_set("modeboot", "nandboot");
  107. break;
  108. case ZYNQ_BM_NOR:
  109. env_set("modeboot", "norboot");
  110. break;
  111. case ZYNQ_BM_SD:
  112. env_set("modeboot", "sdboot");
  113. break;
  114. case ZYNQ_BM_JTAG:
  115. env_set("modeboot", "jtagboot");
  116. break;
  117. default:
  118. env_set("modeboot", "");
  119. break;
  120. }
  121. return 0;
  122. }
  123. #ifdef CONFIG_DISPLAY_BOARDINFO
  124. int checkboard(void)
  125. {
  126. u32 version = zynq_get_silicon_version();
  127. version <<= 1;
  128. if (version > (PCW_SILICON_VERSION_3 << 1))
  129. version += 1;
  130. puts("Board: Xilinx Zynq\n");
  131. printf("Silicon: v%d.%d\n", version >> 1, version & 1);
  132. return 0;
  133. }
  134. #endif
  135. int zynq_board_read_rom_ethaddr(unsigned char *ethaddr)
  136. {
  137. #if defined(CONFIG_ZYNQ_GEM_EEPROM_ADDR) && \
  138. defined(CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET)
  139. if (eeprom_read(CONFIG_ZYNQ_GEM_EEPROM_ADDR,
  140. CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET,
  141. ethaddr, 6))
  142. printf("I2C EEPROM MAC address read failed\n");
  143. #endif
  144. return 0;
  145. }
  146. #if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE)
  147. int dram_init_banksize(void)
  148. {
  149. return fdtdec_setup_memory_banksize();
  150. }
  151. int dram_init(void)
  152. {
  153. if (fdtdec_setup_memory_size() != 0)
  154. return -EINVAL;
  155. zynq_ddrc_init();
  156. return 0;
  157. }
  158. #else
  159. int dram_init(void)
  160. {
  161. gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
  162. CONFIG_SYS_SDRAM_SIZE);
  163. zynq_ddrc_init();
  164. return 0;
  165. }
  166. #endif
  167. #if defined(CONFIG_WATCHDOG)
  168. /* Called by macro WATCHDOG_RESET */
  169. void watchdog_reset(void)
  170. {
  171. # if !defined(CONFIG_SPL_BUILD)
  172. static ulong next_reset;
  173. ulong now;
  174. if (!watchdog_dev)
  175. return;
  176. now = timer_get_us();
  177. /* Do not reset the watchdog too often */
  178. if (now > next_reset) {
  179. wdt_reset(watchdog_dev);
  180. next_reset = now + 1000;
  181. }
  182. # endif
  183. }
  184. #endif