qts-filter.sh 10 KB

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  1. #!/bin/sh
  2. #
  3. # helper function to convert from DOS to Unix, if necessary, and handle
  4. # lines ending in '\'.
  5. #
  6. fix_newlines_in_macros() {
  7. sed -n ':next;s/\r$//;/[^\\]\\$/ {N;s/\\\n//;b next};p' $1
  8. }
  9. #
  10. # Process iocsr_config_*.[ch]
  11. # $1: SoC type
  12. # $2: Input handoff directory
  13. # $3: Input BSP Generated directory
  14. # $4: Output directory
  15. #
  16. process_iocsr_config() {
  17. soc="$1"
  18. in_qts_dir="$2"
  19. in_bsp_dir="$3"
  20. out_dir="$4"
  21. (
  22. cat << EOF
  23. /* SPDX-License-Identifier: BSD-3-Clause */
  24. /*
  25. * Altera SoCFPGA IOCSR configuration
  26. */
  27. #ifndef __SOCFPGA_IOCSR_CONFIG_H__
  28. #define __SOCFPGA_IOCSR_CONFIG_H__
  29. EOF
  30. # Retrieve the scan chain lengths
  31. fix_newlines_in_macros \
  32. ${in_bsp_dir}/generated/iocsr_config_${soc}.h |
  33. grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]\+_LENGTH' | tr -d "()"
  34. echo ""
  35. # Retrieve the scan chain config and zap the ad-hoc length encoding
  36. fix_newlines_in_macros \
  37. ${in_bsp_dir}/generated/iocsr_config_${soc}.c |
  38. sed -n '/^const/ !b; :next {/^const/ s/(.*)//;p;n;b next}'
  39. cat << EOF
  40. #endif /* __SOCFPGA_IOCSR_CONFIG_H__ */
  41. EOF
  42. ) > "${out_dir}/iocsr_config.h"
  43. }
  44. #
  45. # Process pinmux_config_*.c (and ignore pinmux_config.h)
  46. # $1: SoC type
  47. # $2: Input directory
  48. # $3: Output directory
  49. #
  50. process_pinmux_config() {
  51. soc="$1"
  52. in_qts_dir="$2"
  53. in_bsp_dir="$3"
  54. out_dir="$4"
  55. (
  56. cat << EOF
  57. /* SPDX-License-Identifier: BSD-3-Clause */
  58. /*
  59. * Altera SoCFPGA PinMux configuration
  60. */
  61. #ifndef __SOCFPGA_PINMUX_CONFIG_H__
  62. #define __SOCFPGA_PINMUX_CONFIG_H__
  63. EOF
  64. # Retrieve the pinmux config and zap the ad-hoc length encoding
  65. fix_newlines_in_macros \
  66. ${in_bsp_dir}/generated/pinmux_config_${soc}.c |
  67. sed -n '/^unsigned/ !b; :next {/^unsigned/ {s/\[.*\]/[]/;s/unsigned long/const u8/};p;n;b next}'
  68. cat << EOF
  69. #endif /* __SOCFPGA_PINMUX_CONFIG_H__ */
  70. EOF
  71. ) > "${out_dir}/pinmux_config.h"
  72. }
  73. #
  74. # Process pll_config.h
  75. # $1: SoC type (not used)
  76. # $2: Input directory
  77. # $3: Output directory
  78. #
  79. process_pll_config() {
  80. soc="$1"
  81. in_qts_dir="$2"
  82. in_bsp_dir="$3"
  83. out_dir="$4"
  84. (
  85. cat << EOF
  86. /* SPDX-License-Identifier: BSD-3-Clause */
  87. /*
  88. * Altera SoCFPGA Clock and PLL configuration
  89. */
  90. #ifndef __SOCFPGA_PLL_CONFIG_H__
  91. #define __SOCFPGA_PLL_CONFIG_H__
  92. EOF
  93. # Retrieve the pll config and zap parenthesis
  94. fix_newlines_in_macros \
  95. ${in_bsp_dir}/generated/pll_config.h |
  96. sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}'
  97. cat << EOF
  98. #endif /* __SOCFPGA_PLL_CONFIG_H__ */
  99. EOF
  100. ) > "${out_dir}/pll_config.h"
  101. }
  102. #
  103. # Filter out only the macros which are actually used by the code
  104. #
  105. grep_sdram_config() {
  106. egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]"
  107. }
  108. #
  109. # Process sdram_config.h, sequencer_auto*h and sequencer_defines.h
  110. # $1: SoC type (not used)
  111. # $2: Input directory
  112. # $3: Output directory
  113. #
  114. process_sdram_config() {
  115. soc="$1"
  116. in_qts_dir="$2"
  117. in_bsp_dir="$3"
  118. out_dir="$4"
  119. (
  120. cat << EOF
  121. /* SPDX-License-Identifier: BSD-3-Clause */
  122. /*
  123. * Altera SoCFPGA SDRAM configuration
  124. *
  125. */
  126. #ifndef __SOCFPGA_SDRAM_CONFIG_H__
  127. #define __SOCFPGA_SDRAM_CONFIG_H__
  128. EOF
  129. echo "/* SDRAM configuration */"
  130. # Retrieve the sdram config, zap broken lines and zap parenthesis
  131. fix_newlines_in_macros \
  132. ${in_bsp_dir}/generated/sdram/sdram_config.h |
  133. sed -n "/\\\\$/ {N;s/ \\\\\n/\t/};p" |
  134. sed -n '/CONFIG_HPS/ !b; :next {/CONFIG_HPS/ s/[()]//g;/endif/ b;p;n;b next}' |
  135. sort -u | grep_sdram_config
  136. echo ""
  137. echo "/* Sequencer auto configuration */"
  138. fix_newlines_in_macros \
  139. ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto.h |
  140. sed -n "/__RW_MGR/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
  141. sort -u | grep_sdram_config
  142. echo ""
  143. echo "/* Sequencer defines configuration */"
  144. fix_newlines_in_macros \
  145. ${in_qts_dir}/hps_isw_handoff/*/sequencer_defines.h |
  146. sed -n "/^#define [^_]/ {s/__//;s/ \+\([^ ]\+\)$/\t\1/p}" |
  147. sort -u | grep_sdram_config
  148. echo ""
  149. echo "/* Sequencer ac_rom_init configuration */"
  150. fix_newlines_in_macros \
  151. ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_ac_init.c |
  152. sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
  153. echo ""
  154. echo "/* Sequencer inst_rom_init configuration */"
  155. fix_newlines_in_macros \
  156. ${in_qts_dir}/hps_isw_handoff/*/sequencer_auto_inst_init.c |
  157. sed -n '/^const.*\[/ !b; :next {/^const.*\[/ {N;s/\n//;s/alt_u32/u32/;s/\[.*\]/[]/};/endif/ b;p;n;b next}'
  158. cat << EOF
  159. #endif /* __SOCFPGA_SDRAM_CONFIG_H__ */
  160. EOF
  161. ) > "${out_dir}/sdram_config.h"
  162. }
  163. usage() {
  164. echo "$0 [soc_type] [input_qts_dir] [input_bsp_dir] [output_dir]"
  165. echo "Process QTS-generated headers into U-Boot compatible ones."
  166. echo ""
  167. echo " soc_type - Type of SoC, either 'cyclone5' or 'arria5'."
  168. echo " input_qts_dir - Directory with compiled Quartus project"
  169. echo " and containing the Quartus project file (QPF)."
  170. echo " input_bsp_dir - Directory with generated bsp containing"
  171. echo " the settings.bsp file."
  172. echo " output_dir - Directory to store the U-Boot compatible"
  173. echo " headers."
  174. echo ""
  175. }
  176. soc="$1"
  177. in_qts_dir="$2"
  178. in_bsp_dir="$3"
  179. out_dir="$4"
  180. if [ "$#" -ne 4 ] ; then
  181. usage
  182. exit 1
  183. fi
  184. if [ ! -d "${in_qts_dir}" -o ! -d "${in_bsp_dir}" -o \
  185. ! -d "${out_dir}" -o -z "${soc}" ] ; then
  186. usage
  187. exit 3
  188. fi
  189. process_iocsr_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
  190. process_pinmux_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
  191. process_pll_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"
  192. process_sdram_config "${soc}" "${in_qts_dir}" "${in_bsp_dir}" "${out_dir}"