pfc-r8a7791.c 37 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * arch/arm/cpu/armv7/rmobile/pfc-r8a7791.c
  4. *
  5. * Copyright (C) 2013 Renesas Electronics Corporation
  6. */
  7. #include <common.h>
  8. #include <sh_pfc.h>
  9. #include <asm/gpio.h>
  10. #include "pfc-r8a7790.h"
  11. enum {
  12. PINMUX_RESERVED = 0,
  13. PINMUX_DATA_BEGIN,
  14. GP_ALL(DATA),
  15. PINMUX_DATA_END,
  16. PINMUX_INPUT_BEGIN,
  17. GP_ALL(IN),
  18. PINMUX_INPUT_END,
  19. PINMUX_OUTPUT_BEGIN,
  20. GP_ALL(OUT),
  21. PINMUX_OUTPUT_END,
  22. PINMUX_FUNCTION_BEGIN,
  23. GP_ALL(FN),
  24. /* GPSR0 */
  25. FN_IP0_0, FN_IP0_1, FN_IP0_2, FN_IP0_3, FN_IP0_4, FN_IP0_5,
  26. FN_IP0_6, FN_IP0_7, FN_IP0_8, FN_IP0_9, FN_IP0_10, FN_IP0_11,
  27. FN_IP0_12, FN_IP0_13, FN_IP0_14, FN_IP0_15, FN_IP0_18_16, FN_IP0_20_19,
  28. FN_IP0_22_21, FN_IP0_24_23, FN_IP0_26_25, FN_IP0_28_27, FN_IP0_30_29,
  29. FN_IP1_1_0, FN_IP1_3_2, FN_IP1_5_4, FN_IP1_7_6, FN_IP1_10_8,
  30. FN_IP1_13_11, FN_IP1_16_14, FN_IP1_19_17, FN_IP1_22_20,
  31. /* GPSR1 */
  32. FN_IP1_25_23, FN_IP1_28_26, FN_IP1_31_29, FN_IP2_2_0, FN_IP2_4_3,
  33. FN_IP2_6_5, FN_IP2_9_7, FN_IP2_12_10, FN_IP2_15_13, FN_IP2_18_16,
  34. FN_IP2_20_19, FN_IP2_22_21, FN_EX_CS0_N, FN_IP2_24_23, FN_IP2_26_25,
  35. FN_IP2_29_27, FN_IP3_2_0, FN_IP3_5_3, FN_IP3_8_6, FN_RD_N,
  36. FN_IP3_11_9, FN_IP3_13_12, FN_IP3_15_14 , FN_IP3_17_16 , FN_IP3_19_18,
  37. FN_IP3_21_20,
  38. /* GPSR2 */
  39. FN_IP3_27_25, FN_IP3_30_28, FN_IP4_1_0, FN_IP4_4_2, FN_IP4_7_5,
  40. FN_IP4_9_8, FN_IP4_12_10, FN_IP4_15_13, FN_IP4_18_16, FN_IP4_19,
  41. FN_IP4_20, FN_IP4_21, FN_IP4_23_22, FN_IP4_25_24, FN_IP4_27_26,
  42. FN_IP4_30_28, FN_IP5_2_0, FN_IP5_5_3, FN_IP5_8_6, FN_IP5_11_9,
  43. FN_IP5_14_12, FN_IP5_16_15, FN_IP5_19_17, FN_IP5_21_20, FN_IP5_23_22,
  44. FN_IP5_25_24, FN_IP5_28_26, FN_IP5_31_29, FN_AUDIO_CLKA, FN_IP6_2_0,
  45. FN_IP6_5_3, FN_IP6_7_6,
  46. /* GPSR3 */
  47. FN_IP7_5_3, FN_IP7_8_6, FN_IP7_10_9, FN_IP7_12_11, FN_IP7_14_13,
  48. FN_IP7_16_15, FN_IP7_18_17, FN_IP7_20_19, FN_IP7_23_21, FN_IP7_26_24,
  49. FN_IP7_29_27, FN_IP8_2_0, FN_IP8_5_3, FN_IP8_8_6, FN_IP8_11_9,
  50. FN_IP8_14_12, FN_IP8_17_15, FN_IP8_20_18, FN_IP8_23_21, FN_IP8_25_24,
  51. FN_IP8_27_26, FN_IP8_30_28, FN_IP9_2_0, FN_IP9_5_3, FN_IP9_6, FN_IP9_7,
  52. FN_IP9_10_8, FN_IP9_11, FN_IP9_12, FN_IP9_15_13, FN_IP9_16,
  53. FN_IP9_18_17,
  54. /* GPSR4 */
  55. FN_VI0_CLK, FN_IP9_20_19, FN_IP9_22_21, FN_IP9_24_23, FN_IP9_26_25,
  56. FN_VI0_DATA0_VI0_B0, FN_VI0_DATA0_VI0_B1, FN_VI0_DATA0_VI0_B2,
  57. FN_IP9_28_27, FN_VI0_DATA0_VI0_B4, FN_VI0_DATA0_VI0_B5,
  58. FN_VI0_DATA0_VI0_B6, FN_VI0_DATA0_VI0_B7, FN_IP9_31_29, FN_IP10_2_0,
  59. FN_IP10_5_3, FN_IP10_8_6, FN_IP10_11_9, FN_IP10_14_12, FN_IP10_16_15,
  60. FN_IP10_18_17, FN_IP10_21_19, FN_IP10_24_22, FN_IP10_26_25,
  61. FN_IP10_28_27, FN_IP10_31_29, FN_IP11_2_0, FN_IP11_5_3, FN_IP11_8_6,
  62. FN_IP15_1_0, FN_IP15_3_2, FN_IP15_5_4,
  63. /* GPSR5 */
  64. FN_IP11_11_9, FN_IP11_14_12, FN_IP11_16_15, FN_IP11_18_17, FN_IP11_19,
  65. FN_IP11_20, FN_IP11_21, FN_IP11_22, FN_IP11_23, FN_IP11_24,
  66. FN_IP11_25, FN_IP11_26, FN_IP11_27, FN_IP11_29_28, FN_IP11_31_30,
  67. FN_IP12_1_0, FN_IP12_3_2, FN_IP12_6_4, FN_IP12_9_7, FN_IP12_12_10,
  68. FN_IP12_15_13, FN_IP12_17_16, FN_IP12_19_18, FN_IP12_21_20,
  69. FN_IP12_23_22, FN_IP12_26_24, FN_IP12_29_27, FN_IP13_2_0, FN_IP13_4_3,
  70. FN_IP13_6_5, FN_IP13_9_7, FN_IP3_24_22,
  71. /* GPSR6 */
  72. FN_IP13_10, FN_IP13_11, FN_IP13_12, FN_IP13_13, FN_IP13_14,
  73. FN_IP13_15, FN_IP13_18_16, FN_IP13_21_19, FN_IP13_22, FN_IP13_24_23,
  74. FN_IP13_25, FN_IP13_26, FN_IP13_27, FN_IP13_30_28, FN_IP14_1_0,
  75. FN_IP14_2, FN_IP14_3, FN_IP14_4, FN_IP14_5, FN_IP14_6, FN_IP14_7,
  76. FN_IP14_10_8, FN_IP14_13_11, FN_IP14_16_14, FN_IP14_19_17,
  77. FN_IP14_22_20, FN_IP14_25_23, FN_IP14_28_26, FN_IP14_31_29,
  78. /* GPSR7 */
  79. FN_IP15_17_15, FN_IP15_20_18, FN_IP15_23_21, FN_IP15_26_24,
  80. FN_IP15_29_27, FN_IP16_2_0, FN_IP16_5_3, FN_IP16_7_6, FN_IP16_9_8,
  81. FN_IP16_11_10, FN_IP6_9_8, FN_IP6_11_10, FN_IP6_13_12, FN_IP6_15_14,
  82. FN_IP6_18_16, FN_IP6_20_19, FN_IP6_23_21, FN_IP6_26_24, FN_IP6_29_27,
  83. FN_IP7_2_0, FN_IP15_8_6, FN_IP15_11_9, FN_IP15_14_12,
  84. FN_USB0_PWEN, FN_USB0_OVC, FN_USB1_PWEN,
  85. /* IPSR0 - IPSR10 */
  86. /* IPSR11 */
  87. FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
  88. FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
  89. FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
  90. FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D,
  91. FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B, FN_TX4_B, FN_SCIFA4_TXD_B,
  92. FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B, FN_RX4_B, FN_SCIFA4_RXD_B,
  93. FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B,
  94. FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B,
  95. FN_VI1_CLK, FN_AVB_RXD4, FN_VI1_DATA0, FN_AVB_RXD5,
  96. FN_VI1_DATA1, FN_AVB_RXD6, FN_VI1_DATA2, FN_AVB_RXD7,
  97. FN_VI1_DATA3, FN_AVB_RX_ER, FN_VI1_DATA4, FN_AVB_MDIO,
  98. FN_VI1_DATA5, FN_AVB_RX_DV, FN_VI1_DATA6, FN_AVB_MAGIC,
  99. FN_VI1_DATA7, FN_AVB_MDC,
  100. FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C,
  101. FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C,
  102. /* IPSR12 */
  103. FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7,
  104. FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
  105. FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
  106. FN_SCL2_D, FN_MSIOF1_RXD_E,
  107. FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C, FN_SDA2_D, FN_MSIOF1_SCK_E,
  108. FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
  109. FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
  110. FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
  111. FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
  112. FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
  113. FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C,
  114. FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C,
  115. FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C,
  116. FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
  117. FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
  118. FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
  119. FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
  120. /* IPSR13 */
  121. /* MOD_SEL */
  122. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
  123. FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
  124. FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1, FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
  125. FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1, FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
  126. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2,
  127. FN_SEL_SSI9_0, FN_SEL_SSI9_1,
  128. FN_SEL_SCFA_0, FN_SEL_SCFA_1,
  129. FN_SEL_QSP_0, FN_SEL_QSP_1,
  130. FN_SEL_SSI7_0, FN_SEL_SSI7_1,
  131. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2, FN_SEL_HSCIF1_3,
  132. FN_SEL_HSCIF1_4,
  133. FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2,
  134. FN_SEL_TMU1_0, FN_SEL_TMU1_1,
  135. FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
  136. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  137. FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2,
  138. /* MOD_SEL2 */
  139. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2, FN_SEL_SCIF0_3,
  140. FN_SEL_SCIF0_4,
  141. FN_SEL_SCIF_0, FN_SEL_SCIF_1,
  142. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  143. FN_SEL_CAN0_4, FN_SEL_CAN0_5,
  144. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  145. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
  146. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2,
  147. FN_SEL_ADG_0, FN_SEL_ADG_1,
  148. FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2, FN_SEL_FM_3, FN_SEL_FM_4,
  149. FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2,
  150. FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
  151. FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2,
  152. FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2,
  153. FN_SEL_SIM_0, FN_SEL_SIM_1,
  154. FN_SEL_SSI8_0, FN_SEL_SSI8_1,
  155. /* MOD_SEL3 */
  156. FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1, FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
  157. FN_SEL_CANCLK_0, FN_SEL_CANCLK_1, FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
  158. FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2,
  159. FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2,
  160. FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2,
  161. FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
  162. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
  163. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2,
  164. FN_SEL_MMC_0, FN_SEL_MMC_1,
  165. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
  166. FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
  167. FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
  168. FN_SEL_IIC1_4,
  169. FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2,
  170. /* MOD_SEL4 */
  171. FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
  172. FN_SEL_SOF1_4,
  173. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2,
  174. FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2,
  175. FN_SEL_RAD_0, FN_SEL_RAD_1,
  176. FN_SEL_RCN_0, FN_SEL_RCN_1,
  177. FN_SEL_RSP_0, FN_SEL_RSP_1,
  178. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2, FN_SEL_SCIF2_3,
  179. FN_SEL_SCIF2_4,
  180. FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2, FN_SEL_SOF2_3,
  181. FN_SEL_SOF2_4,
  182. FN_SEL_SSI1_0, FN_SEL_SSI1_1,
  183. FN_SEL_SSI0_0, FN_SEL_SSI0_1,
  184. FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2,
  185. PINMUX_FUNCTION_END,
  186. PINMUX_MARK_BEGIN,
  187. EX_CS0_N_MARK, RD_N_MARK,
  188. AUDIO_CLKA_MARK,
  189. VI0_CLK_MARK, VI0_DATA0_VI0_B0_MARK, VI0_DATA0_VI0_B1_MARK,
  190. VI0_DATA0_VI0_B2_MARK, VI0_DATA0_VI0_B4_MARK, VI0_DATA0_VI0_B5_MARK,
  191. VI0_DATA0_VI0_B6_MARK, VI0_DATA0_VI0_B7_MARK,
  192. USB0_PWEN_MARK, USB0_OVC_MARK, USB1_PWEN_MARK,
  193. /* IPSR0 IPSR10 */
  194. /* IPSR11 */
  195. VI0_R5_MARK, VI2_DATA6_MARK, GLO_SDATA_B_MARK, RX0_C_MARK, SDA1_D_MARK,
  196. VI0_R6_MARK, VI2_DATA7_MARK, GLO_SS_B_MARK, TX1_C_MARK, SCL4_B_MARK,
  197. VI0_R7_MARK, GLO_RFON_B_MARK, RX1_C_MARK, CAN0_RX_E_MARK,
  198. SDA4_B_MARK, _MARK, HRX1_D_MARK, SCIFB0_RXD_D_MARK,
  199. VI1_HSYNC_N_MARK, AVB_RXD0_MARK, TS_SDATA0_B_MARK,
  200. TX4_B_MARK, SCIFA4_TXD_B_MARK,
  201. VI1_VSYNC_N_MARK, AVB_RXD1_MARK, TS_SCK0_B_MARK,
  202. RX4_B_MARK, SCIFA4_RXD_B_MARK,
  203. VI1_CLKENB_MARK, AVB_RXD2_MARK, TS_SDEN0_B_MARK,
  204. VI1_FIELD_MARK, AVB_RXD3_MARK, TS_SPSYNC0_B_MARK,
  205. VI1_CLK_MARK, AVB_RXD4_MARK, VI1_DATA0_MARK, AVB_RXD5_MARK,
  206. VI1_DATA1_MARK, AVB_RXD6_MARK, VI1_DATA2_MARK, AVB_RXD7_MARK,
  207. VI1_DATA3_MARK, AVB_RX_ER_MARK, VI1_DATA4_MARK, AVB_MDIO_MARK,
  208. VI1_DATA5_MARK, AVB_RX_DV_MARK, VI1_DATA6_MARK, AVB_MAGIC_MARK,
  209. VI1_DATA7_MARK, AVB_MDC_MARK,
  210. ETH_MDIO_MARK, AVB_RX_CLK_MARK, SCL2_C_MARK,
  211. ETH_CRS_DV_MARK, AVB_LINK_MARK, SDA2_C_MARK,
  212. /* IPSR12 */
  213. ETH_RX_ER_MARK, AVB_CRS_MARK, SCL3_MARK, SCL7_MARK,
  214. ETH_RXD0_MARK, AVB_PHY_INT_MARK, SDA3_MARK, SDA7_MARK,
  215. ETH_RXD1_MARK, AVB_GTXREFCLK_MARK, CAN0_TX_C_MARK,
  216. SCL2_D_MARK, MSIOF1_RXD_E_MARK,
  217. ETH_LINK_MARK, AVB_TXD0_MARK, CAN0_RX_C_MARK,
  218. SDA2_D_MARK, MSIOF1_SCK_E_MARK,
  219. ETH_REFCLK_MARK, AVB_TXD1_MARK, SCIFA3_RXD_B_MARK,
  220. CAN1_RX_C_MARK, MSIOF1_SYNC_E_MARK,
  221. ETH_TXD1_MARK, AVB_TXD2_MARK, SCIFA3_TXD_B_MARK,
  222. CAN1_TX_C_MARK, MSIOF1_TXD_E_MARK,
  223. ETH_TX_EN_MARK, AVB_TXD3_MARK, TCLK1_B_MARK, CAN_CLK_B_MARK,
  224. ETH_MAGIC_MARK, AVB_TXD4_MARK, IETX_C_MARK,
  225. ETH_TXD0_MARK, AVB_TXD5_MARK, IECLK_C_MARK,
  226. ETH_MDC_MARK, AVB_TXD6_MARK, IERX_C_MARK,
  227. STP_IVCXO27_0_MARK, AVB_TXD7_MARK, SCIFB2_TXD_D_MARK,
  228. ADIDATA_B_MARK, MSIOF0_SYNC_C_MARK,
  229. STP_ISCLK_0_MARK, AVB_TX_EN_MARK, SCIFB2_RXD_D_MARK,
  230. ADICS_SAMP_B_MARK, MSIOF0_SCK_C_MARK,
  231. /* IPSR13 */
  232. PINMUX_MARK_END,
  233. };
  234. static pinmux_enum_t pinmux_data[] = {
  235. PINMUX_DATA_GP_ALL(), /* PINMUX_DATA(GP_M_N_DATA, GP_M_N_FN...), */
  236. /* OTHER IPSR0 - IPSR10 */
  237. /* IPSR11 */
  238. PINMUX_IPSR_DATA(IP11_2_0, VI0_R5),
  239. PINMUX_IPSR_DATA(IP11_2_0, VI2_DATA6),
  240. PINMUX_IPSR_MODSEL_DATA(IP11_2_0, GLO_SDATA_B, SEL_GPS_1),
  241. PINMUX_IPSR_MODSEL_DATA(IP11_2_0, RX0_C, SEL_SCIF0_2),
  242. PINMUX_IPSR_MODSEL_DATA(IP11_2_0, SDA1_D, SEL_IIC1_3),
  243. PINMUX_IPSR_DATA(IP11_5_3, VI0_R6),
  244. PINMUX_IPSR_DATA(IP11_5_3, VI2_DATA7),
  245. PINMUX_IPSR_MODSEL_DATA(IP11_5_3, GLO_SS_B, SEL_GPS_1),
  246. PINMUX_IPSR_MODSEL_DATA(IP11_5_3, TX1_C, SEL_SCIF1_2),
  247. PINMUX_IPSR_MODSEL_DATA(IP11_5_3, SCL4_B, SEL_IIC4_1),
  248. PINMUX_IPSR_DATA(IP11_8_6, VI0_R7),
  249. PINMUX_IPSR_MODSEL_DATA(IP11_8_6, GLO_RFON_B, SEL_GPS_1),
  250. PINMUX_IPSR_MODSEL_DATA(IP11_8_6, RX1_C, SEL_SCIF1_2),
  251. PINMUX_IPSR_MODSEL_DATA(IP11_8_6, CAN0_RX_E, SEL_CAN0_4),
  252. PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SDA4_B, SEL_IIC4_1),
  253. PINMUX_IPSR_MODSEL_DATA(IP11_8_6, HRX1_D, SEL_HSCIF1_3),
  254. PINMUX_IPSR_MODSEL_DATA(IP11_8_6, SCIFB0_RXD_D, SEL_SCIFB_3),
  255. PINMUX_IPSR_MODSEL_DATA(IP11_11_9, VI1_HSYNC_N, SEL_VI1_0),
  256. PINMUX_IPSR_DATA(IP11_11_9, AVB_RXD0),
  257. PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TS_SDATA0_B, SEL_TSIF0_1),
  258. PINMUX_IPSR_MODSEL_DATA(IP11_11_9, TX4_B, SEL_SCIF4_1),
  259. PINMUX_IPSR_MODSEL_DATA(IP11_11_9, SCIFA4_TXD_B, SEL_SCIFA4_1),
  260. PINMUX_IPSR_MODSEL_DATA(IP11_14_12, VI1_VSYNC_N, SEL_VI1_0),
  261. PINMUX_IPSR_DATA(IP11_14_12, AVB_RXD1),
  262. PINMUX_IPSR_MODSEL_DATA(IP11_14_12, TS_SCK0_B, SEL_TSIF0_1),
  263. PINMUX_IPSR_MODSEL_DATA(IP11_14_12, RX4_B, SEL_SCIF4_1),
  264. PINMUX_IPSR_MODSEL_DATA(IP11_14_12, SCIFA4_RXD_B, SEL_SCIFA4_1),
  265. PINMUX_IPSR_MODSEL_DATA(IP11_16_15, VI1_CLKENB, SEL_VI1_0),
  266. PINMUX_IPSR_DATA(IP11_16_15, AVB_RXD2),
  267. PINMUX_IPSR_MODSEL_DATA(IP11_16_15, TS_SDEN0_B, SEL_TSIF0_1),
  268. PINMUX_IPSR_MODSEL_DATA(IP11_18_17, VI1_FIELD, SEL_VI1_0),
  269. PINMUX_IPSR_DATA(IP11_18_17, AVB_RXD3),
  270. PINMUX_IPSR_MODSEL_DATA(IP11_18_17, TS_SPSYNC0_B, SEL_TSIF0_1),
  271. PINMUX_IPSR_MODSEL_DATA(IP11_19, VI1_CLK, SEL_VI1_0),
  272. PINMUX_IPSR_DATA(IP11_19, AVB_RXD4),
  273. PINMUX_IPSR_MODSEL_DATA(IP11_20, VI1_DATA0, SEL_VI1_0),
  274. PINMUX_IPSR_DATA(IP11_20, AVB_RXD5),
  275. PINMUX_IPSR_MODSEL_DATA(IP11_21, VI1_DATA1, SEL_VI1_0),
  276. PINMUX_IPSR_DATA(IP11_21, AVB_RXD6),
  277. PINMUX_IPSR_MODSEL_DATA(IP11_22, VI1_DATA2, SEL_VI1_0),
  278. PINMUX_IPSR_DATA(IP11_22, AVB_RXD7),
  279. PINMUX_IPSR_MODSEL_DATA(IP11_23, VI1_DATA3, SEL_VI1_0),
  280. PINMUX_IPSR_DATA(IP11_23, AVB_RX_ER),
  281. PINMUX_IPSR_MODSEL_DATA(IP11_24, VI1_DATA4, SEL_VI1_0),
  282. PINMUX_IPSR_DATA(IP11_24, AVB_MDIO),
  283. PINMUX_IPSR_MODSEL_DATA(IP11_25, VI1_DATA5, SEL_VI1_0),
  284. PINMUX_IPSR_DATA(IP11_25, AVB_RX_DV),
  285. PINMUX_IPSR_MODSEL_DATA(IP11_26, VI1_DATA6, SEL_VI1_0),
  286. PINMUX_IPSR_DATA(IP11_26, AVB_MAGIC),
  287. PINMUX_IPSR_MODSEL_DATA(IP11_27, VI1_DATA7, SEL_VI1_0),
  288. PINMUX_IPSR_DATA(IP11_27, AVB_MDC),
  289. PINMUX_IPSR_DATA(IP11_29_28, ETH_MDIO),
  290. PINMUX_IPSR_DATA(IP11_29_28, AVB_RX_CLK),
  291. PINMUX_IPSR_MODSEL_DATA(IP11_29_28, SCL2_C, SEL_IIC2_2),
  292. PINMUX_IPSR_DATA(IP11_31_30, ETH_CRS_DV),
  293. PINMUX_IPSR_DATA(IP11_31_30, AVB_LINK),
  294. PINMUX_IPSR_MODSEL_DATA(IP11_31_30, SDA2_C, SEL_IIC2_2),
  295. /* IPSR12 */
  296. PINMUX_IPSR_DATA(IP12_1_0, ETH_RX_ER),
  297. PINMUX_IPSR_DATA(IP12_1_0, AVB_CRS),
  298. PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL3, SEL_IIC3_0),
  299. PINMUX_IPSR_MODSEL_DATA(IP12_1_0, SCL7, SEL_IIC7_0),
  300. PINMUX_IPSR_DATA(IP12_3_2, ETH_RXD0),
  301. PINMUX_IPSR_DATA(IP12_3_2, AVB_PHY_INT),
  302. PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA3, SEL_IIC3_0),
  303. PINMUX_IPSR_MODSEL_DATA(IP12_3_2, SDA7, SEL_IIC7_0),
  304. PINMUX_IPSR_DATA(IP12_6_4, ETH_RXD1),
  305. PINMUX_IPSR_DATA(IP12_6_4, AVB_GTXREFCLK),
  306. PINMUX_IPSR_MODSEL_DATA(IP12_6_4, CAN0_TX_C, SEL_CAN0_2),
  307. PINMUX_IPSR_MODSEL_DATA(IP12_6_4, SCL2_D, SEL_IIC2_3),
  308. PINMUX_IPSR_MODSEL_DATA(IP12_6_4, MSIOF1_RXD_E, SEL_SOF1_4),
  309. PINMUX_IPSR_DATA(IP12_9_7, ETH_LINK),
  310. PINMUX_IPSR_DATA(IP12_9_7, AVB_TXD0),
  311. PINMUX_IPSR_MODSEL_DATA(IP12_9_7, CAN0_RX_C, SEL_CAN0_2),
  312. PINMUX_IPSR_MODSEL_DATA(IP12_9_7, SDA2_D, SEL_IIC2_3),
  313. PINMUX_IPSR_MODSEL_DATA(IP12_9_7, MSIOF1_SCK_E, SEL_SOF1_4),
  314. PINMUX_IPSR_DATA(IP12_12_10, ETH_REFCLK),
  315. PINMUX_IPSR_DATA(IP12_12_10, AVB_TXD1),
  316. PINMUX_IPSR_MODSEL_DATA(IP12_12_10, SCIFA3_RXD_B, SEL_SCIFA3_1),
  317. PINMUX_IPSR_MODSEL_DATA(IP12_12_10, CAN1_RX_C, SEL_CAN1_2),
  318. PINMUX_IPSR_MODSEL_DATA(IP12_12_10, MSIOF1_SYNC_E, SEL_SOF1_4),
  319. PINMUX_IPSR_DATA(IP12_15_13, ETH_TXD1),
  320. PINMUX_IPSR_DATA(IP12_15_13, AVB_TXD2),
  321. PINMUX_IPSR_MODSEL_DATA(IP12_15_13, SCIFA3_TXD_B, SEL_SCIFA3_1),
  322. PINMUX_IPSR_MODSEL_DATA(IP12_15_13, CAN1_TX_C, SEL_CAN1_2),
  323. PINMUX_IPSR_MODSEL_DATA(IP12_15_13, MSIOF1_TXD_E, SEL_SOF1_4),
  324. PINMUX_IPSR_DATA(IP12_17_16, ETH_TX_EN),
  325. PINMUX_IPSR_DATA(IP12_17_16, AVB_TXD3),
  326. PINMUX_IPSR_MODSEL_DATA(IP12_17_16, TCLK1_B, SEL_TMU1_0),
  327. PINMUX_IPSR_MODSEL_DATA(IP12_17_16, CAN_CLK_B, SEL_CANCLK_1),
  328. PINMUX_IPSR_DATA(IP12_19_18, ETH_MAGIC),
  329. PINMUX_IPSR_DATA(IP12_19_18, AVB_TXD4),
  330. PINMUX_IPSR_MODSEL_DATA(IP12_19_18, IETX_C, SEL_IEB_2),
  331. PINMUX_IPSR_DATA(IP12_21_20, ETH_TXD0),
  332. PINMUX_IPSR_DATA(IP12_21_20, AVB_TXD5),
  333. PINMUX_IPSR_MODSEL_DATA(IP12_21_20, IECLK_C, SEL_IEB_2),
  334. PINMUX_IPSR_DATA(IP12_23_22, ETH_MDC),
  335. PINMUX_IPSR_DATA(IP12_23_22, AVB_TXD6),
  336. PINMUX_IPSR_MODSEL_DATA(IP12_23_22, IERX_C, SEL_IEB_2),
  337. PINMUX_IPSR_MODSEL_DATA(IP12_26_24, STP_IVCXO27_0, SEL_SSP_0),
  338. PINMUX_IPSR_DATA(IP12_26_24, AVB_TXD7),
  339. PINMUX_IPSR_MODSEL_DATA(IP12_26_24, SCIFB2_TXD_D, SEL_SCIFB2_3),
  340. PINMUX_IPSR_MODSEL_DATA(IP12_26_24, ADIDATA_B, SEL_RAD_1),
  341. PINMUX_IPSR_MODSEL_DATA(IP12_26_24, MSIOF0_SYNC_C, SEL_SOF0_2),
  342. PINMUX_IPSR_MODSEL_DATA(IP12_29_27, STP_ISCLK_0, SEL_SSP_0),
  343. PINMUX_IPSR_DATA(IP12_29_27, AVB_TX_EN),
  344. PINMUX_IPSR_MODSEL_DATA(IP12_29_27, SCIFB2_RXD_D, SEL_SCIFB2_3),
  345. PINMUX_IPSR_MODSEL_DATA(IP12_29_27, ADICS_SAMP_B, SEL_RAD_1),
  346. PINMUX_IPSR_MODSEL_DATA(IP12_29_27, MSIOF0_SCK_C, SEL_SOF0_2),
  347. /* IPSR13 - IPSR16 */
  348. };
  349. static struct pinmux_gpio pinmux_gpios[] = {
  350. PINMUX_GPIO_GP_ALL(),
  351. /* OTHER, IPSR0 - IPSR10 */
  352. /* IPSR11 */
  353. GPIO_FN(VI0_R5), GPIO_FN(VI2_DATA6), GPIO_FN(GLO_SDATA_B),
  354. GPIO_FN(RX0_C), GPIO_FN(SDA1_D),
  355. GPIO_FN(VI0_R6), GPIO_FN(VI2_DATA7),
  356. GPIO_FN(GLO_SS_B), GPIO_FN(TX1_C), GPIO_FN(SCL4_B),
  357. GPIO_FN(VI0_R7), GPIO_FN(GLO_RFON_B),
  358. GPIO_FN(RX1_C), GPIO_FN(CAN0_RX_E),
  359. GPIO_FN(SDA4_B), GPIO_FN(HRX1_D), GPIO_FN(SCIFB0_RXD_D),
  360. GPIO_FN(VI1_HSYNC_N), GPIO_FN(AVB_RXD0), GPIO_FN(TS_SDATA0_B),
  361. GPIO_FN(TX4_B), GPIO_FN(SCIFA4_TXD_B),
  362. GPIO_FN(VI1_VSYNC_N), GPIO_FN(AVB_RXD1), GPIO_FN(TS_SCK0_B),
  363. GPIO_FN(RX4_B), GPIO_FN(SCIFA4_RXD_B),
  364. GPIO_FN(VI1_CLKENB), GPIO_FN(AVB_RXD2), GPIO_FN(TS_SDEN0_B),
  365. GPIO_FN(VI1_FIELD), GPIO_FN(AVB_RXD3), GPIO_FN(TS_SPSYNC0_B),
  366. GPIO_FN(VI1_CLK), GPIO_FN(AVB_RXD4),
  367. GPIO_FN(VI1_DATA0), GPIO_FN(AVB_RXD5),
  368. GPIO_FN(VI1_DATA1), GPIO_FN(AVB_RXD6),
  369. GPIO_FN(VI1_DATA2), GPIO_FN(AVB_RXD7),
  370. GPIO_FN(VI1_DATA3), GPIO_FN(AVB_RX_ER),
  371. GPIO_FN(VI1_DATA4), GPIO_FN(AVB_MDIO),
  372. GPIO_FN(VI1_DATA5), GPIO_FN(AVB_RX_DV),
  373. GPIO_FN(VI1_DATA6), GPIO_FN(AVB_MAGIC),
  374. GPIO_FN(VI1_DATA7), GPIO_FN(AVB_MDC),
  375. GPIO_FN(ETH_MDIO), GPIO_FN(AVB_RX_CLK), GPIO_FN(SCL2_C),
  376. GPIO_FN(ETH_CRS_DV), GPIO_FN(AVB_LINK), GPIO_FN(SDA2_C),
  377. /* IPSR12 */
  378. GPIO_FN(ETH_RX_ER), GPIO_FN(AVB_CRS), GPIO_FN(SCL3), GPIO_FN(SCL7),
  379. GPIO_FN(ETH_RXD0), GPIO_FN(AVB_PHY_INT), GPIO_FN(SDA3), GPIO_FN(SDA7),
  380. GPIO_FN(ETH_RXD1), GPIO_FN(AVB_GTXREFCLK), GPIO_FN(CAN0_TX_C),
  381. GPIO_FN(SCL2_D), GPIO_FN(MSIOF1_RXD_E),
  382. GPIO_FN(ETH_LINK), GPIO_FN(AVB_TXD0), GPIO_FN(CAN0_RX_C),
  383. GPIO_FN(SDA2_D), GPIO_FN(MSIOF1_SCK_E),
  384. GPIO_FN(ETH_REFCLK), GPIO_FN(AVB_TXD1), GPIO_FN(SCIFA3_RXD_B),
  385. GPIO_FN(CAN1_RX_C), GPIO_FN(MSIOF1_SYNC_E),
  386. GPIO_FN(ETH_TXD1), GPIO_FN(AVB_TXD2), GPIO_FN(SCIFA3_TXD_B),
  387. GPIO_FN(CAN1_TX_C), GPIO_FN(MSIOF1_TXD_E),
  388. GPIO_FN(ETH_TX_EN), GPIO_FN(AVB_TXD3),
  389. GPIO_FN(TCLK1_B), GPIO_FN(CAN_CLK_B),
  390. GPIO_FN(ETH_MAGIC), GPIO_FN(AVB_TXD4), GPIO_FN(IETX_C),
  391. GPIO_FN(ETH_TXD0), GPIO_FN(AVB_TXD5), GPIO_FN(IECLK_C),
  392. GPIO_FN(ETH_MDC), GPIO_FN(AVB_TXD6), GPIO_FN(IERX_C),
  393. GPIO_FN(STP_IVCXO27_0), GPIO_FN(AVB_TXD7), GPIO_FN(SCIFB2_TXD_D),
  394. GPIO_FN(ADIDATA_B), GPIO_FN(MSIOF0_SYNC_C),
  395. GPIO_FN(STP_ISCLK_0), GPIO_FN(AVB_TX_EN), GPIO_FN(SCIFB2_RXD_D),
  396. GPIO_FN(ADICS_SAMP_B), GPIO_FN(MSIOF0_SCK_C),
  397. /* IPSR13 - IPSR16 */
  398. };
  399. static struct pinmux_cfg_reg pinmux_config_regs[] = {
  400. { PINMUX_CFG_REG("GPSR0", 0xE6060004, 32, 1) {
  401. GP_0_31_FN, FN_IP1_22_20,
  402. GP_0_30_FN, FN_IP1_19_17,
  403. GP_0_29_FN, FN_IP1_16_14,
  404. GP_0_28_FN, FN_IP1_13_11,
  405. GP_0_27_FN, FN_IP1_10_8,
  406. GP_0_26_FN, FN_IP1_7_6,
  407. GP_0_25_FN, FN_IP1_5_4,
  408. GP_0_24_FN, FN_IP1_3_2,
  409. GP_0_23_FN, FN_IP1_1_0,
  410. GP_0_22_FN, FN_IP0_30_29,
  411. GP_0_21_FN, FN_IP0_28_27,
  412. GP_0_20_FN, FN_IP0_26_25,
  413. GP_0_19_FN, FN_IP0_24_23,
  414. GP_0_18_FN, FN_IP0_22_21,
  415. GP_0_17_FN, FN_IP0_20_19,
  416. GP_0_16_FN, FN_IP0_18_16,
  417. GP_0_15_FN, FN_IP0_15,
  418. GP_0_14_FN, FN_IP0_14,
  419. GP_0_13_FN, FN_IP0_13,
  420. GP_0_12_FN, FN_IP0_12,
  421. GP_0_11_FN, FN_IP0_11,
  422. GP_0_10_FN, FN_IP0_10,
  423. GP_0_9_FN, FN_IP0_9,
  424. GP_0_8_FN, FN_IP0_8,
  425. GP_0_7_FN, FN_IP0_7,
  426. GP_0_6_FN, FN_IP0_6,
  427. GP_0_5_FN, FN_IP0_5,
  428. GP_0_4_FN, FN_IP0_4,
  429. GP_0_3_FN, FN_IP0_3,
  430. GP_0_2_FN, FN_IP0_2,
  431. GP_0_1_FN, FN_IP0_1,
  432. GP_0_0_FN, FN_IP0_0, }
  433. },
  434. { PINMUX_CFG_REG("GPSR1", 0xE6060008, 32, 1) {
  435. 0, 0,
  436. 0, 0,
  437. 0, 0,
  438. 0, 0,
  439. 0, 0,
  440. 0, 0,
  441. GP_1_25_FN, FN_IP3_21_20,
  442. GP_1_24_FN, FN_IP3_19_18,
  443. GP_1_23_FN, FN_IP3_17_16,
  444. GP_1_22_FN, FN_IP3_15_14,
  445. GP_1_21_FN, FN_IP3_13_12,
  446. GP_1_20_FN, FN_IP3_11_9,
  447. GP_1_19_FN, FN_RD_N,
  448. GP_1_18_FN, FN_IP3_8_6,
  449. GP_1_17_FN, FN_IP3_5_3,
  450. GP_1_16_FN, FN_IP3_2_0,
  451. GP_1_15_FN, FN_IP2_29_27,
  452. GP_1_14_FN, FN_IP2_26_25,
  453. GP_1_13_FN, FN_IP2_24_23,
  454. GP_1_12_FN, FN_EX_CS0_N,
  455. GP_1_11_FN, FN_IP2_22_21,
  456. GP_1_10_FN, FN_IP2_20_19,
  457. GP_1_9_FN, FN_IP2_18_16,
  458. GP_1_8_FN, FN_IP2_15_13,
  459. GP_1_7_FN, FN_IP2_12_10,
  460. GP_1_6_FN, FN_IP2_9_7,
  461. GP_1_5_FN, FN_IP2_6_5,
  462. GP_1_4_FN, FN_IP2_4_3,
  463. GP_1_3_FN, FN_IP2_2_0,
  464. GP_1_2_FN, FN_IP1_31_29,
  465. GP_1_1_FN, FN_IP1_28_26,
  466. GP_1_0_FN, FN_IP1_25_23, }
  467. },
  468. { PINMUX_CFG_REG("GPSR2", 0xE606000C, 32, 1) {
  469. GP_2_31_FN, FN_IP6_7_6,
  470. GP_2_30_FN, FN_IP6_5_3,
  471. GP_2_29_FN, FN_IP6_2_0,
  472. GP_2_28_FN, FN_AUDIO_CLKA,
  473. GP_2_27_FN, FN_IP5_31_29,
  474. GP_2_26_FN, FN_IP5_28_26,
  475. GP_2_25_FN, FN_IP5_25_24,
  476. GP_2_24_FN, FN_IP5_23_22,
  477. GP_2_23_FN, FN_IP5_21_20,
  478. GP_2_22_FN, FN_IP5_19_17,
  479. GP_2_21_FN, FN_IP5_16_15,
  480. GP_2_20_FN, FN_IP5_14_12,
  481. GP_2_19_FN, FN_IP5_11_9,
  482. GP_2_18_FN, FN_IP5_8_6,
  483. GP_2_17_FN, FN_IP5_5_3,
  484. GP_2_16_FN, FN_IP5_2_0,
  485. GP_2_15_FN, FN_IP4_30_28,
  486. GP_2_14_FN, FN_IP4_27_26,
  487. GP_2_13_FN, FN_IP4_25_24,
  488. GP_2_12_FN, FN_IP4_23_22,
  489. GP_2_11_FN, FN_IP4_21,
  490. GP_2_10_FN, FN_IP4_20,
  491. GP_2_9_FN, FN_IP4_19,
  492. GP_2_8_FN, FN_IP4_18_16,
  493. GP_2_7_FN, FN_IP4_15_13,
  494. GP_2_6_FN, FN_IP4_12_10,
  495. GP_2_5_FN, FN_IP4_9_8,
  496. GP_2_4_FN, FN_IP4_7_5,
  497. GP_2_3_FN, FN_IP4_4_2,
  498. GP_2_2_FN, FN_IP4_1_0,
  499. GP_2_1_FN, FN_IP3_30_28,
  500. GP_2_0_FN, FN_IP3_27_25 }
  501. },
  502. { PINMUX_CFG_REG("GPSR3", 0xE6060010, 32, 1) {
  503. GP_3_31_FN, FN_IP9_18_17,
  504. GP_3_30_FN, FN_IP9_16,
  505. GP_3_29_FN, FN_IP9_15_13,
  506. GP_3_28_FN, FN_IP9_12,
  507. GP_3_27_FN, FN_IP9_11,
  508. GP_3_26_FN, FN_IP9_10_8,
  509. GP_3_25_FN, FN_IP9_7,
  510. GP_3_24_FN, FN_IP9_6,
  511. GP_3_23_FN, FN_IP9_5_3,
  512. GP_3_22_FN, FN_IP9_2_0,
  513. GP_3_21_FN, FN_IP8_30_28,
  514. GP_3_20_FN, FN_IP8_27_26,
  515. GP_3_19_FN, FN_IP8_25_24,
  516. GP_3_18_FN, FN_IP8_23_21,
  517. GP_3_17_FN, FN_IP8_20_18,
  518. GP_3_16_FN, FN_IP8_17_15,
  519. GP_3_15_FN, FN_IP8_14_12,
  520. GP_3_14_FN, FN_IP8_11_9,
  521. GP_3_13_FN, FN_IP8_8_6,
  522. GP_3_12_FN, FN_IP8_5_3,
  523. GP_3_11_FN, FN_IP8_2_0,
  524. GP_3_10_FN, FN_IP7_29_27,
  525. GP_3_9_FN, FN_IP7_26_24,
  526. GP_3_8_FN, FN_IP7_23_21,
  527. GP_3_7_FN, FN_IP7_20_19,
  528. GP_3_6_FN, FN_IP7_18_17,
  529. GP_3_5_FN, FN_IP7_16_15,
  530. GP_3_4_FN, FN_IP7_14_13,
  531. GP_3_3_FN, FN_IP7_12_11,
  532. GP_3_2_FN, FN_IP7_10_9,
  533. GP_3_1_FN, FN_IP7_8_6,
  534. GP_3_0_FN, FN_IP7_5_3 }
  535. },
  536. { PINMUX_CFG_REG("GPSR4", 0xE6060014, 32, 1) {
  537. GP_4_31_FN, FN_IP15_5_4,
  538. GP_4_30_FN, FN_IP15_3_2,
  539. GP_4_29_FN, FN_IP15_1_0,
  540. GP_4_28_FN, FN_IP11_8_6,
  541. GP_4_27_FN, FN_IP11_5_3,
  542. GP_4_26_FN, FN_IP11_2_0,
  543. GP_4_25_FN, FN_IP10_31_29,
  544. GP_4_24_FN, FN_IP10_28_27,
  545. GP_4_23_FN, FN_IP10_26_25,
  546. GP_4_22_FN, FN_IP10_24_22,
  547. GP_4_21_FN, FN_IP10_21_19,
  548. GP_4_20_FN, FN_IP10_18_17,
  549. GP_4_19_FN, FN_IP10_16_15,
  550. GP_4_18_FN, FN_IP10_14_12,
  551. GP_4_17_FN, FN_IP10_11_9,
  552. GP_4_16_FN, FN_IP10_8_6,
  553. GP_4_15_FN, FN_IP10_5_3,
  554. GP_4_14_FN, FN_IP10_2_0,
  555. GP_4_13_FN, FN_IP9_31_29,
  556. GP_4_12_FN, FN_VI0_DATA0_VI0_B7,
  557. GP_4_11_FN, FN_VI0_DATA0_VI0_B6,
  558. GP_4_10_FN, FN_VI0_DATA0_VI0_B5,
  559. GP_4_9_FN, FN_VI0_DATA0_VI0_B4,
  560. GP_4_8_FN, FN_IP9_28_27,
  561. GP_4_7_FN, FN_VI0_DATA0_VI0_B2,
  562. GP_4_6_FN, FN_VI0_DATA0_VI0_B1,
  563. GP_4_5_FN, FN_VI0_DATA0_VI0_B0,
  564. GP_4_4_FN, FN_IP9_26_25,
  565. GP_4_3_FN, FN_IP9_24_23,
  566. GP_4_2_FN, FN_IP9_22_21,
  567. GP_4_1_FN, FN_IP9_20_19,
  568. GP_4_0_FN, FN_VI0_CLK }
  569. },
  570. { PINMUX_CFG_REG("GPSR5", 0xE6060018, 32, 1) {
  571. GP_5_31_FN, FN_IP3_24_22,
  572. GP_5_30_FN, FN_IP13_9_7,
  573. GP_5_29_FN, FN_IP13_6_5,
  574. GP_5_28_FN, FN_IP13_4_3,
  575. GP_5_27_FN, FN_IP13_2_0,
  576. GP_5_26_FN, FN_IP12_29_27,
  577. GP_5_25_FN, FN_IP12_26_24,
  578. GP_5_24_FN, FN_IP12_23_22,
  579. GP_5_23_FN, FN_IP12_21_20,
  580. GP_5_22_FN, FN_IP12_19_18,
  581. GP_5_21_FN, FN_IP12_17_16,
  582. GP_5_20_FN, FN_IP12_15_13,
  583. GP_5_19_FN, FN_IP12_12_10,
  584. GP_5_18_FN, FN_IP12_9_7,
  585. GP_5_17_FN, FN_IP12_6_4,
  586. GP_5_16_FN, FN_IP12_3_2,
  587. GP_5_15_FN, FN_IP12_1_0,
  588. GP_5_14_FN, FN_IP11_31_30,
  589. GP_5_13_FN, FN_IP11_29_28,
  590. GP_5_12_FN, FN_IP11_27,
  591. GP_5_11_FN, FN_IP11_26,
  592. GP_5_10_FN, FN_IP11_25,
  593. GP_5_9_FN, FN_IP11_24,
  594. GP_5_8_FN, FN_IP11_23,
  595. GP_5_7_FN, FN_IP11_22,
  596. GP_5_6_FN, FN_IP11_21,
  597. GP_5_5_FN, FN_IP11_20,
  598. GP_5_4_FN, FN_IP11_19,
  599. GP_5_3_FN, FN_IP11_18_17,
  600. GP_5_2_FN, FN_IP11_16_15,
  601. GP_5_1_FN, FN_IP11_14_12,
  602. GP_5_0_FN, FN_IP11_11_9 }
  603. },
  604. { PINMUX_CFG_REG("GPSR6", 0xE606001C, 32, 1) {
  605. 0, 0,
  606. 0, 0,
  607. GP_6_29_FN, FN_IP14_31_29,
  608. GP_6_28_FN, FN_IP14_28_26,
  609. GP_6_27_FN, FN_IP14_25_23,
  610. GP_6_26_FN, FN_IP14_22_20,
  611. GP_6_25_FN, FN_IP14_19_17,
  612. GP_6_24_FN, FN_IP14_16_14,
  613. GP_6_23_FN, FN_IP14_13_11,
  614. GP_6_22_FN, FN_IP14_10_8,
  615. GP_6_21_FN, FN_IP14_7,
  616. GP_6_20_FN, FN_IP14_6,
  617. GP_6_19_FN, FN_IP14_5,
  618. GP_6_18_FN, FN_IP14_4,
  619. GP_6_17_FN, FN_IP14_3,
  620. GP_6_16_FN, FN_IP14_2,
  621. GP_6_15_FN, FN_IP14_1_0,
  622. GP_6_14_FN, FN_IP13_30_28,
  623. GP_6_13_FN, FN_IP13_27,
  624. GP_6_12_FN, FN_IP13_26,
  625. GP_6_11_FN, FN_IP13_25,
  626. GP_6_10_FN, FN_IP13_24_23,
  627. GP_6_9_FN, FN_IP13_22,
  628. 0, 0,
  629. GP_6_7_FN, FN_IP13_21_19,
  630. GP_6_6_FN, FN_IP13_18_16,
  631. GP_6_5_FN, FN_IP13_15,
  632. GP_6_4_FN, FN_IP13_14,
  633. GP_6_3_FN, FN_IP13_13,
  634. GP_6_2_FN, FN_IP13_12,
  635. GP_6_1_FN, FN_IP13_11,
  636. GP_6_0_FN, FN_IP13_10 }
  637. },
  638. { PINMUX_CFG_REG("GPSR7", 0xE6060074, 32, 1) {
  639. 0, 0,
  640. 0, 0,
  641. 0, 0,
  642. 0, 0,
  643. 0, 0,
  644. 0, 0,
  645. GP_7_25_FN, FN_USB1_PWEN,
  646. GP_7_24_FN, FN_USB0_OVC,
  647. GP_7_23_FN, FN_USB0_PWEN,
  648. GP_7_22_FN, FN_IP15_14_12,
  649. GP_7_21_FN, FN_IP15_11_9,
  650. GP_7_20_FN, FN_IP15_8_6,
  651. GP_7_19_FN, FN_IP7_2_0,
  652. GP_7_18_FN, FN_IP6_29_27,
  653. GP_7_17_FN, FN_IP6_26_24,
  654. GP_7_16_FN, FN_IP6_23_21,
  655. GP_7_15_FN, FN_IP6_20_19,
  656. GP_7_14_FN, FN_IP6_18_16,
  657. GP_7_13_FN, FN_IP6_15_14,
  658. GP_7_12_FN, FN_IP6_13_12,
  659. GP_7_11_FN, FN_IP6_11_10,
  660. GP_7_10_FN, FN_IP6_9_8,
  661. GP_7_9_FN, FN_IP16_11_10,
  662. GP_7_8_FN, FN_IP16_9_8,
  663. GP_7_7_FN, FN_IP16_7_6,
  664. GP_7_6_FN, FN_IP16_5_3,
  665. GP_7_5_FN, FN_IP16_2_0,
  666. GP_7_4_FN, FN_IP15_29_27,
  667. GP_7_3_FN, FN_IP15_26_24,
  668. GP_7_2_FN, FN_IP15_23_21,
  669. GP_7_1_FN, FN_IP15_20_18,
  670. GP_7_0_FN, FN_IP15_17_15 }
  671. },
  672. /* IPSR0 - IPSR10 */
  673. { PINMUX_CFG_REG_VAR("IPSR11", 0xE606004C, 32,
  674. 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2,
  675. 3, 3, 3, 3, 3) {
  676. /* IP11_31_30 [2] */
  677. FN_ETH_CRS_DV, FN_AVB_LINK, FN_SDA2_C, 0,
  678. /* IP11_29_28 [2] */
  679. FN_ETH_MDIO, FN_AVB_RX_CLK, FN_SCL2_C, 0,
  680. /* IP11_27 [1] */
  681. FN_VI1_DATA7, FN_AVB_MDC,
  682. /* IP11_26 [1] */
  683. FN_VI1_DATA6, FN_AVB_MAGIC,
  684. /* IP11_25 [1] */
  685. FN_VI1_DATA5, FN_AVB_RX_DV,
  686. /* IP11_24 [1] */
  687. FN_VI1_DATA4, FN_AVB_MDIO,
  688. /* IP11_23 [1] */
  689. FN_VI1_DATA3, FN_AVB_RX_ER,
  690. /* IP11_22 [1] */
  691. FN_VI1_DATA2, FN_AVB_RXD7,
  692. /* IP11_21 [1] */
  693. FN_VI1_DATA1, FN_AVB_RXD6,
  694. /* IP11_20 [1] */
  695. FN_VI1_DATA0, FN_AVB_RXD5,
  696. /* IP11_19 [1] */
  697. FN_VI1_CLK, FN_AVB_RXD4,
  698. /* IP11_18_17 [2] */
  699. FN_VI1_FIELD, FN_AVB_RXD3, FN_TS_SPSYNC0_B, 0,
  700. /* IP11_16_15 [2] */
  701. FN_VI1_CLKENB, FN_AVB_RXD2, FN_TS_SDEN0_B, 0,
  702. /* IP11_14_12 [3] */
  703. FN_VI1_VSYNC_N, FN_AVB_RXD1, FN_TS_SCK0_B,
  704. FN_RX4_B, FN_SCIFA4_RXD_B,
  705. 0, 0, 0,
  706. /* IP11_11_9 [3] */
  707. FN_VI1_HSYNC_N, FN_AVB_RXD0, FN_TS_SDATA0_B,
  708. FN_TX4_B, FN_SCIFA4_TXD_B,
  709. 0, 0, 0,
  710. /* IP11_8_6 [3] */
  711. FN_VI0_R7, FN_GLO_RFON_B, FN_RX1_C, FN_CAN0_RX_E,
  712. FN_SDA4_B, FN_HRX1_D, FN_SCIFB0_RXD_D, 0,
  713. /* IP11_5_3 [3] */
  714. FN_VI0_R6, FN_VI2_DATA7, FN_GLO_SS_B, FN_TX1_C, FN_SCL4_B,
  715. 0, 0, 0,
  716. /* IP11_2_0 [3] */
  717. FN_VI0_R5, FN_VI2_DATA6, FN_GLO_SDATA_B, FN_RX0_C, FN_SDA1_D,
  718. 0, 0, 0, }
  719. },
  720. { PINMUX_CFG_REG_VAR("IPSR12", 0xE6060050, 32,
  721. 2, 3, 3, 2, 2, 2, 2, 3, 3, 3, 3, 2, 2) {
  722. /* IP12_31_30 [2] */
  723. 0, 0, 0, 0,
  724. /* IP12_29_27 [3] */
  725. FN_STP_ISCLK_0, FN_AVB_TX_EN, FN_SCIFB2_RXD_D,
  726. FN_ADICS_SAMP_B, FN_MSIOF0_SCK_C,
  727. 0, 0, 0,
  728. /* IP12_26_24 [3] */
  729. FN_STP_IVCXO27_0, FN_AVB_TXD7, FN_SCIFB2_TXD_D,
  730. FN_ADIDATA_B, FN_MSIOF0_SYNC_C,
  731. 0, 0, 0,
  732. /* IP12_23_22 [2] */
  733. FN_ETH_MDC, FN_AVB_TXD6, FN_IERX_C, 0,
  734. /* IP12_21_20 [2] */
  735. FN_ETH_TXD0, FN_AVB_TXD5, FN_IECLK_C, 0,
  736. /* IP12_19_18 [2] */
  737. FN_ETH_MAGIC, FN_AVB_TXD4, FN_IETX_C, 0,
  738. /* IP12_17_16 [2] */
  739. FN_ETH_TX_EN, FN_AVB_TXD3, FN_TCLK1_B, FN_CAN_CLK_B,
  740. /* IP12_15_13 [3] */
  741. FN_ETH_TXD1, FN_AVB_TXD2, FN_SCIFA3_TXD_B,
  742. FN_CAN1_TX_C, FN_MSIOF1_TXD_E,
  743. 0, 0, 0,
  744. /* IP12_12_10 [3] */
  745. FN_ETH_REFCLK, FN_AVB_TXD1, FN_SCIFA3_RXD_B,
  746. FN_CAN1_RX_C, FN_MSIOF1_SYNC_E,
  747. 0, 0, 0,
  748. /* IP12_9_7 [3] */
  749. FN_ETH_LINK, FN_AVB_TXD0, FN_CAN0_RX_C,
  750. FN_SDA2_D, FN_MSIOF1_SCK_E,
  751. 0, 0, 0,
  752. /* IP12_6_4 [3] */
  753. FN_ETH_RXD1, FN_AVB_GTXREFCLK, FN_CAN0_TX_C,
  754. FN_SCL2_D, FN_MSIOF1_RXD_E,
  755. 0, 0, 0,
  756. /* IP12_3_2 [2] */
  757. FN_ETH_RXD0, FN_AVB_PHY_INT, FN_SDA3, FN_SDA7,
  758. /* IP12_1_0 [2] */
  759. FN_ETH_RX_ER, FN_AVB_CRS, FN_SCL3, FN_SCL7, }
  760. },
  761. /* IPSR13 - IPSR16 */
  762. { PINMUX_CFG_REG_VAR("MOD_SEL", 0xE6060090, 32,
  763. 1, 2, 2, 2, 3, 2, 1, 1, 1, 1,
  764. 3, 2, 2, 2, 1, 2, 2, 2) {
  765. /* RESEVED [1] */
  766. 0, 0,
  767. /* SEL_SCIF1 [2] */
  768. FN_SEL_SCIF1_0, FN_SEL_SCIF1_1, FN_SEL_SCIF1_2, FN_SEL_SCIF1_3,
  769. /* SEL_SCIFB [2] */
  770. FN_SEL_SCIFB_0, FN_SEL_SCIFB_1, FN_SEL_SCIFB_2, FN_SEL_SCIFB_3,
  771. /* SEL_SCIFB2 [2] */
  772. FN_SEL_SCIFB2_0, FN_SEL_SCIFB2_1,
  773. FN_SEL_SCIFB2_2, FN_SEL_SCIFB2_3,
  774. /* SEL_SCIFB1 [3] */
  775. FN_SEL_SCIFB1_0, FN_SEL_SCIFB1_1,
  776. FN_SEL_SCIFB1_2, FN_SEL_SCIFB1_3,
  777. 0, 0, 0, 0,
  778. /* SEL_SCIFA1 [2] */
  779. FN_SEL_SCIFA1_0, FN_SEL_SCIFA1_1, FN_SEL_SCIFA1_2, 0,
  780. /* SEL_SSI9 [1] */
  781. FN_SEL_SSI9_0, FN_SEL_SSI9_1,
  782. /* SEL_SCFA [1] */
  783. FN_SEL_SCFA_0, FN_SEL_SCFA_1,
  784. /* SEL_QSP [1] */
  785. FN_SEL_QSP_0, FN_SEL_QSP_1,
  786. /* SEL_SSI7 [1] */
  787. FN_SEL_SSI7_0, FN_SEL_SSI7_1,
  788. /* SEL_HSCIF1 [3] */
  789. FN_SEL_HSCIF1_0, FN_SEL_HSCIF1_1, FN_SEL_HSCIF1_2,
  790. FN_SEL_HSCIF1_3, FN_SEL_HSCIF1_4,
  791. 0, 0, 0,
  792. /* RESEVED [2] */
  793. 0, 0, 0, 0,
  794. /* SEL_VI1 [2] */
  795. FN_SEL_VI1_0, FN_SEL_VI1_1, FN_SEL_VI1_2, 0,
  796. /* RESEVED [2] */
  797. 0, 0, 0, 0,
  798. /* SEL_TMU [1] */
  799. FN_SEL_TMU1_0, FN_SEL_TMU1_1,
  800. /* SEL_LBS [2] */
  801. FN_SEL_LBS_0, FN_SEL_LBS_1, FN_SEL_LBS_2, FN_SEL_LBS_3,
  802. /* SEL_TSIF0 [2] */
  803. FN_SEL_TSIF0_0, FN_SEL_TSIF0_1, FN_SEL_TSIF0_2, FN_SEL_TSIF0_3,
  804. /* SEL_SOF0 [2] */
  805. FN_SEL_SOF0_0, FN_SEL_SOF0_1, FN_SEL_SOF0_2, 0, }
  806. },
  807. { PINMUX_CFG_REG_VAR("MOD_SEL2", 0xE6060094, 32,
  808. 3, 1, 1, 3, 2, 1, 1, 2, 2,
  809. 1, 3, 2, 1, 2, 2, 2, 1, 1, 1) {
  810. /* SEL_SCIF0 [3] */
  811. FN_SEL_SCIF0_0, FN_SEL_SCIF0_1, FN_SEL_SCIF0_2,
  812. FN_SEL_SCIF0_3, FN_SEL_SCIF0_4,
  813. 0, 0, 0,
  814. /* RESEVED [1] */
  815. 0, 0,
  816. /* SEL_SCIF [1] */
  817. FN_SEL_SCIF_0, FN_SEL_SCIF_1,
  818. /* SEL_CAN0 [3] */
  819. FN_SEL_CAN0_0, FN_SEL_CAN0_1, FN_SEL_CAN0_2, FN_SEL_CAN0_3,
  820. FN_SEL_CAN0_4, FN_SEL_CAN0_5,
  821. 0, 0,
  822. /* SEL_CAN1 [2] */
  823. FN_SEL_CAN1_0, FN_SEL_CAN1_1, FN_SEL_CAN1_2, FN_SEL_CAN1_3,
  824. /* RESEVED [1] */
  825. 0, 0,
  826. /* SEL_SCIFA2 [1] */
  827. FN_SEL_SCIFA2_0, FN_SEL_SCIFA2_1,
  828. /* SEL_SCIF4 [2] */
  829. FN_SEL_SCIF4_0, FN_SEL_SCIF4_1, FN_SEL_SCIF4_2, 0,
  830. /* RESEVED [2] */
  831. 0, 0, 0, 0,
  832. /* SEL_ADG [1] */
  833. FN_SEL_ADG_0, FN_SEL_ADG_1,
  834. /* SEL_FM [3] */
  835. FN_SEL_FM_0, FN_SEL_FM_1, FN_SEL_FM_2,
  836. FN_SEL_FM_3, FN_SEL_FM_4,
  837. 0, 0, 0,
  838. /* SEL_SCIFA5 [2] */
  839. FN_SEL_SCIFA5_0, FN_SEL_SCIFA5_1, FN_SEL_SCIFA5_2, 0,
  840. /* RESEVED [1] */
  841. 0, 0,
  842. /* SEL_GPS [2] */
  843. FN_SEL_GPS_0, FN_SEL_GPS_1, FN_SEL_GPS_2, FN_SEL_GPS_3,
  844. /* SEL_SCIFA4 [2] */
  845. FN_SEL_SCIFA4_0, FN_SEL_SCIFA4_1, FN_SEL_SCIFA4_2, 0,
  846. /* SEL_SCIFA3 [2] */
  847. FN_SEL_SCIFA3_0, FN_SEL_SCIFA3_1, FN_SEL_SCIFA3_2, 0,
  848. /* SEL_SIM [1] */
  849. FN_SEL_SIM_0, FN_SEL_SIM_1,
  850. /* RESEVED [1] */
  851. 0, 0,
  852. /* SEL_SSI8 [1] */
  853. FN_SEL_SSI8_0, FN_SEL_SSI8_1, }
  854. },
  855. { PINMUX_CFG_REG_VAR("MOD_SEL3", 0xE6060098, 32,
  856. 2, 2, 2, 2, 2, 2, 2, 2,
  857. 1, 1, 2, 2, 3, 2, 2, 2, 1) {
  858. /* SEL_HSCIF2 [2] */
  859. FN_SEL_HSCIF2_0, FN_SEL_HSCIF2_1,
  860. FN_SEL_HSCIF2_2, FN_SEL_HSCIF2_3,
  861. /* SEL_CANCLK [2] */
  862. FN_SEL_CANCLK_0, FN_SEL_CANCLK_1,
  863. FN_SEL_CANCLK_2, FN_SEL_CANCLK_3,
  864. /* SEL_IIC8 [2] */
  865. FN_SEL_IIC8_0, FN_SEL_IIC8_1, FN_SEL_IIC8_2, 0,
  866. /* SEL_IIC7 [2] */
  867. FN_SEL_IIC7_0, FN_SEL_IIC7_1, FN_SEL_IIC7_2, 0,
  868. /* SEL_IIC4 [2] */
  869. FN_SEL_IIC4_0, FN_SEL_IIC4_1, FN_SEL_IIC4_2, 0,
  870. /* SEL_IIC3 [2] */
  871. FN_SEL_IIC3_0, FN_SEL_IIC3_1, FN_SEL_IIC3_2, FN_SEL_IIC3_3,
  872. /* SEL_SCIF3 [2] */
  873. FN_SEL_SCIF3_0, FN_SEL_SCIF3_1, FN_SEL_SCIF3_2, FN_SEL_SCIF3_3,
  874. /* SEL_IEB [2] */
  875. FN_SEL_IEB_0, FN_SEL_IEB_1, FN_SEL_IEB_2, 0,
  876. /* SEL_MMC [1] */
  877. FN_SEL_MMC_0, FN_SEL_MMC_1,
  878. /* SEL_SCIF5 [1] */
  879. FN_SEL_SCIF5_0, FN_SEL_SCIF5_1,
  880. /* RESEVED [2] */
  881. 0, 0, 0, 0,
  882. /* SEL_IIC2 [2] */
  883. FN_SEL_IIC2_0, FN_SEL_IIC2_1, FN_SEL_IIC2_2, FN_SEL_IIC2_3,
  884. /* SEL_IIC1 [3] */
  885. FN_SEL_IIC1_0, FN_SEL_IIC1_1, FN_SEL_IIC1_2, FN_SEL_IIC1_3,
  886. FN_SEL_IIC1_4,
  887. 0, 0, 0,
  888. /* SEL_IIC0 [2] */
  889. FN_SEL_IIC0_0, FN_SEL_IIC0_1, FN_SEL_IIC0_2, 0,
  890. /* RESEVED [2] */
  891. 0, 0, 0, 0,
  892. /* RESEVED [2] */
  893. 0, 0, 0, 0,
  894. /* RESEVED [1] */
  895. 0, 0, }
  896. },
  897. { PINMUX_CFG_REG_VAR("MOD_SEL4", 0xE606009C, 32,
  898. 3, 2, 2, 1, 1, 1, 1, 3, 2,
  899. 2, 3, 1, 1, 1, 2, 2, 2, 2) {
  900. /* SEL_SOF1 [3] */
  901. FN_SEL_SOF1_0, FN_SEL_SOF1_1, FN_SEL_SOF1_2, FN_SEL_SOF1_3,
  902. FN_SEL_SOF1_4,
  903. 0, 0, 0,
  904. /* SEL_HSCIF0 [2] */
  905. FN_SEL_HSCIF0_0, FN_SEL_HSCIF0_1, FN_SEL_HSCIF0_2, 0,
  906. /* SEL_DIS [2] */
  907. FN_SEL_DIS_0, FN_SEL_DIS_1, FN_SEL_DIS_2, 0,
  908. /* RESEVED [1] */
  909. 0, 0,
  910. /* SEL_RAD [1] */
  911. FN_SEL_RAD_0, FN_SEL_RAD_1,
  912. /* SEL_RCN [1] */
  913. FN_SEL_RCN_0, FN_SEL_RCN_1,
  914. /* SEL_RSP [1] */
  915. FN_SEL_RSP_0, FN_SEL_RSP_1,
  916. /* SEL_SCIF2 [3] */
  917. FN_SEL_SCIF2_0, FN_SEL_SCIF2_1, FN_SEL_SCIF2_2,
  918. FN_SEL_SCIF2_3, FN_SEL_SCIF2_4,
  919. 0, 0, 0,
  920. /* RESEVED [2] */
  921. 0, 0, 0, 0,
  922. /* RESEVED [2] */
  923. 0, 0, 0, 0,
  924. /* SEL_SOF2 [3] */
  925. FN_SEL_SOF2_0, FN_SEL_SOF2_1, FN_SEL_SOF2_2,
  926. FN_SEL_SOF2_3, FN_SEL_SOF2_4,
  927. 0, 0, 0,
  928. /* RESEVED [1] */
  929. 0, 0,
  930. /* SEL_SSI1 [1] */
  931. FN_SEL_SSI1_0, FN_SEL_SSI1_1,
  932. /* SEL_SSI0 [1] */
  933. FN_SEL_SSI0_0, FN_SEL_SSI0_1,
  934. /* SEL_SSP [2] */
  935. FN_SEL_SSP_0, FN_SEL_SSP_1, FN_SEL_SSP_2, 0,
  936. /* RESEVED [2] */
  937. 0, 0, 0, 0,
  938. /* RESEVED [2] */
  939. 0, 0, 0, 0,
  940. /* RESEVED [2] */
  941. 0, 0, 0, 0, }
  942. },
  943. { PINMUX_CFG_REG("INOUTSEL0", 0xE6050004, 32, 1) { GP_INOUTSEL(0) } },
  944. { PINMUX_CFG_REG("INOUTSEL1", 0xE6051004, 32, 1) {
  945. 0, 0,
  946. 0, 0,
  947. 0, 0,
  948. 0, 0,
  949. 0, 0,
  950. 0, 0,
  951. GP_1_25_IN, GP_1_25_OUT,
  952. GP_1_24_IN, GP_1_24_OUT,
  953. GP_1_23_IN, GP_1_23_OUT,
  954. GP_1_22_IN, GP_1_22_OUT,
  955. GP_1_21_IN, GP_1_21_OUT,
  956. GP_1_20_IN, GP_1_20_OUT,
  957. GP_1_19_IN, GP_1_19_OUT,
  958. GP_1_18_IN, GP_1_18_OUT,
  959. GP_1_17_IN, GP_1_17_OUT,
  960. GP_1_16_IN, GP_1_16_OUT,
  961. GP_1_15_IN, GP_1_15_OUT,
  962. GP_1_14_IN, GP_1_14_OUT,
  963. GP_1_13_IN, GP_1_13_OUT,
  964. GP_1_12_IN, GP_1_12_OUT,
  965. GP_1_11_IN, GP_1_11_OUT,
  966. GP_1_10_IN, GP_1_10_OUT,
  967. GP_1_9_IN, GP_1_9_OUT,
  968. GP_1_8_IN, GP_1_8_OUT,
  969. GP_1_7_IN, GP_1_7_OUT,
  970. GP_1_6_IN, GP_1_6_OUT,
  971. GP_1_5_IN, GP_1_5_OUT,
  972. GP_1_4_IN, GP_1_4_OUT,
  973. GP_1_3_IN, GP_1_3_OUT,
  974. GP_1_2_IN, GP_1_2_OUT,
  975. GP_1_1_IN, GP_1_1_OUT,
  976. GP_1_0_IN, GP_1_0_OUT, }
  977. },
  978. { PINMUX_CFG_REG("INOUTSEL2", 0xE6052004, 32, 1) { GP_INOUTSEL(2) } },
  979. { PINMUX_CFG_REG("INOUTSEL3", 0xE6053004, 32, 1) { GP_INOUTSEL(3) } },
  980. { PINMUX_CFG_REG("INOUTSEL4", 0xE6054004, 32, 1) { GP_INOUTSEL(4) } },
  981. { PINMUX_CFG_REG("INOUTSEL5", 0xE6055004, 32, 1) { GP_INOUTSEL(5) } },
  982. { PINMUX_CFG_REG("INOUTSEL6", 0xE6055404, 32, 1) { GP_INOUTSEL(6) } },
  983. { PINMUX_CFG_REG("INOUTSEL7", 0xE6055804, 32, 1) {
  984. 0, 0,
  985. 0, 0,
  986. 0, 0,
  987. 0, 0,
  988. 0, 0,
  989. 0, 0,
  990. GP_7_25_IN, GP_7_25_OUT,
  991. GP_7_24_IN, GP_7_24_OUT,
  992. GP_7_23_IN, GP_7_23_OUT,
  993. GP_7_22_IN, GP_7_22_OUT,
  994. GP_7_21_IN, GP_7_21_OUT,
  995. GP_7_20_IN, GP_7_20_OUT,
  996. GP_7_19_IN, GP_7_19_OUT,
  997. GP_7_18_IN, GP_7_18_OUT,
  998. GP_7_17_IN, GP_7_17_OUT,
  999. GP_7_16_IN, GP_7_16_OUT,
  1000. GP_7_15_IN, GP_7_15_OUT,
  1001. GP_7_14_IN, GP_7_14_OUT,
  1002. GP_7_13_IN, GP_7_13_OUT,
  1003. GP_7_12_IN, GP_7_12_OUT,
  1004. GP_7_11_IN, GP_7_11_OUT,
  1005. GP_7_10_IN, GP_7_10_OUT,
  1006. GP_7_9_IN, GP_7_9_OUT,
  1007. GP_7_8_IN, GP_7_8_OUT,
  1008. GP_7_7_IN, GP_7_7_OUT,
  1009. GP_7_6_IN, GP_7_6_OUT,
  1010. GP_7_5_IN, GP_7_5_OUT,
  1011. GP_7_4_IN, GP_7_4_OUT,
  1012. GP_7_3_IN, GP_7_3_OUT,
  1013. GP_7_2_IN, GP_7_2_OUT,
  1014. GP_7_1_IN, GP_7_1_OUT,
  1015. GP_7_0_IN, GP_7_0_OUT, }
  1016. },
  1017. { },
  1018. };
  1019. static struct pinmux_data_reg pinmux_data_regs[] = {
  1020. { PINMUX_DATA_REG("INDT0", 0xE6050008, 32) { GP_INDT(0) } },
  1021. { PINMUX_DATA_REG("INDT1", 0xE6051008, 32) {
  1022. 0, 0, 0, 0,
  1023. 0, 0, GP_1_25_DATA, GP_1_24_DATA,
  1024. GP_1_23_DATA, GP_1_22_DATA, GP_1_21_DATA, GP_1_20_DATA,
  1025. GP_1_19_DATA, GP_1_18_DATA, GP_1_17_DATA, GP_1_16_DATA,
  1026. GP_1_15_DATA, GP_1_14_DATA, GP_1_13_DATA, GP_1_12_DATA,
  1027. GP_1_11_DATA, GP_1_10_DATA, GP_1_9_DATA, GP_1_8_DATA,
  1028. GP_1_7_DATA, GP_1_6_DATA, GP_1_5_DATA, GP_1_4_DATA,
  1029. GP_1_3_DATA, GP_1_2_DATA, GP_1_1_DATA, GP_1_0_DATA }
  1030. },
  1031. { PINMUX_DATA_REG("INDT2", 0xE6052008, 32) { GP_INDT(2) } },
  1032. { PINMUX_DATA_REG("INDT3", 0xE6053008, 32) { GP_INDT(3) } },
  1033. { PINMUX_DATA_REG("INDT4", 0xE6054008, 32) { GP_INDT(4) } },
  1034. { PINMUX_DATA_REG("INDT5", 0xE6055008, 32) { GP_INDT(5) } },
  1035. { PINMUX_DATA_REG("INDT6", 0xE6055408, 32) { GP_INDT(6) } },
  1036. { PINMUX_DATA_REG("INDT7", 0xE6055808, 32) {
  1037. 0, 0, 0, 0,
  1038. 0, 0, GP_7_25_DATA, GP_7_24_DATA,
  1039. GP_7_23_DATA, GP_7_22_DATA, GP_7_21_DATA, GP_7_20_DATA,
  1040. GP_7_19_DATA, GP_7_18_DATA, GP_7_17_DATA, GP_7_16_DATA,
  1041. GP_7_15_DATA, GP_7_14_DATA, GP_7_13_DATA, GP_7_12_DATA,
  1042. GP_7_11_DATA, GP_7_10_DATA, GP_7_9_DATA, GP_7_8_DATA,
  1043. GP_7_7_DATA, GP_7_6_DATA, GP_7_5_DATA, GP_7_4_DATA,
  1044. GP_7_3_DATA, GP_7_2_DATA, GP_7_1_DATA, GP_7_0_DATA }
  1045. },
  1046. { },
  1047. };
  1048. static struct pinmux_info r8a7791_pinmux_info = {
  1049. .name = "r8a7791_pfc",
  1050. .unlock_reg = 0xe6060000, /* PMMR */
  1051. .reserved_id = PINMUX_RESERVED,
  1052. .data = { PINMUX_DATA_BEGIN, PINMUX_DATA_END },
  1053. .input = { PINMUX_INPUT_BEGIN, PINMUX_INPUT_END },
  1054. .output = { PINMUX_OUTPUT_BEGIN, PINMUX_OUTPUT_END },
  1055. .mark = { PINMUX_MARK_BEGIN, PINMUX_MARK_END },
  1056. .function = { PINMUX_FUNCTION_BEGIN, PINMUX_FUNCTION_END },
  1057. .first_gpio = GPIO_GP_0_0,
  1058. .last_gpio = GPIO_FN_MSIOF0_SCK_C /* GPIO_FN_CAN1_RX_B */,
  1059. .gpios = pinmux_gpios,
  1060. .cfg_regs = pinmux_config_regs,
  1061. .data_regs = pinmux_data_regs,
  1062. .gpio_data = pinmux_data,
  1063. .gpio_data_size = ARRAY_SIZE(pinmux_data),
  1064. };
  1065. void r8a7791_pinmux_init(void)
  1066. {
  1067. register_pinmux(&r8a7791_pinmux_info);
  1068. }