sh_sdhi.h 5.0 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * drivers/mmc/sh-sdhi.h
  4. *
  5. * SD/MMC driver for Renesas rmobile ARM SoCs
  6. *
  7. * Copyright (C) 2013-2017 Renesas Electronics Corporation
  8. * Copyright (C) 2008-2009 Renesas Solutions Corp.
  9. */
  10. #ifndef _SH_SDHI_H
  11. #define _SH_SDHI_H
  12. #define SDHI_CMD (0x0000 >> 1)
  13. #define SDHI_PORTSEL (0x0004 >> 1)
  14. #define SDHI_ARG0 (0x0008 >> 1)
  15. #define SDHI_ARG1 (0x000C >> 1)
  16. #define SDHI_STOP (0x0010 >> 1)
  17. #define SDHI_SECCNT (0x0014 >> 1)
  18. #define SDHI_RSP00 (0x0018 >> 1)
  19. #define SDHI_RSP01 (0x001C >> 1)
  20. #define SDHI_RSP02 (0x0020 >> 1)
  21. #define SDHI_RSP03 (0x0024 >> 1)
  22. #define SDHI_RSP04 (0x0028 >> 1)
  23. #define SDHI_RSP05 (0x002C >> 1)
  24. #define SDHI_RSP06 (0x0030 >> 1)
  25. #define SDHI_RSP07 (0x0034 >> 1)
  26. #define SDHI_INFO1 (0x0038 >> 1)
  27. #define SDHI_INFO2 (0x003C >> 1)
  28. #define SDHI_INFO1_MASK (0x0040 >> 1)
  29. #define SDHI_INFO2_MASK (0x0044 >> 1)
  30. #define SDHI_CLK_CTRL (0x0048 >> 1)
  31. #define SDHI_SIZE (0x004C >> 1)
  32. #define SDHI_OPTION (0x0050 >> 1)
  33. #define SDHI_ERR_STS1 (0x0058 >> 1)
  34. #define SDHI_ERR_STS2 (0x005C >> 1)
  35. #define SDHI_BUF0 (0x0060 >> 1)
  36. #define SDHI_SDIO_MODE (0x0068 >> 1)
  37. #define SDHI_SDIO_INFO1 (0x006C >> 1)
  38. #define SDHI_SDIO_INFO1_MASK (0x0070 >> 1)
  39. #define SDHI_CC_EXT_MODE (0x01B0 >> 1)
  40. #define SDHI_SOFT_RST (0x01C0 >> 1)
  41. #define SDHI_VERSION (0x01C4 >> 1)
  42. #define SDHI_HOST_MODE (0x01C8 >> 1)
  43. #define SDHI_SDIF_MODE (0x01CC >> 1)
  44. #define SDHI_EXT_SWAP (0x01E0 >> 1)
  45. #define SDHI_SD_DMACR (0x0324 >> 1)
  46. /* SDHI CMD VALUE */
  47. #define CMD_MASK 0x0000ffff
  48. /* SDHI_PORTSEL */
  49. #define USE_1PORT (1 << 8) /* 1 port */
  50. /* SDHI_ARG */
  51. #define ARG0_MASK 0x0000ffff
  52. #define ARG1_MASK 0x0000ffff
  53. /* SDHI_STOP */
  54. #define STOP_SEC_ENABLE (1 << 8)
  55. /* SDHI_INFO1 */
  56. #define INFO1_RESP_END (1 << 0)
  57. #define INFO1_ACCESS_END (1 << 2)
  58. #define INFO1_CARD_RE (1 << 3)
  59. #define INFO1_CARD_IN (1 << 4)
  60. #define INFO1_ISD0CD (1 << 5)
  61. #define INFO1_WRITE_PRO (1 << 7)
  62. #define INFO1_DATA3_CARD_RE (1 << 8)
  63. #define INFO1_DATA3_CARD_IN (1 << 9)
  64. #define INFO1_DATA3 (1 << 10)
  65. /* SDHI_INFO2 */
  66. #define INFO2_CMD_ERROR (1 << 0)
  67. #define INFO2_CRC_ERROR (1 << 1)
  68. #define INFO2_END_ERROR (1 << 2)
  69. #define INFO2_TIMEOUT (1 << 3)
  70. #define INFO2_BUF_ILL_WRITE (1 << 4)
  71. #define INFO2_BUF_ILL_READ (1 << 5)
  72. #define INFO2_RESP_TIMEOUT (1 << 6)
  73. #define INFO2_SDDAT0 (1 << 7)
  74. #define INFO2_BRE_ENABLE (1 << 8)
  75. #define INFO2_BWE_ENABLE (1 << 9)
  76. #define INFO2_CBUSY (1 << 14)
  77. #define INFO2_ILA (1 << 15)
  78. #define INFO2_ALL_ERR (0x807f)
  79. /* SDHI_INFO1_MASK */
  80. #define INFO1M_RESP_END (1 << 0)
  81. #define INFO1M_ACCESS_END (1 << 2)
  82. #define INFO1M_CARD_RE (1 << 3)
  83. #define INFO1M_CARD_IN (1 << 4)
  84. #define INFO1M_DATA3_CARD_RE (1 << 8)
  85. #define INFO1M_DATA3_CARD_IN (1 << 9)
  86. #define INFO1M_ALL (0xffff)
  87. #define INFO1M_SET (INFO1M_RESP_END | \
  88. INFO1M_ACCESS_END | \
  89. INFO1M_DATA3_CARD_RE | \
  90. INFO1M_DATA3_CARD_IN)
  91. /* SDHI_INFO2_MASK */
  92. #define INFO2M_CMD_ERROR (1 << 0)
  93. #define INFO2M_CRC_ERROR (1 << 1)
  94. #define INFO2M_END_ERROR (1 << 2)
  95. #define INFO2M_TIMEOUT (1 << 3)
  96. #define INFO2M_BUF_ILL_WRITE (1 << 4)
  97. #define INFO2M_BUF_ILL_READ (1 << 5)
  98. #define INFO2M_RESP_TIMEOUT (1 << 6)
  99. #define INFO2M_BRE_ENABLE (1 << 8)
  100. #define INFO2M_BWE_ENABLE (1 << 9)
  101. #define INFO2M_ILA (1 << 15)
  102. #define INFO2M_ALL (0xffff)
  103. #define INFO2M_ALL_ERR (0x807f)
  104. /* SDHI_CLK_CTRL */
  105. #define CLK_ENABLE (1 << 8)
  106. /* SDHI_OPTION */
  107. #define OPT_BUS_WIDTH_M (5 << 13) /* 101b (15-13bit) */
  108. #define OPT_BUS_WIDTH_1 (4 << 13) /* bus width = 1 bit */
  109. #define OPT_BUS_WIDTH_4 (0 << 13) /* bus width = 4 bit */
  110. #define OPT_BUS_WIDTH_8 (1 << 13) /* bus width = 8 bit */
  111. /* SDHI_ERR_STS1 */
  112. #define ERR_STS1_CRC_ERROR ((1 << 11) | (1 << 10) | (1 << 9) | \
  113. (1 << 8) | (1 << 5))
  114. #define ERR_STS1_CMD_ERROR ((1 << 4) | (1 << 3) | (1 << 2) | \
  115. (1 << 1) | (1 << 0))
  116. /* SDHI_ERR_STS2 */
  117. #define ERR_STS2_RES_TIMEOUT (1 << 0)
  118. #define ERR_STS2_RES_STOP_TIMEOUT ((1 << 0) | (1 << 1))
  119. #define ERR_STS2_SYS_ERROR ((1 << 6) | (1 << 5) | (1 << 4) | \
  120. (1 << 3) | (1 << 2) | (1 << 1) | \
  121. (1 << 0))
  122. /* SDHI_SDIO_MODE */
  123. #define SDIO_MODE_ON (1 << 0)
  124. #define SDIO_MODE_OFF (0 << 0)
  125. /* SDHI_SDIO_INFO1 */
  126. #define SDIO_INFO1_IOIRQ (1 << 0)
  127. #define SDIO_INFO1_EXPUB52 (1 << 14)
  128. #define SDIO_INFO1_EXWT (1 << 15)
  129. /* SDHI_SDIO_INFO1_MASK */
  130. #define SDIO_INFO1M_CLEAR ((1 << 1) | (1 << 2))
  131. #define SDIO_INFO1M_ON ((1 << 15) | (1 << 14) | (1 << 2) | \
  132. (1 << 1) | (1 << 0))
  133. /* SDHI_EXT_SWAP */
  134. #define SET_SWAP ((1 << 6) | (1 << 7)) /* SWAP */
  135. /* SDHI_SOFT_RST */
  136. #define SOFT_RST_ON (0 << 0)
  137. #define SOFT_RST_OFF (1 << 0)
  138. #define CLKDEV_SD_DATA 25000000 /* 25 MHz */
  139. #define CLKDEV_HS_DATA 50000000 /* 50 MHz */
  140. #define CLKDEV_MMC_DATA 20000000 /* 20MHz */
  141. #define CLKDEV_INIT 400000 /* 100 - 400 KHz */
  142. /* For quirk */
  143. #define SH_SDHI_QUIRK_16BIT_BUF BIT(0)
  144. #define SH_SDHI_QUIRK_64BIT_BUF BIT(1)
  145. int sh_sdhi_init(unsigned long addr, int ch, unsigned long quirks);
  146. #endif /* _SH_SDHI_H */