sh73a0.h 5.2 KB

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  1. #ifndef __ASM_ARCH_RMOBILE_SH73A0_H
  2. #define __ASM_ARCH_RMOBILE_SH73A0_H
  3. /* Global Timer */
  4. #define GLOBAL_TIMER_BASE_ADDR (0xF0000200)
  5. #define MERAM_BASE (0xE5580000)
  6. /* GIC */
  7. #define GIC_BASE (0xF0000100)
  8. #define ICCICR GIC_BASE
  9. /* Secure control register */
  10. #define LIFEC_SEC_SRC (0xE6110008)
  11. /* RWDT */
  12. #define RWDT_BASE (0xE6020000)
  13. /* HPB Semaphore Control Registers */
  14. #define HPB_BASE (0xE6001010)
  15. /* Bus Semaphore Control Registers */
  16. #define HPBSCR_BASE (0xE6001600)
  17. /* SBSC1 */
  18. #define SBSC1_BASE (0xFE400000)
  19. #define SDMRA1A (SBSC1_BASE + 0x100000)
  20. #define SDMRA2A (SBSC1_BASE + 0x1C0000)
  21. #define SDMRA3A (SBSC1_BASE + 0x104000)
  22. /* SBSC2 */
  23. #define SBSC2_BASE (0xFB400000)
  24. #define SDMRA1B (SBSC2_BASE + 0x100000)
  25. #define SDMRA2B (SBSC2_BASE + 0x1C0000)
  26. #define SDMRA3B (SBSC2_BASE + 0x104000)
  27. /* CPG */
  28. #define CPG_BASE (0xE6150000)
  29. #define CPG_SRCR_BASE (CPG_BASE + 0x80A0)
  30. #define WUPCR (CPG_BASE + 0x1010)
  31. #define SRESCR (CPG_BASE + 0x1018)
  32. #define PCLKCR (CPG_BASE + 0x1020)
  33. /* SYSC */
  34. #define SYSC_BASE (0xE6180000)
  35. #define RESCNT2 (SYSC_BASE + 0x8020)
  36. /* BSC */
  37. #define BSC_BASE (0xFEC10000)
  38. /* SCIF */
  39. #define SCIF0_BASE (0xE6C40000)
  40. #define SCIF1_BASE (0xE6C50000)
  41. #define SCIF2_BASE (0xE6C60000)
  42. #define SCIF3_BASE (0xE6C70000)
  43. #define SCIF4_BASE (0xE6C80000)
  44. #define SCIF5_BASE (0xE6CB0000)
  45. #define SCIF6_BASE (0xE6CC0000)
  46. #define SCIF7_BASE (0xE6CD0000)
  47. #ifndef __ASSEMBLY__
  48. #include <asm/types.h>
  49. /* RWDT */
  50. struct sh73a0_rwdt {
  51. u16 rwtcnt0; /* 0x00 */
  52. u16 dummy0; /* 0x02 */
  53. u16 rwtcsra0; /* 0x04 */
  54. u16 dummy1; /* 0x06 */
  55. u16 rwtcsrb0; /* 0x08 */
  56. };
  57. /* HPB Semaphore Control Registers */
  58. struct sh73a0_hpb {
  59. u32 hpbctrl0;
  60. u32 hpbctrl1;
  61. u32 hpbctrl2;
  62. u32 cccr;
  63. u32 dummy0; /* 0x20 */
  64. u32 hpbctrl4;
  65. u32 hpbctrl5;
  66. u32 dummy1; /* 0x2C */
  67. u32 hpbctrl6;
  68. };
  69. /* Bus Semaphore Control Registers */
  70. struct sh73a0_hpb_bscr {
  71. u32 mpsrc; /* 0x00 */
  72. u32 mpacctl; /* 0x04 */
  73. u32 dummy0[6];
  74. u32 smgpiosrc; /* 0x20 */
  75. u32 smgpioerr;
  76. u32 smgpiotime;
  77. u32 smgpiocnt;
  78. u32 dummy1[4]; /* 0x30 .. 0x3C */
  79. u32 smcmt2src;
  80. u32 smcmt2err;
  81. u32 smcmt2time;
  82. u32 smcmt2cnt;
  83. u32 smcpgsrc;
  84. u32 smcpgerr;
  85. u32 smcpgtime;
  86. u32 smcpgcnt;
  87. u32 dummy2[4]; /* 0x60 - 0x6C */
  88. u32 smsyscsrc;
  89. u32 smsyscerr;
  90. u32 smsysctime;
  91. u32 smsysccnt;
  92. };
  93. /* SBSC */
  94. struct sh73a0_sbsc {
  95. u32 dummy0[2]; /* 0x00, 0x04 */
  96. u32 sdcr0;
  97. u32 sdcr1;
  98. u32 sdpcr;
  99. u32 dummy1; /* 0x14 */
  100. u32 sdcr0s;
  101. u32 sdcr1s;
  102. u32 rtcsr;
  103. u32 dummy2; /* 0x24 */
  104. u32 rtcor;
  105. u32 rtcorh;
  106. u32 rtcors;
  107. u32 rtcorsh;
  108. u32 dummy3[2]; /* 0x38, 0x3C */
  109. u32 sdwcrc0;
  110. u32 sdwcrc1;
  111. u32 sdwcr00;
  112. u32 sdwcr01;
  113. u32 sdwcr10;
  114. u32 sdwcr11;
  115. u32 sdpdcr0;
  116. u32 dummy4; /* 0x5C */
  117. u32 sdwcr2;
  118. u32 sdwcrc2;
  119. u32 zqccr;
  120. u32 dummy5[6]; /* 0x6C .. 0x80 */
  121. u32 sdmracr0;
  122. u32 dummy6; /* 0x88 */
  123. u32 sdmrtmpcr;
  124. u32 dummy7; /* 0x90 */
  125. u32 sdmrtmpmsk;
  126. u32 dummy8; /* 0x98 */
  127. u32 sdgencnt;
  128. u32 dphycnt0;
  129. u32 dphycnt1;
  130. u32 dphycnt2;
  131. u32 dummy9[2]; /* 0xAC .. 0xB0 */
  132. u32 sddrvcr0;
  133. u32 dummy10[14]; /* 0xB8 .. 0xEC */
  134. u32 dptdivcr0;
  135. u32 dptdivcr1;
  136. u32 dptdivcr2;
  137. u32 dummy11; /* 0xFC */
  138. u32 sdptcr0;
  139. u32 sdptcr1;
  140. u32 sdptcr2;
  141. u32 sdptcr3; /* 0x10C */
  142. u32 dummy12[145]; /* 0x110 .. 0x350 */
  143. u32 dllcnt0; /* 0x354 */
  144. u32 sbscmon0;
  145. };
  146. /* CPG */
  147. struct sh73a0_sbsc_cpg {
  148. u32 frqcra; /* 0x00 */
  149. u32 frqcrb;
  150. u32 vclkcr1;
  151. u32 vclkcr2;
  152. u32 zbckcr;
  153. u32 flckcr;
  154. u32 fsiackcr;
  155. u32 vclkcr3;
  156. u32 rtstbcr;
  157. u32 systbcr;
  158. u32 pll1cr;
  159. u32 pll2cr;
  160. u32 mstpsr0;
  161. u32 dummy0; /* 0x34 */
  162. u32 mstpsr1;
  163. u32 mstpsr5;
  164. u32 mstpsr2;
  165. u32 dummy1; /* 0x44 */
  166. u32 mstpsr3;
  167. u32 mstpsr4;
  168. u32 dummy2; /* 0x50 */
  169. u32 astat;
  170. u32 dvfscr0;
  171. u32 dvfscr1;
  172. u32 dsitckcr;
  173. u32 dsi0pckcr;
  174. u32 dsi1pckcr;
  175. u32 dsi0phycr;
  176. u32 dsi1phycr;
  177. u32 sd0ckcr;
  178. u32 sd1ckcr;
  179. u32 sd2ckcr;
  180. u32 subckcr;
  181. u32 spuackcr;
  182. u32 msuckcr;
  183. u32 hsickcr;
  184. u32 fsibckcr;
  185. u32 spuvckcr;
  186. u32 mfck1cr;
  187. u32 mfck2cr;
  188. u32 dummy3[8]; /* 0xA0 .. 0xBC */
  189. u32 ckscr;
  190. u32 dummy4; /* 0xC4 */
  191. u32 pll1stpcr;
  192. u32 mpmode;
  193. u32 pllecr;
  194. u32 dummy5; /* 0xD4 */
  195. u32 pll0cr;
  196. u32 pll3cr;
  197. u32 dummy6; /* 0xE0 */
  198. u32 frqcrd;
  199. u32 dummyi7; /* 0xE8 */
  200. u32 vrefcr;
  201. u32 pll0stpcr;
  202. u32 dummy8; /* 0xF4 */
  203. u32 pll2stpcr;
  204. u32 pll3stpcr;
  205. u32 dummy9[4]; /* 0x100 .. 0x10c */
  206. u32 rmstpcr0;
  207. u32 rmstpcr1;
  208. u32 rmstpcr2;
  209. u32 rmstpcr3;
  210. u32 rmstpcr4;
  211. u32 rmstpcr5;
  212. u32 dummy10[2]; /* 0x128 .. 0x12c */
  213. u32 smstpcr0;
  214. u32 smstpcr1;
  215. u32 smstpcr2;
  216. u32 smstpcr3;
  217. u32 smstpcr4;
  218. u32 smstpcr5;
  219. u32 dummy11[2]; /* 0x148 .. 0x14c */
  220. u32 cpgxxcs4;
  221. u32 dummy12[7]; /* 0x154 .. 0x16c */
  222. u32 dvfscr2;
  223. u32 dvfscr3;
  224. u32 dvfscr4;
  225. u32 dvfscr5; /* 0x17C */
  226. };
  227. /* CPG SRCR part OK */
  228. struct sh73a0_sbsc_cpg_srcr {
  229. u32 srcr0;
  230. u32 dummy0; /* 0xA4 */
  231. u32 srcr1;
  232. u32 dummy1; /* 0xAC */
  233. u32 srcr2;
  234. u32 dummy2; /* 0xB4 */
  235. u32 srcr3;
  236. u32 srcr4;
  237. u32 dummy3; /* 0xC0 */
  238. u32 srcr5;
  239. };
  240. /* BSC */
  241. struct sh73a0_bsc {
  242. u32 cmncr;
  243. u32 cs0bcr;
  244. u32 cs2bcr;
  245. u32 dummy0; /* 0x0C */
  246. u32 cs4bcr;
  247. u32 cs5abcr;
  248. u32 cs5bbcr;
  249. u32 cs6abcr;
  250. u32 cs6bbcr;
  251. u32 cs0wcr;
  252. u32 cs2wcr;
  253. u32 dummy1; /* 0x2C */
  254. u32 cs4wcr;
  255. u32 cs5awcr;
  256. u32 cs5bwcr;
  257. u32 cs6awcr;
  258. u32 cs6bwcr;
  259. u32 rbwtcnt;
  260. u32 busycr;
  261. u32 dummy2; /* 0x5c */
  262. u32 cs7abcr;
  263. u32 cs7awcr;
  264. u32 dummy3[2]; /* 0x68, 0x6C */
  265. u32 bromtimcr;
  266. };
  267. #endif /* __ASSEMBLY__ */
  268. #endif /* __ASM_ARCH_RMOBILE_SH73A0_H */