rcar-base.h 30 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046
  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * arch/arm/include/asm/arch-rmobile/rcar-base.h
  4. *
  5. * Copyright (C) 2013,2014 Renesas Electronics Corporation
  6. */
  7. #ifndef __ASM_ARCH_RCAR_BASE_H
  8. #define __ASM_ARCH_RCAR_BASE_H
  9. /*
  10. * R-Car (R8A7790/R8A7791/R8A7792/R8A7793/R8A7794) I/O Addresses
  11. */
  12. #define RWDT_BASE 0xE6020000
  13. #define SWDT_BASE 0xE6030000
  14. #define LBSC_BASE 0xFEC00200
  15. #define DBSC3_0_BASE 0xE6790000
  16. #define DBSC3_1_BASE 0xE67A0000
  17. #define TMU_BASE 0xE61E0000
  18. #define GPIO5_BASE 0xE6055000
  19. #define SH_QSPI_BASE 0xE6B10000
  20. /* SCIF */
  21. #define SCIF0_BASE 0xE6E60000
  22. #define SCIF1_BASE 0xE6E68000
  23. #define SCIF2_BASE 0xE6E58000
  24. #define SCIF3_BASE 0xE6EA8000
  25. #define SCIF4_BASE 0xE6EE0000
  26. #define SCIF5_BASE 0xE6EE8000
  27. #define SCIFA0_BASE 0xE6C40000
  28. #define SCIFA1_BASE 0xE6C50000
  29. #define SCIFA2_BASE 0xE6C60000
  30. /* Module stop status register */
  31. #define MSTPSR0 0xE6150030
  32. #define MSTPSR1 0xE6150038
  33. #define MSTPSR2 0xE6150040
  34. #define MSTPSR3 0xE6150048
  35. #define MSTPSR4 0xE615004C
  36. #define MSTPSR5 0xE615003C
  37. #define MSTPSR7 0xE61501C4
  38. #define MSTPSR8 0xE61509A0
  39. #define MSTPSR9 0xE61509A4
  40. #define MSTPSR10 0xE61509A8
  41. #define MSTPSR11 0xE61509AC
  42. /* Realtime module stop control register */
  43. #define RMSTPCR0 0xE6150110
  44. #define RMSTPCR1 0xE6150114
  45. #define RMSTPCR2 0xE6150118
  46. #define RMSTPCR3 0xE615011C
  47. #define RMSTPCR4 0xE6150120
  48. #define RMSTPCR5 0xE6150124
  49. #define RMSTPCR7 0xE615012C
  50. #define RMSTPCR8 0xE6150980
  51. #define RMSTPCR9 0xE6150984
  52. #define RMSTPCR10 0xE6150988
  53. #define RMSTPCR11 0xE615098C
  54. /* System module stop control register */
  55. #define SMSTPCR0 0xE6150130
  56. #define SMSTPCR1 0xE6150134
  57. #define SMSTPCR2 0xE6150138
  58. #define SMSTPCR3 0xE615013C
  59. #define SMSTPCR4 0xE6150140
  60. #define SMSTPCR5 0xE6150144
  61. #define SMSTPCR7 0xE615014C
  62. #define SMSTPCR8 0xE6150990
  63. #define SMSTPCR9 0xE6150994
  64. #define SMSTPCR10 0xE6150998
  65. #define SMSTPCR11 0xE615099C
  66. /*
  67. * SH-I2C
  68. * Ch2 and ch3 are different address. These are defined
  69. * in the header of each SoCs.
  70. */
  71. #define CONFIG_SYS_I2C_SH_BASE0 0xE6500000
  72. #define CONFIG_SYS_I2C_SH_BASE1 0xE6510000
  73. /* RCAR-I2C */
  74. #define CONFIG_SYS_RCAR_I2C0_BASE 0xE6508000
  75. #define CONFIG_SYS_RCAR_I2C1_BASE 0xE6518000
  76. #define CONFIG_SYS_RCAR_I2C2_BASE 0xE6530000
  77. #define CONFIG_SYS_RCAR_I2C3_BASE 0xE6540000
  78. /* SDHI */
  79. #define CONFIG_SYS_SH_SDHI0_BASE 0xEE100000
  80. #define S3C_BASE 0xE6784000
  81. #define S3C_INT_BASE 0xE6784A00
  82. #define S3C_MEDIA_BASE 0xE6784B00
  83. #define S3C_QOS_DCACHE_BASE 0xE6784BDC
  84. #define S3C_QOS_CCI0_BASE 0xE6784C00
  85. #define S3C_QOS_CCI1_BASE 0xE6784C24
  86. #define S3C_QOS_MXI_BASE 0xE6784C48
  87. #define S3C_QOS_AXI_BASE 0xE6784C6C
  88. #define DBSC3_0_QOS_R0_BASE 0xE6791000
  89. #define DBSC3_0_QOS_R1_BASE 0xE6791100
  90. #define DBSC3_0_QOS_R2_BASE 0xE6791200
  91. #define DBSC3_0_QOS_R3_BASE 0xE6791300
  92. #define DBSC3_0_QOS_R4_BASE 0xE6791400
  93. #define DBSC3_0_QOS_R5_BASE 0xE6791500
  94. #define DBSC3_0_QOS_R6_BASE 0xE6791600
  95. #define DBSC3_0_QOS_R7_BASE 0xE6791700
  96. #define DBSC3_0_QOS_R8_BASE 0xE6791800
  97. #define DBSC3_0_QOS_R9_BASE 0xE6791900
  98. #define DBSC3_0_QOS_R10_BASE 0xE6791A00
  99. #define DBSC3_0_QOS_R11_BASE 0xE6791B00
  100. #define DBSC3_0_QOS_R12_BASE 0xE6791C00
  101. #define DBSC3_0_QOS_R13_BASE 0xE6791D00
  102. #define DBSC3_0_QOS_R14_BASE 0xE6791E00
  103. #define DBSC3_0_QOS_R15_BASE 0xE6791F00
  104. #define DBSC3_0_QOS_W0_BASE 0xE6792000
  105. #define DBSC3_0_QOS_W1_BASE 0xE6792100
  106. #define DBSC3_0_QOS_W2_BASE 0xE6792200
  107. #define DBSC3_0_QOS_W3_BASE 0xE6792300
  108. #define DBSC3_0_QOS_W4_BASE 0xE6792400
  109. #define DBSC3_0_QOS_W5_BASE 0xE6792500
  110. #define DBSC3_0_QOS_W6_BASE 0xE6792600
  111. #define DBSC3_0_QOS_W7_BASE 0xE6792700
  112. #define DBSC3_0_QOS_W8_BASE 0xE6792800
  113. #define DBSC3_0_QOS_W9_BASE 0xE6792900
  114. #define DBSC3_0_QOS_W10_BASE 0xE6792A00
  115. #define DBSC3_0_QOS_W11_BASE 0xE6792B00
  116. #define DBSC3_0_QOS_W12_BASE 0xE6792C00
  117. #define DBSC3_0_QOS_W13_BASE 0xE6792D00
  118. #define DBSC3_0_QOS_W14_BASE 0xE6792E00
  119. #define DBSC3_0_QOS_W15_BASE 0xE6792F00
  120. #define DBSC3_0_DBADJ2 0xE67900C8
  121. #define CCI_400_MAXOT_1 0xF0091110
  122. #define CCI_400_MAXOT_2 0xF0092110
  123. #define CCI_400_QOSCNTL_1 0xF009110C
  124. #define CCI_400_QOSCNTL_2 0xF009210C
  125. #define MXI_BASE 0xFE960000
  126. #define MXI_QOS_BASE 0xFE960300
  127. #define SYS_AXI_SYX64TO128_BASE 0xFF800300
  128. #define SYS_AXI_AVB_BASE 0xFF800340
  129. #define SYS_AXI_AX2M_BASE 0xFF800380
  130. #define SYS_AXI_CC50_BASE 0xFF8003C0
  131. #define SYS_AXI_CCI_BASE 0xFF800440
  132. #define SYS_AXI_CS_BASE 0xFF800480
  133. #define SYS_AXI_DDM_BASE 0xFF8004C0
  134. #define SYS_AXI_ETH_BASE 0xFF800500
  135. #define SYS_AXI_G2D_BASE 0xFF800540
  136. #define SYS_AXI_IMP0_BASE 0xFF800580
  137. #define SYS_AXI_IMP1_BASE 0xFF8005C0
  138. #define SYS_AXI_IMUX0_BASE 0xFF800600
  139. #define SYS_AXI_IMUX1_BASE 0xFF800640
  140. #define SYS_AXI_IMUX2_BASE 0xFF800680
  141. #define SYS_AXI_LBS_BASE 0xFF8006C0
  142. #define SYS_AXI_MMUDS_BASE 0xFF800700
  143. #define SYS_AXI_MMUM_BASE 0xFF800740
  144. #define SYS_AXI_MMUR_BASE 0xFF800780
  145. #define SYS_AXI_MMUS0_BASE 0xFF8007C0
  146. #define SYS_AXI_MMUS1_BASE 0xFF800800
  147. #define SYS_AXI_MPXM_BASE 0xFF800840
  148. #define SYS_AXI_MTSB0_BASE 0xFF800880
  149. #define SYS_AXI_MTSB1_BASE 0xFF8008C0
  150. #define SYS_AXI_PCI_BASE 0xFF800900
  151. #define SYS_AXI_RTX_BASE 0xFF800940
  152. #define SYS_AXI_SAT0_BASE 0xFF800980
  153. #define SYS_AXI_SAT1_BASE 0xFF8009C0
  154. #define SYS_AXI_SDM0_BASE 0xFF800A00
  155. #define SYS_AXI_SDM1_BASE 0xFF800A40
  156. #define SYS_AXI_SDS0_BASE 0xFF800A80
  157. #define SYS_AXI_SDS1_BASE 0xFF800AC0
  158. #define SYS_AXI_TRAB_BASE 0xFF800B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
  159. #define SYS_AXI_UDM0_BASE 0xFF800B80
  160. #define SYS_AXI_UDM1_BASE 0xFF800BC0
  161. #define SYS_AXI_USB20_BASE 0xFF800C00
  162. #define SYS_AXI_USB21_BASE 0xFF800C40
  163. #define SYS_AXI_USB22_BASE 0xFF800C80
  164. #define SYS_AXI_USB30_BASE 0xFF800CC0
  165. #define SYS_AXI_ADM_BASE 0xFF800D00
  166. #define SYS_AXI_ADS_BASE 0xFF800D40
  167. #define SYS_AXI_SYX_BASE 0xFF800FB8
  168. #define SYS_AXI_AXI64TO128W_BASE 0xFF801300
  169. #define SYS_AXI_AVBW_BASE 0xFF801340
  170. #define SYS_AXI_CC50W_BASE 0xFF8013C0
  171. #define SYS_AXI_CCIW_BASE 0xFF801440
  172. #define SYS_AXI_CSW_BASE 0xFF801480
  173. #define SYS_AXI_G2DW_BASE 0xFF801540
  174. #define SYS_AXI_IMUX0W_BASE 0xFF801600
  175. #define SYS_AXI_IMUX1W_BASE 0xFF801640
  176. #define SYS_AXI_IMUX2W_BASE 0xFF801680
  177. #define SYS_AXI_LBSW_BASE 0xFF8016C0
  178. #define SYS_AXI_RTXW_BASE 0xFF801940
  179. #define SYS_AXI_SDM0W_BASE 0xFF801A00
  180. #define SYS_AXI_SDM1W_BASE 0xFF801A40
  181. #define SYS_AXI_SDS0W_BASE 0xFF801A80
  182. #define SYS_AXI_SDS1W_BASE 0xFF801AC0
  183. #define SYS_AXI_TRABW_BASE 0xFF801B00 /* SYS_AXI_TRKF_BASE in R*A7794 */
  184. #define SYS_AXI_UDM0W_BASE 0xFF801B80
  185. #define SYS_AXI_UDM1W_BASE 0xFF801BC0
  186. #define SYS_AXI_ADMW_BASE 0xFF801D00
  187. #define SYS_AXI_ADSW_BASE 0xFF801D40
  188. #define SYS_AXI_SYXW_BASE 0xFF801FB8
  189. #define RT_AXI_SHX_BASE 0xFF810100
  190. #define RT_AXI_DBG_BASE 0xFF810140 /* R8A7791 only */
  191. #define RT_AXI_RDM_BASE 0xFF810180 /* R8A7791 only */
  192. #define RT_AXI_RDS_BASE 0xFF8101C0
  193. #define RT_AXI_RTX64TO128_BASE 0xFF810200
  194. #define RT_AXI_STPRO_BASE 0xFF810240
  195. #define RT_AXI_SY2RT_BASE 0xFF810280 /* R8A7791 only */
  196. #define RT_AXI_RT_BASE 0xFF810FC0
  197. #define RT_AXI_SHXW_BASE 0xFF811100
  198. #define RT_AXI_DBGW_BASE 0xFF811140
  199. #define RT_AXI_RTX64TO128W_BASE 0xFF811200
  200. #define RT_AXI_RTW_BASE 0xFF811FC0
  201. #define MP_AXI_ADSP_BASE 0xFF820100
  202. #define MP_AXI_ASDS0_BASE 0xFF8201C0
  203. #define MP_AXI_ASDS1_BASE 0xFF820200
  204. #define MP_AXI_MLP_BASE 0xFF820240
  205. #define MP_AXI_MMUMP_BASE 0xFF820280
  206. #define MP_AXI_SPU_BASE 0xFF8202C0
  207. #define MP_AXI_SPUC_BASE 0xFF820300
  208. #define SYS_AXI256_AXI128TO256_BASE 0xFF860100
  209. #define SYS_AXI256_SYX_BASE 0xFF860140
  210. #define SYS_AXI256_AXM_BASE 0xFF860140
  211. #define SYS_AXI256_MPX_BASE 0xFF860180
  212. #define SYS_AXI256_MXI_BASE 0xFF8601C0
  213. #define SYS_AXI256_IMP0_BASE 0xFF860580
  214. #define SYS_AXI256_SY2_BASE 0xFF860FC0
  215. #define SYS_AXI256_AXI128TO256W_BASE 0xFF861100
  216. #define SYS_AXI256_AXMW_BASE 0xFF861140
  217. #define SYS_AXI256_MXIW_BASE 0xFF8611C0
  218. #define SYS_AXI256_IMP0W_BASE 0xFF861580
  219. #define SYS_AXI256_SY2W_BASE 0xFF861FC0
  220. #define CCI_AXI_MMUS0_BASE 0xFF880100
  221. #define CCI_AXI_SYX2_BASE 0xFF880140
  222. #define CCI_AXI_MMUR_BASE 0xFF880180
  223. #define CCI_AXI_MMUDS_BASE 0xFF8801C0
  224. #define CCI_AXI_MMUM_BASE 0xFF880200
  225. #define CCI_AXI_MXI_BASE 0xFF880240
  226. #define CCI_AXI_MMUS1_BASE 0xFF880280
  227. #define CCI_AXI_MMUMP_BASE 0xFF8802C0
  228. #define MEDIA_AXI_MXR_BASE 0xFE960080 /* R8A7791 only */
  229. #define MEDIA_AXI_MXW_BASE 0xFE9600C0 /* R8A7791 only */
  230. #define MEDIA_AXI_JPR_BASE 0xFE964100
  231. #define MEDIA_AXI_JPW_BASE 0xFE966100
  232. #define MEDIA_AXI_GCU0R_BASE 0xFE964140
  233. #define MEDIA_AXI_GCU0W_BASE 0xFE966140
  234. #define MEDIA_AXI_GCU1R_BASE 0xFE964180
  235. #define MEDIA_AXI_GCU1W_BASE 0xFE966180
  236. #define MEDIA_AXI_TDMR_BASE 0xFE964500
  237. #define MEDIA_AXI_TDMW_BASE 0xFE966500
  238. #define MEDIA_AXI_VSP0CR_BASE 0xFE964540
  239. #define MEDIA_AXI_VSP0CW_BASE 0xFE966540
  240. #define MEDIA_AXI_VSP1CR_BASE 0xFE964580
  241. #define MEDIA_AXI_VSP1CW_BASE 0xFE966580
  242. #define MEDIA_AXI_VSPDU0CR_BASE 0xFE9645C0
  243. #define MEDIA_AXI_VSPDU0CW_BASE 0xFE9665C0
  244. #define MEDIA_AXI_VSPDU1CR_BASE 0xFE964600
  245. #define MEDIA_AXI_VSPDU1CW_BASE 0xFE966600
  246. #define MEDIA_AXI_FDP0R_BASE 0xFE964D40
  247. #define MEDIA_AXI_FDP0W_BASE 0xFE966D40
  248. #define MEDIA_AXI_IMSR_BASE 0xFE964D80
  249. #define MEDIA_AXI_IMSW_BASE 0xFE966D80
  250. #define MEDIA_AXI_VSP1R_BASE 0xFE965100
  251. #define MEDIA_AXI_VSP1W_BASE 0xFE967100
  252. #define MEDIA_AXI_FDP1R_BASE 0xFE965140
  253. #define MEDIA_AXI_FDP1W_BASE 0xFE967140
  254. #define MEDIA_AXI_IMRR_BASE 0xFE965180
  255. #define MEDIA_AXI_IMRW_BASE 0xFE967180
  256. #define MEDIA_AXI_FDP2R_BASE 0xFE9651C0
  257. #define MEDIA_AXI_FDP2W_BASE 0xFE966DC0
  258. #define MEDIA_AXI_DU1R_BASE 0xFE9655C0
  259. #define MEDIA_AXI_DU1W_BASE 0xFE9675C0
  260. #define MEDIA_AXI_VCP0CR_BASE 0xFE965900
  261. #define MEDIA_AXI_VCP0CW_BASE 0xFE967900
  262. #define MEDIA_AXI_VCP0VR_BASE 0xFE965940
  263. #define MEDIA_AXI_VCP0VW_BASE 0xFE967940
  264. #define MEDIA_AXI_VPC0R_BASE 0xFE965980
  265. #define MEDIA_AXI_VCP1CR_BASE 0xFE965D00
  266. #define MEDIA_AXI_VCP1CW_BASE 0xFE967D00
  267. #define MEDIA_AXI_VCP1VR_BASE 0xFE965D40
  268. #define MEDIA_AXI_VCP1VW_BASE 0xFE967D40
  269. #define MEDIA_AXI_VPC1R_BASE 0xFE965D80
  270. #if defined (CONFIG_R8A7792)
  271. #define MEDIA_AXI_VCTU0R_BASE 0xFE964500 /* R8A7792 */
  272. #define MEDIA_AXI_VCTU0W_BASE 0xFE966500
  273. #define MEDIA_AXI_VDCTU0R_BASE 0xFE964540
  274. #define MEDIA_AXI_VDCTU0W_BASE 0xFE966540
  275. #define MEDIA_AXI_VDCTU1R_BASE 0xFE964580
  276. #define MEDIA_AXI_VDCTU1W_BASE 0xFE966580
  277. #define MEDIA_AXI_VIN0W_BASE 0xFE967580
  278. #define MEDIA_AXI_VIN1W_BASE 0xFE966D80
  279. #define MEDIA_AXI_RDRW_BASE 0xFE9675C0
  280. #define MEDIA_AXI_IMS01R_BASE 0xFE965500
  281. #define MEDIA_AXI_IMS01W_BASE 0xFE967500
  282. #define MEDIA_AXI_IMS23R_BASE 0xFE965540 /* FIXME */
  283. #define MEDIA_AXI_IMS23W_BASE 0xFE967540
  284. #define MEDIA_AXI_IMS45R_BASE 0xFE964D00
  285. #define MEDIA_AXI_IMS45W_BASE 0xFE966D00
  286. #define MEDIA_AXI_ROTCE4R_BASE 0xFE965100
  287. #define MEDIA_AXI_ROTCE4W_BASE 0xFE967100
  288. #define MEDIA_AXI_ROTVLC4R_BASE 0xFE965140
  289. #define MEDIA_AXI_ROTVLC4W_BASE 0xFE965140
  290. #define MEDIA_AXI_VSPD0R_BASE 0xFE964900
  291. #define MEDIA_AXI_VSPD0W_BASE 0xFE966900
  292. #define MEDIA_AXI_VSPD1R_BASE 0xFE964940
  293. #define MEDIA_AXI_VSPD1W_BASE 0xFE966940
  294. #define MEDIA_AXI_DU0R_BASE 0xFE964980
  295. #define MEDIA_AXI_DU0W_BASE 0xFE966980
  296. #define MEDIA_AXI_VSP0R_BASE 0xFE9649C0
  297. #define MEDIA_AXI_VSP0W_BASE 0xFE9669C0
  298. #define MEDIA_AXI_ROTCE0R_BASE 0xFE965900
  299. #define MEDIA_AXI_ROTCE0W_BASE 0xFE967900
  300. #define MEDIA_AXI_ROTVLC0R_BASE 0xFE965940
  301. #define MEDIA_AXI_ROTVLC0W_BASE 0xFE967940
  302. #define MEDIA_AXI_ROTCE1R_BASE 0xFE965980
  303. #define MEDIA_AXI_ROTCE1W_BASE 0xFE967980
  304. #define MEDIA_AXI_ROTVLC1R_BASE 0xFE9659C0
  305. #define MEDIA_AXI_ROTVLC1W_BASE 0xFE9679C0
  306. #define MEDIA_AXI_ROTCE2R_BASE 0xFE965D00
  307. #define MEDIA_AXI_ROTCE2W_BASE 0xFE967D00
  308. #define MEDIA_AXI_ROTVLC2R_BASE 0xFE965D40
  309. #define MEDIA_AXI_ROTVLC2W_BASE 0xFE967D40
  310. #define MEDIA_AXI_ROTCE3R_BASE 0xFE965D80
  311. #define MEDIA_AXI_ROTCE3W_BASE 0xFE967D80
  312. #define MEDIA_AXI_ROTVLC3R_BASE 0xFE965DC0
  313. #define MEDIA_AXI_ROTVLC3W_BASE 0xFE967DC0
  314. #else /* R8A7792 */
  315. #define MEDIA_AXI_VIN0W_BASE 0xFE966900
  316. #define MEDIA_AXI_VSPD0R_BASE 0xFE965500
  317. #define MEDIA_AXI_VSPD0W_BASE 0xFE967500
  318. #define MEDIA_AXI_VSPD1R_BASE 0xFE965540
  319. #define MEDIA_AXI_VSPD1W_BASE 0xFE967540
  320. #define MEDIA_AXI_DU0R_BASE 0xFE965580
  321. #define MEDIA_AXI_DU0W_BASE 0xFE967580
  322. #define MEDIA_AXI_VSP0R_BASE 0xFE964D00
  323. #define MEDIA_AXI_VSP0W_BASE 0xFE966D00
  324. #endif /* R8A7792 */
  325. #define SYS_AXI_AVBDMSCR 0xFF802000
  326. #define SYS_AXI_SYX2DMSCR 0xFF802004
  327. #define SYS_AXI_AX2MDMSCR 0xFF802004
  328. #define SYS_AXI_CC50DMSCR 0xFF802008
  329. #define SYS_AXI_CC51DMSCR 0xFF80200C
  330. #define SYS_AXI_CCIDMSCR 0xFF802010
  331. #define SYS_AXI_CSDMSCR 0xFF802014
  332. #define SYS_AXI_DDMDMSCR 0xFF802018
  333. #define SYS_AXI_ETHDMSCR 0xFF80201C
  334. #define SYS_AXI_G2DDMSCR 0xFF802020
  335. #define SYS_AXI_IMP0DMSCR 0xFF802024
  336. #define SYS_AXI_IMP1DMSCR 0xFF802028
  337. #define SYS_AXI_LBSDMSCR 0xFF80202C
  338. #define SYS_AXI_MMUDSDMSCR 0xFF802030
  339. #define SYS_AXI_MMUMXDMSCR 0xFF802034
  340. #define SYS_AXI_MMURDDMSCR 0xFF802038
  341. #define SYS_AXI_MMUS0DMSCR 0xFF80203C
  342. #define SYS_AXI_MMUS1DMSCR 0xFF802040
  343. #define SYS_AXI_MPXDMSCR 0xFF802044
  344. #define SYS_AXI_MTSB0DMSCR 0xFF802048
  345. #define SYS_AXI_MTSB1DMSCR 0xFF80204C
  346. #define SYS_AXI_PCIDMSCR 0xFF802050
  347. #define SYS_AXI_RTXDMSCR 0xFF802054
  348. #define SYS_AXI_SAT0DMSCR 0xFF802058
  349. #define SYS_AXI_SAT1DMSCR 0xFF80205C
  350. #define SYS_AXI_SDM0DMSCR 0xFF802060
  351. #define SYS_AXI_SDM1DMSCR 0xFF802064
  352. #define SYS_AXI_SDS0DMSCR 0xFF802068
  353. #define SYS_AXI_SDS1DMSCR 0xFF80206C
  354. #define SYS_AXI_ETRABDMSCR 0xFF802070
  355. #define SYS_AXI_ETRKFDMSCR 0xFF802074
  356. #define SYS_AXI_UDM0DMSCR 0xFF802078
  357. #define SYS_AXI_UDM1DMSCR 0xFF80207C
  358. #define SYS_AXI_USB20DMSCR 0xFF802080
  359. #define SYS_AXI_USB21DMSCR 0xFF802084
  360. #define SYS_AXI_USB22DMSCR 0xFF802088
  361. #define SYS_AXI_USB30DMSCR 0xFF80208C
  362. #define SYS_AXI_X128TO64SLVDMSCR 0xFF802100
  363. #define SYS_AXI_X64TO128SLVDMSCR 0xFF802104
  364. #define SYS_AXI_AVBSLVDMSCR 0xFF802108
  365. #define SYS_AXI_SYX2SLVDMSCR 0xFF80210C
  366. #define SYS_AXI_AX2SLVDMSCR 0xFF80210C
  367. #define SYS_AXI_ETHSLVDMSCR 0xFF802110
  368. #define SYS_AXI_GICSLVDMSCR 0xFF802114
  369. #define SYS_AXI_IMPSLVDMSCR 0xFF802118
  370. #define SYS_AXI_IMX0SLVDMSCR 0xFF80211C
  371. #define SYS_AXI_IMX1SLVDMSCR 0xFF802120
  372. #define SYS_AXI_IMX2SLVDMSCR 0xFF802124
  373. #define SYS_AXI_LBSSLVDMSCR 0xFF802128
  374. #define SYS_AXI_MMC0SLVDMSCR 0xFF80212C
  375. #define SYS_AXI_MMC1SLVDMSCR 0xFF802130
  376. #define SYS_AXI_MPXSLVDMSCR 0xFF802134
  377. #define SYS_AXI_MTSB0SLVDMSCR 0xFF802138
  378. #define SYS_AXI_MTSB1SLVDMSCR 0xFF80213C
  379. #define SYS_AXI_MXTSLVDMSCR 0xFF802140
  380. #define SYS_AXI_PCISLVDMSCR 0xFF802144
  381. #define SYS_AXI_SYAPBSLVDMSCR 0xFF802148
  382. #define SYS_AXI_QSAPBSLVDMSCR 0xFF80214C
  383. #define SYS_AXI_RTXSLVDMSCR 0xFF802150
  384. #define SYS_AXI_SAPC1SLVDMSCR 0xFF802154
  385. #define SYS_AXI_SAPC2SLVDMSCR 0xFF802158
  386. #define SYS_AXI_SAPC3SLVDMSCR 0xFF80215C
  387. #define SYS_AXI_SAPC65SLVDMSCR 0xFF802160
  388. #define SYS_AXI_SAPC8SLVDMSCR 0xFF802164
  389. #define SYS_AXI_SAT0SLVDMSCR 0xFF802168
  390. #define SYS_AXI_SAT1SLVDMSCR 0xFF80216C
  391. #define SYS_AXI_SDAP0SLVDMSCR 0xFF802170
  392. #define SYS_AXI_SDAP1SLVDMSCR 0xFF802174
  393. #define SYS_AXI_SDAP2SLVDMSCR 0xFF802178
  394. #define SYS_AXI_SDAP3SLVDMSCR 0xFF80217C
  395. #define SYS_AXI_SGXSLVDMSCR 0xFF802180
  396. #define SYS_AXI_SGXSLV1SLVDMSCR 0xFF802184
  397. #define SYS_AXI_STBSLVDMSCR 0xFF802188
  398. #define SYS_AXI_STMSLVDMSCR 0xFF80218C
  399. #define SYS_AXI_SYXXDEFAULTSLAVESLVDMSCR 0xFF802190
  400. #define SYS_AXI_TSPL0SLVDMSCR 0xFF802194
  401. #define SYS_AXI_TSPL1SLVDMSCR 0xFF802198
  402. #define SYS_AXI_TSPL2SLVDMSCR 0xFF80219C
  403. #define SYS_AXI_USB20SLVDMSCR 0xFF8021A0
  404. #define SYS_AXI_USB21SLVDMSCR 0xFF8021A4
  405. #define SYS_AXI_USB22SLVDMSCR 0xFF8021A8
  406. #define SYS_AXI_USB30SLVDMSCR 0xFF8021AC
  407. #define SYS_AXI_UTLBDSSLVDMSCR 0xFF8021B0
  408. #define SYS_AXI_UTLBS0SLVDMSCR 0xFF8021B4
  409. #define SYS_AXI_UTLBS1SLVDMSCR 0xFF8021B8
  410. #define SYS_AXI_ROT0DMSCR 0xFF802320
  411. #define SYS_AXI_ROT1DMSCR 0xFF802324
  412. #define SYS_AXI_ROT2DMSCR 0xFF802328
  413. #define SYS_AXI_ROT3DMSCR 0xFF80232C
  414. #define SYS_AXI_ROT4DMSCR 0xFF802330
  415. #define SYS_AXI_IMUX3SLVDMSCR 0xFF802334
  416. #define SYS_AXI_STBR0SLVDMSCR 0xFF803200
  417. #define SYS_AXI_STBR0PSLVDMSCR 0xFF803204
  418. #define SYS_AXI_STBR0XSLVDMSCR 0xFF803208
  419. #define SYS_AXI_STBR1SLVDMSCR 0xFF803210
  420. #define SYS_AXI_STBR1PSLVDMSCR 0xFF803214
  421. #define SYS_AXI_STBR1XSLVDMSCR 0xFF803218
  422. #define SYS_AXI_STBR2SLVDMSCR 0xFF803220
  423. #define SYS_AXI_STBR2PSLVDMSCR 0xFF803224
  424. #define SYS_AXI_STBR2XSLVDMSCR 0xFF803228
  425. #define SYS_AXI_STBR3SLVDMSCR 0xFF803230
  426. #define SYS_AXI_STBR3PSLVDMSCR 0xFF803234
  427. #define SYS_AXI_STBR3XSLVDMSCR 0xFF803238
  428. #define SYS_AXI_STBR4SLVDMSCR 0xFF803240
  429. #define SYS_AXI_STBR4PSLVDMSCR 0xFF803244
  430. #define SYS_AXI_STBR4XSLVDMSCR 0xFF803248
  431. #define SYS_AXI_ADM_DMSCR 0xFF803260
  432. #define SYS_AXI_ADS_DMSCR 0xFF803264
  433. #define RT_AXI_CBMDMSCR 0xFF812000
  434. #define RT_AXI_DBDMSCR 0xFF812004
  435. #define RT_AXI_RDMDMSCR 0xFF812008
  436. #define RT_AXI_RDSDMSCR 0xFF81200C
  437. #define RT_AXI_STRDMSCR 0xFF812010
  438. #define RT_AXI_SY2RTDMSCR 0xFF812014
  439. #define RT_AXI_CBSSLVDMSCR 0xFF812100
  440. #define RT_AXI_DBSSLVDMSCR 0xFF812104
  441. #define RT_AXI_RTAP1SLVDMSCR 0xFF812108
  442. #define RT_AXI_RTAP2SLVDMSCR 0xFF81210C
  443. #define RT_AXI_RTAP3SLVDMSCR 0xFF812110
  444. #define RT_AXI_RT2SYSLVDMSCR 0xFF812114
  445. #define RT_AXI_A128TO64SLVDMSCR 0xFF812118
  446. #define RT_AXI_A64TO128SLVDMSCR 0xFF81211C
  447. #define RT_AXI_A64TO128CSLVDMSCR 0xFF812120
  448. #define RT_AXI_UTLBRSLVDMSCR 0xFF812128
  449. #define MP_AXI_ADSPDMSCR 0xFF822000
  450. #define MP_AXI_ASDM0DMSCR 0xFF822004
  451. #define MP_AXI_ASDM1DMSCR 0xFF822008
  452. #define MP_AXI_ASDS0DMSCR 0xFF82200C
  453. #define MP_AXI_ASDS1DMSCR 0xFF822010
  454. #define MP_AXI_MLPDMSCR 0xFF822014
  455. #define MP_AXI_MMUMPDMSCR 0xFF822018
  456. #define MP_AXI_SPUDMSCR 0xFF82201C
  457. #define MP_AXI_SPUCDMSCR 0xFF822020
  458. #define MP_AXI_SY2MPDMSCR 0xFF822024
  459. #define MP_AXI_ADSPSLVDMSCR 0xFF822100
  460. #define MP_AXI_MLMSLVDMSCR 0xFF822104
  461. #define MP_AXI_MPAP4SLVDMSCR 0xFF822108
  462. #define MP_AXI_MPAP5SLVDMSCR 0xFF82210C
  463. #define MP_AXI_MPAP6SLVDMSCR 0xFF822110
  464. #define MP_AXI_MPAP7SLVDMSCR 0xFF822114
  465. #define MP_AXI_MP2SYSLVDMSCR 0xFF822118
  466. #define MP_AXI_MP2SY2SLVDMSCR 0xFF82211C
  467. #define MP_AXI_MPXAPSLVDMSCR 0xFF822124
  468. #define MP_AXI_SPUSLVDMSCR 0xFF822128
  469. #define MP_AXI_UTLBMPSLVDMSCR 0xFF82212C
  470. #define ADM_AXI_ASDM0DMSCR 0xFF842000
  471. #define ADM_AXI_ASDM1DMSCR 0xFF842004
  472. #define ADM_AXI_MPAP1SLVDMSCR 0xFF842104
  473. #define ADM_AXI_MPAP2SLVDMSCR 0xFF842108
  474. #define ADM_AXI_MPAP3SLVDMSCR 0xFF84210C
  475. #define DM_AXI_DMAXICONF 0xFF850000
  476. #define DM_AXI_DMAPBCONF 0xFF850004
  477. #define DM_AXI_DMADMCONF 0xFF850020
  478. #define DM_AXI_DMSDM0CONF 0xFF850024
  479. #define DM_AXI_DMSDM1CONF 0xFF850028
  480. #define DM_AXI_DMQSPAPSLVCONF 0xFF850030
  481. #define DM_AXI_RAPD4SLVCONF 0xFF850034
  482. #define DM_AXI_SAPD4SLVCONF 0xFF85003C
  483. #define DM_AXI_SAPD5SLVCONF 0xFF850040
  484. #define DM_AXI_SAPD6SLVCONF 0xFF850044
  485. #define DM_AXI_SAPD65DSLVCONF 0xFF850048
  486. #define DM_AXI_SDAP0SLVCONF 0xFF85004C
  487. #define DM_AXI_MAPD2SLVCONF 0xFF850050
  488. #define DM_AXI_MAPD3SLVCONF 0xFF850054
  489. #define DM_AXI_DMXXDEFAULTSLAVESLVCONF 0xFF850058
  490. #define DM_AXI_DMADMRQOSCONF 0xFF850100
  491. #define DM_AXI_DMADMRQOSCTSET0 0xFF850104
  492. #define DM_AXI_DMADMRQOSREQCTR 0xFF850114
  493. #define DM_AXI_DMADMRQOSQON 0xFF850124
  494. #define DM_AXI_DMADMRQOSIN 0xFF850128
  495. #define DM_AXI_DMADMRQOSSTAT 0xFF85012C
  496. #define DM_AXI_DMSDM0RQOSCONF 0xFF850140
  497. #define DM_AXI_DMSDM0RQOSCTSET0 0xFF850144
  498. #define DM_AXI_DMSDM0RQOSREQCTR 0xFF850154
  499. #define DM_AXI_DMSDM0RQOSQON 0xFF850164
  500. #define DM_AXI_DMSDM0RQOSIN 0xFF850168
  501. #define DM_AXI_DMSDM0RQOSSTAT 0xFF85016C
  502. #define DM_AXI_DMSDM1RQOSCONF 0xFF850180
  503. #define DM_AXI_DMSDM1RQOSCTSET0 0xFF850184
  504. #define DM_AXI_DMSDM1RQOSREQCTR 0xFF850194
  505. #define DM_AXI_DMSDM1RQOSQON 0xFF8501A4
  506. #define DM_AXI_DMSDM1RQOSIN 0xFF8501A8
  507. #define DM_AXI_DMSDM1RQOSSTAT 0xFF8501AC
  508. #define DM_AXI_DMRQOSCTSET1 0xFF850FC0
  509. #define DM_AXI_DMRQOSCTSET2 0xFF850FC4
  510. #define DM_AXI_DMRQOSCTSET3 0xFF850FC8
  511. #define DM_AXI_DMRQOSTHRES0 0xFF850FCC
  512. #define DM_AXI_DMRQOSTHRES1 0xFF850FD0
  513. #define DM_AXI_DMRQOSTHRES2 0xFF850FD4
  514. #define DM_AXI_DMADMWQOSCONF 0xFF851100
  515. #define DM_AXI_DMADMWQOSCTSET0 0xFF851104
  516. #define DM_AXI_DMADMWQOSREQCTR 0xFF851114
  517. #define DM_AXI_DMADMWQOSQON 0xFF851124
  518. #define DM_AXI_DMADMWQOSIN 0xFF851128
  519. #define DM_AXI_DMADMWQOSSTAT 0xFF85112C
  520. #define DM_AXI_DMSDM0WQOSCONF 0xFF851140
  521. #define DM_AXI_DMSDM0WQOSCTSET0 0xFF851144
  522. #define DM_AXI_DMSDM0WQOSREQCTR 0xFF851154
  523. #define DM_AXI_DMSDM0WQOSQON 0xFF851164
  524. #define DM_AXI_DMSDM0WQOSIN 0xFF851168
  525. #define DM_AXI_DMSDM0WQOSSTAT 0xFF85116C
  526. #define DM_AXI_DMSDM1WQOSCONF 0xFF851180
  527. #define DM_AXI_DMSDM1WQOSCTSET0 0xFF851184
  528. #define DM_AXI_DMSDM1WQOSREQCTR 0xFF851194
  529. #define DM_AXI_DMSDM1WQOSQON 0xFF8511A4
  530. #define DM_AXI_DMSDM1WQOSIN 0xFF8511A8
  531. #define DM_AXI_DMSDM1WQOSSTAT 0xFF8511AC
  532. #define DM_AXI_DMWQOSCTSET1 0xFF851FC0
  533. #define DM_AXI_DMWQOSCTSET2 0xFF851FC4
  534. #define DM_AXI_DMWQOSCTSET3 0xFF851FC8
  535. #define DM_AXI_DMWQOSTHRES0 0xFF851FCC
  536. #define DM_AXI_DMWQOSTHRES1 0xFF851FD0
  537. #define DM_AXI_DMWQOSTHRES2 0xFF851FD4
  538. #define DM_AXI_RDMDMSCR 0xFF852000
  539. #define DM_AXI_SDM0DMSCR 0xFF852004
  540. #define DM_AXI_SDM1DMSCR 0xFF852008
  541. #if defined(CONFIG_R8A7792)
  542. #define DM_AXI_DMQSPAPSLVDMSCR 0xFF852104
  543. #define DM_AXI_RAPD4SLVDMSCR 0xFF852108
  544. #define DM_AXI_SAPD4SLVDMSCR 0xFF852110
  545. #define DM_AXI_SAPD5SLVDMSCR 0xFF852114
  546. #define DM_AXI_SAPD6SLVDMSCR 0xFF852118
  547. #define DM_AXI_SAPD65DSLVDMSCR 0xFF85211C
  548. #define DM_AXI_SDAP0SLVDMSCR 0xFF852120
  549. #define DM_AXI_MAPD2SLVDMSCR 0xFF852124
  550. #define DM_AXI_MAPD3SLVDMSCR 0xFF852128
  551. #define DM_AXI_DMXXDEFAULTSLAVESLVDMSCR 0xFF85212C
  552. #define DM_AXI_DMXREGDMSENN 0xFF852200
  553. #else
  554. #define DM_AXI_MMAP0SLVDMSCR 0xFF852100
  555. #define DM_AXI_MMAP1SLVDMSCR 0xFF852104
  556. #define DM_AXI_QSPAPSLVDMSCR 0xFF852108
  557. #define DM_AXI_RAP4SLVDMSCR 0xFF85210C
  558. #define DM_AXI_RAP5SLVDMSCR 0xFF852110
  559. #define DM_AXI_SAP4SLVDMSCR 0xFF852114
  560. #define DM_AXI_SAP5SLVDMSCR 0xFF852118
  561. #define DM_AXI_SAP6SLVDMSCR 0xFF85211C
  562. #define DM_AXI_SAP65SLVDMSCR 0xFF852120
  563. #define DM_AXI_SDAP0SLVDMSCR 0xFF852124
  564. #define DM_AXI_SDAP1SLVDMSCR 0xFF852128
  565. #define DM_AXI_SDAP2SLVDMSCR 0xFF85212C
  566. #define DM_AXI_SDAP3SLVDMSCR 0xFF852130
  567. #endif
  568. #define SYS_AXI256_SYXDMSCR 0xFF862000
  569. #define SYS_AXI256_MPXDMSCR 0xFF862004
  570. #define SYS_AXI256_MXIDMSCR 0xFF862008
  571. #define SYS_AXI256_X128TO256SLVDMSCR 0xFF862100
  572. #define SYS_AXI256_X256TO128SLVDMSCR 0xFF862104
  573. #define SYS_AXI256_SYXSLVDMSCR 0xFF862108
  574. #define SYS_AXI256_CCXSLVDMSCR 0xFF86210C
  575. #define SYS_AXI256_S3CSLVDMSCR 0xFF862110
  576. #define MXT_SYXDMSCR 0xFF872000
  577. #if defined(CONFIG_R8A7792)
  578. #define MXT_IMRSLVDMSCR 0xFF872110
  579. #define MXT_VINSLVDMSCR 0xFF872114
  580. #define MXT_VSP1SLVDMSCR 0xFF87211C
  581. #define MXT_VSPD0SLVDMSCR 0xFF872120
  582. #define MXT_VSPD1SLVDMSCR 0xFF872124
  583. #define MXT_MAP1SLVDMSCR 0xFF872128
  584. #define MXT_MAP2SLVDMSCR 0xFF87212C
  585. #define MXT_MAP2BSLVDMSCR 0xFF872134
  586. #else /* R8A7792 */
  587. #define MXT_CMM0SLVDMSCR 0xFF872100
  588. #define MXT_CMM1SLVDMSCR 0xFF872104
  589. #define MXT_CMM2SLVDMSCR 0xFF872108
  590. #define MXT_FDPSLVDMSCR 0xFF87210C
  591. #define MXT_IMRSLVDMSCR 0xFF872110
  592. #define MXT_VINSLVDMSCR 0xFF872114
  593. #define MXT_VPC0SLVDMSCR 0xFF872118
  594. #define MXT_VPC1SLVDMSCR 0xFF87211C
  595. #define MXT_VSP0SLVDMSCR 0xFF872120
  596. #define MXT_VSP1SLVDMSCR 0xFF872124
  597. #define MXT_VSPD0SLVDMSCR 0xFF872128
  598. #define MXT_VSPD1SLVDMSCR 0xFF87212C
  599. #define MXT_MAP1SLVDMSCR 0xFF872130
  600. #define MXT_MAP2SLVDMSCR 0xFF872134
  601. #endif /* R8A7792 */
  602. /* DMS Register (MXI) */
  603. #if defined(CONFIG_R8A7792)
  604. #define MXI_JPURDMSCR 0xFE964200
  605. #define MXI_JPUWDMSCR 0xFE966200
  606. #define MXI_VCTU0RDMSCR 0xFE964600
  607. #define MXI_VCTU0WDMSCR 0xFE966600
  608. #define MXI_VDCTU0RDMSCR 0xFE964604
  609. #define MXI_VDCTU0WDMSCR 0xFE966604
  610. #define MXI_VDCTU1RDMSCR 0xFE964608
  611. #define MXI_VDCTU1WDMSCR 0xFE966608
  612. #define MXI_VIN0WDMSCR 0xFE967608
  613. #define MXI_VIN1WDMSCR 0xFE966E08
  614. #define MXI_RDRWDMSCR 0xFE96760C
  615. #define MXI_IMS01RDMSCR 0xFE965600
  616. #define MXI_IMS01WDMSCR 0xFE967600
  617. #define MXI_IMS23RDMSCR 0xFE965604
  618. #define MXI_IMS23WDMSCR 0xFE967604
  619. #define MXI_IMS45RDMSCR 0xFE964E00
  620. #define MXI_IMS45WDMSCR 0xFE966E00
  621. #define MXI_IMRRDMSCR 0xFE964E04
  622. #define MXI_IMRWDMSCR 0xFE966E04
  623. #define MXI_ROTCE4RDMSCR 0xFE965200
  624. #define MXI_ROTCE4WDMSCR 0xFE967200
  625. #define MXI_ROTVLC4RDMSCR 0xFE965204
  626. #define MXI_ROTVLC4WDMSCR 0xFE967204
  627. #define MXI_VSPD0RDMSCR 0xFE964A00
  628. #define MXI_VSPD0WDMSCR 0xFE966A00
  629. #define MXI_VSPD1RDMSCR 0xFE964A04
  630. #define MXI_VSPD1WDMSCR 0xFE966A04
  631. #define MXI_DU0RDMSCR 0xFE964A08
  632. #define MXI_DU0WDMSCR 0xFE966A08
  633. #define MXI_VSP0RDMSCR 0xFE964A0C
  634. #define MXI_VSP0WDMSCR 0xFE966A0C
  635. #define MXI_ROTCE0RDMSCR 0xFE965A00
  636. #define MXI_ROTCE0WDMSCR 0xFE967A00
  637. #define MXI_ROTVLC0RDMSCR 0xFE965A04
  638. #define MXI_ROTVLC0WDMSCR 0xFE967A04
  639. #define MXI_ROTCE1RDMSCR 0xFE965A08
  640. #define MXI_ROTCE1WDMSCR 0xFE967A08
  641. #define MXI_ROTVLC1RDMSCR 0xFE965A0C
  642. #define MXI_ROTVLC1WDMSCR 0xFE967A0C
  643. #define MXI_ROTCE2RDMSCR 0xFE965E00
  644. #define MXI_ROTCE2WDMSCR 0xFE967E00
  645. #define MXI_ROTVLC2RDMSCR 0xFE965E04
  646. #define MXI_ROTVLC2WDMSCR 0xFE967E04
  647. #define MXI_ROTCE3RDMSCR 0xFE965E08
  648. #define MXI_ROTCE3WDMSCR 0xFE967E08
  649. #define MXI_ROTVLC3RDMSCR 0xFE965E0C
  650. #define MXI_ROTVLC3WDMSCR 0xFE967E0C
  651. #endif /* R8A7792 */
  652. #define CCI_AXI_MMUS0DMSCR 0xFF882000
  653. #define CCI_AXI_SYX2DMSCR 0xFF882004
  654. #define CCI_AXI_MMURDMSCR 0xFF882008
  655. #define CCI_AXI_MMUDSDMSCR 0xFF88200C
  656. #define CCI_AXI_MMUMDMSCR 0xFF882010
  657. #define CCI_AXI_MXIDMSCR 0xFF882014
  658. #define CCI_AXI_MMUS1DMSCR 0xFF882018
  659. #define CCI_AXI_MMUMPDMSCR 0xFF88201C
  660. #define CCI_AXI_DVMDMSCR 0xFF882020
  661. #define CCI_AXI_CCISLVDMSCR 0xFF882100
  662. #define CCI_AXI_IPMMUIDVMCR 0xFF880400
  663. #define CCI_AXI_IPMMURDVMCR 0xFF880404
  664. #define CCI_AXI_IPMMUS0DVMCR 0xFF880408
  665. #define CCI_AXI_IPMMUS1DVMCR 0xFF88040C
  666. #define CCI_AXI_IPMMUMPDVMCR 0xFF880410
  667. #define CCI_AXI_IPMMUDSDVMCR 0xFF880414
  668. #define CCI_AXI_AX2ADDRMASK 0xFF88041C
  669. #define PLL0CR 0xE61500D8
  670. #define PLL0_STC_MASK 0x7F000000
  671. #define PLL0_STC_BIT 24
  672. #define PLLECR 0xE61500D0
  673. #define PLL0ST 0x100
  674. #ifndef __ASSEMBLY__
  675. #include <asm/types.h>
  676. /* RWDT */
  677. struct rcar_rwdt {
  678. u32 rwtcnt; /* 0x00 */
  679. u32 rwtcsra; /* 0x04 */
  680. u16 rwtcsrb; /* 0x08 */
  681. };
  682. /* SWDT */
  683. struct rcar_swdt {
  684. u32 swtcnt; /* 0x00 */
  685. u32 swtcsra; /* 0x04 */
  686. u16 swtcsrb; /* 0x08 */
  687. };
  688. /* LBSC */
  689. struct rcar_lbsc {
  690. u32 cs0ctrl;
  691. u32 cs1ctrl;
  692. u32 ecs0ctrl;
  693. u32 ecs1ctrl;
  694. u32 ecs2ctrl;
  695. u32 ecs3ctrl;
  696. u32 ecs4ctrl;
  697. u32 ecs5ctrl;
  698. u32 dummy0[4]; /* 0x20 .. 0x2C */
  699. u32 cswcr0;
  700. u32 cswcr1;
  701. u32 ecswcr0;
  702. u32 ecswcr1;
  703. u32 ecswcr2;
  704. u32 ecswcr3;
  705. u32 ecswcr4;
  706. u32 ecswcr5;
  707. u32 exdmawcr0;
  708. u32 exdmawcr1;
  709. u32 exdmawcr2;
  710. u32 dummy1[9]; /* 0x5C .. 0x7C */
  711. u32 cspwcr0;
  712. u32 cspwcr1;
  713. u32 ecspwcr0;
  714. u32 ecspwcr1;
  715. u32 ecspwcr2;
  716. u32 ecspwcr3;
  717. u32 ecspwcr4;
  718. u32 ecspwcr5;
  719. u32 exwtsync;
  720. u32 dummy2[3]; /* 0xA4 .. 0xAC */
  721. u32 cs0bstctl;
  722. u32 cs0btph;
  723. u32 dummy3[2]; /* 0xB8 .. 0xBC */
  724. u32 cs1gdst;
  725. u32 ecs0gdst;
  726. u32 ecs1gdst;
  727. u32 ecs2gdst;
  728. u32 ecs3gdst;
  729. u32 ecs4gdst;
  730. u32 ecs5gdst;
  731. u32 dummy4[5]; /* 0xDC .. 0xEC */
  732. u32 exdmaset0;
  733. u32 exdmaset1;
  734. u32 exdmaset2;
  735. u32 dummy5[5]; /* 0xFC .. 0x10C */
  736. u32 exdmcr0;
  737. u32 exdmcr1;
  738. u32 exdmcr2;
  739. u32 dummy6[5]; /* 0x11C .. 0x12C */
  740. u32 bcintsr;
  741. u32 bcintcr;
  742. u32 bcintmr;
  743. u32 dummy7; /* 0x13C */
  744. u32 exbatlv;
  745. u32 exwtsts;
  746. u32 dummy8[14]; /* 0x148 .. 0x17C */
  747. u32 atacsctrl;
  748. u32 dummy9[15]; /* 0x184 .. 0x1BC */
  749. u32 exbct;
  750. u32 extct;
  751. };
  752. /* DBSC3 */
  753. struct rcar_dbsc3 {
  754. u32 dummy0[3]; /* 0x00 .. 0x08 */
  755. u32 dbstate1;
  756. u32 dbacen;
  757. u32 dbrfen;
  758. u32 dbcmd;
  759. u32 dbwait;
  760. u32 dbkind;
  761. u32 dbconf0;
  762. u32 dummy1[2]; /* 0x28 .. 0x2C */
  763. u32 dbphytype;
  764. u32 dummy2[3]; /* 0x34 .. 0x3C */
  765. u32 dbtr0;
  766. u32 dbtr1;
  767. u32 dbtr2;
  768. u32 dummy3; /* 0x4C */
  769. u32 dbtr3;
  770. u32 dbtr4;
  771. u32 dbtr5;
  772. u32 dbtr6;
  773. u32 dbtr7;
  774. u32 dbtr8;
  775. u32 dbtr9;
  776. u32 dbtr10;
  777. u32 dbtr11;
  778. u32 dbtr12;
  779. u32 dbtr13;
  780. u32 dbtr14;
  781. u32 dbtr15;
  782. u32 dbtr16;
  783. u32 dbtr17;
  784. u32 dbtr18;
  785. u32 dbtr19;
  786. u32 dummy4[7]; /* 0x94 .. 0xAC */
  787. u32 dbbl;
  788. u32 dummy5[3]; /* 0xB4 .. 0xBC */
  789. u32 dbadj0;
  790. u32 dummy6; /* 0xC4 */
  791. u32 dbadj2;
  792. u32 dummy7[5]; /* 0xCC .. 0xDC */
  793. u32 dbrfcnf0;
  794. u32 dbrfcnf1;
  795. u32 dbrfcnf2;
  796. u32 dummy8[2]; /* 0xEC .. 0xF0 */
  797. u32 dbcalcnf;
  798. u32 dbcaltr;
  799. u32 dummy9; /* 0xFC */
  800. u32 dbrnk0;
  801. u32 dummy10[31]; /* 0x104 .. 0x17C */
  802. u32 dbpdncnf;
  803. u32 dummy11[47]; /* 0x184 ..0x23C */
  804. u32 dbdfistat;
  805. u32 dbdficnt;
  806. u32 dummy12[14]; /* 0x248 .. 0x27C */
  807. u32 dbpdlck;
  808. u32 dummy13[3]; /* 0x284 .. 0x28C */
  809. u32 dbpdrga;
  810. u32 dummy14[3]; /* 0x294 .. 0x29C */
  811. u32 dbpdrgd;
  812. u32 dummy15[24]; /* 0x2A4 .. 0x300 */
  813. u32 dbbs0cnt1;
  814. u32 dummy16[30]; /* 0x308 .. 0x37C */
  815. u32 dbwt0cnf0;
  816. u32 dbwt0cnf1;
  817. u32 dbwt0cnf2;
  818. u32 dbwt0cnf3;
  819. u32 dbwt0cnf4;
  820. u32 dummy17[27]; /* 0x394 .. 0x3FC */
  821. u32 dbeccmode;
  822. u32 dummy18[3]; /* 0x404 .. 0x40C */
  823. u32 dbeccarea0;
  824. u32 dbeccarea1;
  825. u32 dbeccarea2;
  826. u32 dbeccarea3;
  827. u32 dummy19[4]; /* 0x420 .. 0x42C */
  828. u32 dbeccintenable;
  829. u32 dbeccintdetect;
  830. u32 dummy20[22]; /* 0x438 .. 0x48C */
  831. u32 dbeccmodulcnt;
  832. u32 dummy21[27]; /* 0x494 .. 0x4FC */
  833. u32 dbschecnt0;
  834. u32 dummy22[63]; /* 0x504 .. 0x5FC */
  835. u32 dbreradr0;
  836. u32 dbreblane0;
  837. u32 dbrerid0;
  838. u32 dbrerinfo0;
  839. u32 dbureradr0;
  840. u32 dbureblane0;
  841. u32 dburerid0;
  842. u32 dburerinfo0;
  843. u32 dbreradr1;
  844. u32 dbreblane1;
  845. u32 dbrerid1;
  846. u32 dbrerinfo1;
  847. u32 dbureradr1;
  848. u32 dbureblane1;
  849. u32 dburerid1;
  850. u32 dburerinfo1;
  851. u32 dbreradr2;
  852. u32 dbreblane2;
  853. u32 dbrerid2;
  854. u32 dbrerinfo2;
  855. u32 dbureradr2;
  856. u32 dbureblane2;
  857. u32 dburerid2;
  858. u32 dburerinfo2;
  859. u32 dbreradr3;
  860. u32 dbreblane3;
  861. u32 dbrerid3;
  862. u32 dbrerinfo3;
  863. u32 dbureradr3;
  864. u32 dbureblane3;
  865. u32 dburerid3;
  866. u32 dburerinfo3;
  867. u32 dummy23[160]; /* 0x680 .. 0x8FC */
  868. u32 dbpccr;
  869. u32 dbpeier;
  870. u32 dbpeisr;
  871. u32 dummy24;
  872. u32 dbwdpesr0;
  873. u32 dbwspesr0;
  874. u32 dbpwear0;
  875. u32 dbpweid0;
  876. u32 dbpweinfo0;
  877. u32 dummy25[3]; /* 0x924 .. 0x92C */
  878. u32 dbwdpesr1;
  879. u32 dbwspesr1;
  880. u32 dbpwear1;
  881. u32 dbpweid1;
  882. u32 dbpweinfo1;
  883. u32 dummy26[3]; /* 0x944 .. 0x94C */
  884. u32 dbwdpesr2;
  885. u32 dbwspesr2;
  886. u32 dbpwear2;
  887. u32 dbpweid2;
  888. u32 dbpweinfo2;
  889. u32 dummy27[3]; /* 0x964 .. 0x96C */
  890. u32 dbwdpesr3;
  891. u32 dbwspesr3;
  892. u32 dbpwear3;
  893. u32 dbpweid3;
  894. u32 dbpweinfo3;
  895. };
  896. /* GPIO */
  897. struct rcar_gpio {
  898. u32 iointsel;
  899. u32 inoutsel;
  900. u32 outdt;
  901. u32 indt;
  902. u32 intdt;
  903. u32 intclr;
  904. u32 intmsk;
  905. u32 posneg;
  906. u32 edglevel;
  907. u32 filonoff;
  908. u32 intmsks;
  909. u32 mskclrs;
  910. u32 outdtsel;
  911. u32 outdth;
  912. u32 outdtl;
  913. u32 bothedge;
  914. };
  915. /* S3C(QoS) */
  916. struct rcar_s3c {
  917. u32 s3cexcladdmsk;
  918. u32 s3cexclidmsk;
  919. u32 s3cadsplcr;
  920. u32 s3cmaar;
  921. u32 s3carcr11;
  922. u32 s3crorr;
  923. u32 s3cworr;
  924. u32 s3carcr22;
  925. u32 dummy1[2]; /* 0x20 .. 0x24 */
  926. u32 s3cmctr;
  927. u32 dummy2; /* 0x2C */
  928. u32 cconf0;
  929. u32 cconf1;
  930. u32 cconf2;
  931. u32 cconf3;
  932. };
  933. struct rcar_s3c_qos {
  934. u32 s3cqos0;
  935. u32 s3cqos1;
  936. u32 s3cqos2;
  937. u32 s3cqos3;
  938. u32 s3cqos4;
  939. u32 s3cqos5;
  940. u32 s3cqos6;
  941. u32 s3cqos7;
  942. u32 s3cqos8;
  943. };
  944. /* DBSC(QoS) */
  945. struct rcar_dbsc3_qos {
  946. u32 dblgcnt;
  947. u32 dbtmval0;
  948. u32 dbtmval1;
  949. u32 dbtmval2;
  950. u32 dbtmval3;
  951. u32 dbrqctr;
  952. u32 dbthres0;
  953. u32 dbthres1;
  954. u32 dbthres2;
  955. u32 dummy0; /* 0x24 */
  956. u32 dblgqon;
  957. };
  958. /* MXI(QoS) */
  959. struct rcar_mxi {
  960. u32 mxsaar0;
  961. u32 mxsaar1;
  962. u32 dummy0[7]; /* 0x08 .. 0x20 */
  963. u32 mxaxiracr; /* R8a7790 only */
  964. u32 mxs3cracr;
  965. u32 dummy1[2]; /* 0x2C .. 0x30 */
  966. u32 mxaxiwacr; /* R8a7790 only */
  967. u32 mxs3cwacr;
  968. u32 dummy2; /* 0x3C */
  969. u32 mxrtcr;
  970. u32 mxwtcr;
  971. u32 mxaxirtcr; /* R8a7792 only */
  972. u32 mxaxiwtcr;
  973. u32 mxs3crtcr;
  974. u32 mxs3cwtcr;
  975. };
  976. struct rcar_mxi_qos {
  977. u32 vspdu0;
  978. u32 vspdu1;
  979. u32 du0;
  980. u32 du1;
  981. };
  982. /* AXI(QoS) */
  983. struct rcar_axi_qos {
  984. u32 qosconf;
  985. u32 qosctset0;
  986. u32 qosctset1;
  987. u32 qosctset2;
  988. u32 qosctset3;
  989. u32 qosreqctr;
  990. u32 qosthres0;
  991. u32 qosthres1;
  992. u32 qosthres2;
  993. u32 qosqon;
  994. u32 qosin;
  995. };
  996. #endif
  997. #endif /* __ASM_ARCH_RCAR_BASE_H */