tlb.c 3.3 KB

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  1. /*
  2. * Copyright 2013 Freescale Semiconductor, Inc.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. #include <common.h>
  23. #include <asm/mmu.h>
  24. struct fsl_e_tlb_entry tlb_table[] = {
  25. /* TLB 0 - for temp stack in cache */
  26. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  27. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  28. 0, 0, BOOKE_PAGESZ_4K, 0),
  29. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
  30. CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  31. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  32. 0, 0, BOOKE_PAGESZ_4K, 0),
  33. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
  34. CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  35. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  36. 0, 0, BOOKE_PAGESZ_4K, 0),
  37. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
  38. CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  39. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  40. 0, 0, BOOKE_PAGESZ_4K, 0),
  41. /* TLB 1 */
  42. /* *I*** - Covers boot page */
  43. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  44. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  45. 0, 0, BOOKE_PAGESZ_4K, 1),
  46. #ifdef CONFIG_SPL_NAND_MINIMAL
  47. SET_TLB_ENTRY(1, 0xffffe000, 0xffffe000,
  48. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  49. 0, 10, BOOKE_PAGESZ_4K, 1),
  50. #endif
  51. /* *I*G* - CCSRBAR (PA) */
  52. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  53. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54. 0, 1, BOOKE_PAGESZ_1M, 1),
  55. #ifndef CONFIG_SPL_BUILD
  56. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  57. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  58. 0, 3, BOOKE_PAGESZ_64M, 1),
  59. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE + 0x4000000,
  60. CONFIG_SYS_FLASH_BASE_PHYS + 0x4000000,
  61. MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  62. 0, 4, BOOKE_PAGESZ_64M, 1),
  63. #ifdef CONFIG_PCI
  64. /* *I*G* - PCI */
  65. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  66. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  67. 0, 6, BOOKE_PAGESZ_256M, 1),
  68. /* *I*G* - PCI I/O */
  69. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  70. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71. 0, 7, BOOKE_PAGESZ_64K, 1),
  72. #endif
  73. #endif
  74. #if defined(CONFIG_SYS_RAMBOOT) || defined(CONFIG_SPL)
  75. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  76. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  77. 0, 8, BOOKE_PAGESZ_1G, 1),
  78. #endif
  79. #ifdef CONFIG_SYS_FPGA_BASE
  80. /* *I*G - Board FPGA */
  81. SET_TLB_ENTRY(1, CONFIG_SYS_FPGA_BASE, CONFIG_SYS_FPGA_BASE_PHYS,
  82. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  83. 0, 9, BOOKE_PAGESZ_256K, 1),
  84. #endif
  85. #ifdef CONFIG_SYS_NAND_BASE_PHYS
  86. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  87. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88. 0, 5, BOOKE_PAGESZ_1M, 1),
  89. #endif
  90. };
  91. int num_tlb_entries = ARRAY_SIZE(tlb_table);