ns16550.h 5.6 KB

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  1. /*
  2. * NS16550 Serial Port
  3. * originally from linux source (arch/powerpc/boot/ns16550.h)
  4. *
  5. * Cleanup and unification
  6. * (C) 2009 by Detlev Zundel, DENX Software Engineering GmbH
  7. *
  8. * modified slightly to
  9. * have addresses as offsets from CONFIG_SYS_ISA_BASE
  10. * added a few more definitions
  11. * added prototypes for ns16550.c
  12. * reduced no of com ports to 2
  13. * modifications (c) Rob Taylor, Flying Pig Systems. 2000.
  14. *
  15. * added support for port on 64-bit bus
  16. * by Richard Danter (richard.danter@windriver.com), (C) 2005 Wind River Systems
  17. */
  18. /*
  19. * Note that the following macro magic uses the fact that the compiler
  20. * will not allocate storage for arrays of size 0
  21. */
  22. #if !defined(CONFIG_SYS_NS16550_REG_SIZE) || (CONFIG_SYS_NS16550_REG_SIZE == 0)
  23. #error "Please define NS16550 registers size."
  24. #elif (CONFIG_SYS_NS16550_REG_SIZE > 0)
  25. #define UART_REG(x) \
  26. unsigned char prepad_##x[CONFIG_SYS_NS16550_REG_SIZE - 1]; \
  27. unsigned char x;
  28. #elif (CONFIG_SYS_NS16550_REG_SIZE < 0)
  29. #define UART_REG(x) \
  30. unsigned char x; \
  31. unsigned char postpad_##x[-CONFIG_SYS_NS16550_REG_SIZE - 1];
  32. #endif
  33. struct NS16550 {
  34. UART_REG(rbr); /* 0 */
  35. UART_REG(ier); /* 1 */
  36. UART_REG(fcr); /* 2 */
  37. UART_REG(lcr); /* 3 */
  38. UART_REG(mcr); /* 4 */
  39. UART_REG(lsr); /* 5 */
  40. UART_REG(msr); /* 6 */
  41. UART_REG(spr); /* 7 */
  42. UART_REG(mdr1); /* 8 */
  43. UART_REG(reg9); /* 9 */
  44. UART_REG(regA); /* A */
  45. UART_REG(regB); /* B */
  46. UART_REG(regC); /* C */
  47. UART_REG(regD); /* D */
  48. UART_REG(regE); /* E */
  49. UART_REG(uasr); /* F */
  50. UART_REG(scr); /* 10*/
  51. UART_REG(ssr); /* 11*/
  52. UART_REG(reg12); /* 12*/
  53. UART_REG(osc_12m_sel); /* 13*/
  54. };
  55. #define thr rbr
  56. #define iir fcr
  57. #define dll rbr
  58. #define dlm ier
  59. typedef volatile struct NS16550 *NS16550_t;
  60. /*
  61. * These are the definitions for the FIFO Control Register
  62. */
  63. #define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
  64. #define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
  65. #define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
  66. #define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
  67. #define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
  68. #define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
  69. #define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
  70. #define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
  71. #define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
  72. #define UART_FCR_RXSR 0x02 /* Receiver soft reset */
  73. #define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
  74. /*
  75. * These are the definitions for the Modem Control Register
  76. */
  77. #define UART_MCR_DTR 0x01 /* DTR */
  78. #define UART_MCR_RTS 0x02 /* RTS */
  79. #define UART_MCR_OUT1 0x04 /* Out 1 */
  80. #define UART_MCR_OUT2 0x08 /* Out 2 */
  81. #define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
  82. #define UART_MCR_DMA_EN 0x04
  83. #define UART_MCR_TX_DFR 0x08
  84. /*
  85. * These are the definitions for the Line Control Register
  86. *
  87. * Note: if the word length is 5 bits (UART_LCR_WLEN5), then setting
  88. * UART_LCR_STOP will select 1.5 stop bits, not 2 stop bits.
  89. */
  90. #define UART_LCR_WLS_MSK 0x03 /* character length select mask */
  91. #define UART_LCR_WLS_5 0x00 /* 5 bit character length */
  92. #define UART_LCR_WLS_6 0x01 /* 6 bit character length */
  93. #define UART_LCR_WLS_7 0x02 /* 7 bit character length */
  94. #define UART_LCR_WLS_8 0x03 /* 8 bit character length */
  95. #define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
  96. #define UART_LCR_PEN 0x08 /* Parity eneble */
  97. #define UART_LCR_EPS 0x10 /* Even Parity Select */
  98. #define UART_LCR_STKP 0x20 /* Stick Parity */
  99. #define UART_LCR_SBRK 0x40 /* Set Break */
  100. #define UART_LCR_BKSE 0x80 /* Bank select enable */
  101. #define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
  102. /*
  103. * These are the definitions for the Line Status Register
  104. */
  105. #define UART_LSR_DR 0x01 /* Data ready */
  106. #define UART_LSR_OE 0x02 /* Overrun */
  107. #define UART_LSR_PE 0x04 /* Parity error */
  108. #define UART_LSR_FE 0x08 /* Framing error */
  109. #define UART_LSR_BI 0x10 /* Break */
  110. #define UART_LSR_THRE 0x20 /* Xmit holding register empty */
  111. #define UART_LSR_TEMT 0x40 /* Xmitter empty */
  112. #define UART_LSR_ERR 0x80 /* Error */
  113. #define UART_MSR_DCD 0x80 /* Data Carrier Detect */
  114. #define UART_MSR_RI 0x40 /* Ring Indicator */
  115. #define UART_MSR_DSR 0x20 /* Data Set Ready */
  116. #define UART_MSR_CTS 0x10 /* Clear to Send */
  117. #define UART_MSR_DDCD 0x08 /* Delta DCD */
  118. #define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
  119. #define UART_MSR_DDSR 0x02 /* Delta DSR */
  120. #define UART_MSR_DCTS 0x01 /* Delta CTS */
  121. /*
  122. * These are the definitions for the Interrupt Identification Register
  123. */
  124. #define UART_IIR_NO_INT 0x01 /* No interrupts pending */
  125. #define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
  126. #define UART_IIR_MSI 0x00 /* Modem status interrupt */
  127. #define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
  128. #define UART_IIR_RDI 0x04 /* Receiver data interrupt */
  129. #define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
  130. /*
  131. * These are the definitions for the Interrupt Enable Register
  132. */
  133. #define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
  134. #define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
  135. #define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
  136. #define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
  137. #ifdef CONFIG_OMAP1510
  138. #define OSC_12M_SEL 0x01 /* selects 6.5 * current clk div */
  139. #endif
  140. /* useful defaults for LCR */
  141. #define UART_LCR_8N1 0x03
  142. void NS16550_init (NS16550_t com_port, int baud_divisor);
  143. void NS16550_putc (NS16550_t com_port, char c);
  144. char NS16550_getc (NS16550_t com_port);
  145. int NS16550_tstc (NS16550_t com_port);
  146. void NS16550_reinit (NS16550_t com_port, int baud_divisor);