lpd7a400_cpld.h 7.2 KB

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  1. /*
  2. * See file CREDITS for list of people who contributed to this
  3. * project.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. /*
  21. * Logic lh7a400-10 Card Engine CPLD interface
  22. */
  23. #ifndef __LPD7A400_CPLD_H_
  24. #define __LPD7A400_CPLD_H_
  25. /*
  26. * IO Controller Address and Register Definitions
  27. * - using LH7A400-10 Card Engine IO Controller Specification
  28. * (logic PN: 70000079)
  29. */
  30. /*------------------------------------------------------------------
  31. * Slow Peripherals (nCS6)
  32. */
  33. #define LPD7A400_CPLD_CF (0x60200000)
  34. #define LPD7A400_CPLD_ISA (0x60400000)
  35. /*------------------------------------------------------------------
  36. * Fast Peripherals (nCS7)
  37. *
  38. * The CPLD directs access to 0x70000000-0x701fffff to the onboard
  39. * ethernet controller
  40. */
  41. #define LPD7A400_CPLD_WLAN_BASE (0x70000000)
  42. /* All registers are 8 bit */
  43. #define LPD7A400_CPLD_CECTL_REG (0x70200000)
  44. #define LPD7A400_CPLD_SPIDATA_REG (0x70600000)
  45. #define LPD7A400_CPLD_SPICTL_REG (0x70800000)
  46. #define LPD7A400_CPLD_EEPSPI_REG (0x70a00000)
  47. #define LPD7A400_CPLD_INTMASK_REG (0x70c00000)
  48. #define LPD7A400_CPLD_MODE_REG (0x70e00000)
  49. #define LPD7A400_CPLD_FLASH_REG (0x71000000)
  50. #define LPD7A400_CPLD_PWRMG_REG (0x71200000)
  51. #define LPD7A400_CPLD_REV_REG (0x71400000)
  52. #define LPD7A400_CPLD_EXTGPIO_REG (0x71600000)
  53. #define LPD7A400_CPLD_GPIODATA_REG (0x71800000)
  54. #define LPD7A400_CPLD_GPIODIR_REG (0x71a00000)
  55. #define LPD7A400_CPLD_REGPTR (volatile u8*)
  56. /* Card Engine Control Register (section 3.1.2) */
  57. #define CECTL_SWINT (0x80) /* Software settable interrupt source
  58. (routed to uP PF3)
  59. 0 = generate interrupt, 1 = do not */
  60. #define CECTL_OCMSK (0x40) /* USB1 connection interrupt mask
  61. 0 = not masked, 1 = masked */
  62. #define CECTL_PDRV (0x20) /* PCC_nDRV output
  63. 0 = active, 1 = inactive */
  64. #define CECTL_USB1C (0x10) /* USB1 connection interrupt
  65. 0 = active, 1 = inactive */
  66. #define CECTL_USB1P (0x08) /* USB1 Power enable
  67. 0 = enabled, 1 = disabled */
  68. #define CECTL_AWKP (0x04) /* Auto-Wakeup enable
  69. 0 = enabled, 1 = disabled */
  70. #define CECTL_LCDV (0x02) /* LCD VEE enable
  71. 0 = disabled, 1 = enabled */
  72. #define CECTL_WLPE (0x01) /* Wired LAN power enable
  73. 0 = enabled, 1 = disabled */
  74. /* SPI Control Register (section 3.1.5) */
  75. #define SPICTL_SPLD (0x20) /* SPI load (R)
  76. 0 = data reg. has not been loaded, shift
  77. count has not been reset
  78. 1 = data reg. loaded, shift count reset */
  79. #define SPICTL_SPST (0x10) /* SPI start (RW)
  80. 0 = don't load data reg. and reset shift count
  81. 1 = ready to load data reg and reset shift count */
  82. #define SPICTL_SPDN (0x08) /* SPI done (R)
  83. 0 = not done
  84. 1 = access done */
  85. #define SPICTL_SPRW (0x04) /* SPI read/write (RW)
  86. 0 = SPI write access
  87. 1 = SPI read access */
  88. #define SPICTL_STCS (0x02) /* SPI touch chip select (RW)
  89. 0 = not selected
  90. 1 = selected */
  91. #define SPICTL_SCCS (0x01) /* SPI CODEC chip select (RW) {not used}
  92. 0 = not selected
  93. 1 = selected */
  94. /* EEPROM SPI Interface Register (section 3.1.6) */
  95. #define EEPSPI_EECS (0x08) /* EEPROM chip select (RW)
  96. 0 = not selected
  97. 1 = selected */
  98. #define EEPSPI_EECK (0x04) /* EEPROM SPI clock (RW) */
  99. #define EEPSPI_EETX (0x02) /* EEPROM SPI tx data (RW) */
  100. #define EEPSPI_EERX (0x01) /* EEPROM SPI rx data (R) */
  101. /* Interrupt/Mask Register (section 3.1.7) */
  102. #define INTMASK_CMSK (0x80) /* CPLD_nIRQD interrupt mask (RW)
  103. 0 = not masked
  104. 1 = masked */
  105. #define INTMASK_CIRQ (0x40) /* interrupt signal to CPLD (R)
  106. 0 = interrupt active
  107. 1 = no interrupt */
  108. #define INTMASK_PIRQ (0x10) /* legacy, no effect */
  109. #define INTMASK_TMSK (0x08) /* Touch chip interrupt mask (RW)
  110. 0 = not masked
  111. 1 = masked */
  112. #define INTMASK_WMSK (0x04) /* Wired LAN interrupt mask (RW)
  113. 0 = not masked
  114. 1 = masked */
  115. #define INTMASK_TIRQ (0x02) /* Touch chip interrupt request (R)
  116. 0 = interrupt active
  117. 1 = no interrupt */
  118. #define INTMASK_WIRQ (0x01) /* Wired LAN interrupt request (R)
  119. 0 = interrupt active
  120. 1 = no interrupt */
  121. /* Mode Register (section 3.1.8) */
  122. #define MODE_VS1 (0x80) /* PCMCIA Voltage Sense 1 input (PCC_VS1) (R)
  123. 0 = active slot VS1 pin is low
  124. 1 = active slot VS1 pin is high */
  125. #define MODE_CD2 (0x40) /* PCMCIA Card Detect 2 input (PCC_nCD2) (R)
  126. 0 = active slot CD2 is low
  127. 1 = active slot CD2 is high */
  128. #define MODE_IOIS16 (0x20) /* PCMCIA IOIS16 input (PCC_nIOIS16) (R)
  129. 0 = 16 bit access area
  130. 1 = 8 bit access area */
  131. #define MODE_CD1 (0x10) /* PCMCIA Card Detect 1 input (PCC_nCD1) (R)
  132. 0 = active slot CD1 is low
  133. 1 = active slot CD1 is high */
  134. #define MODE_upMODE3 (0x08) /* Mode Pin 3 (R)
  135. 0 = off-board boot device
  136. 1 = on-board boot device (flash) */
  137. #define MODE_upMODE2 (0x04) /* Mode Pin 2 (R) (LH7A400 Little Endian only)
  138. 0 = big endian
  139. 1 = little endian */
  140. #define MODE_upMODE1 (0x02) /* Mode Pin 1 and Mode Pin 2 (R) */
  141. #define MODE_upMODE0 (0x01) /* - bus width at boot */
  142. /* Flash Register (section 3.1.9) */
  143. #define FLASH_FPOP (0x08) /* Flash populated (RW)
  144. 0 = populated, 1 = not */
  145. #define FLASH_FST2 (0x04) /* Flash status (R) (RY/BY# pin for upper 16 bit chip
  146. 0 = busy, 1 = ready */
  147. #define FLASH_FST1 (0x02) /* Flash status (R) (RY/BY# pin for lower 16 bit chip
  148. 0 = busy, 1 = ready */
  149. #define FLASH_FPEN (0x01) /* Flash program enable (RW)
  150. 0 = flash write protected
  151. 1 = programming enabled */
  152. /* Power Management Register (section 3.1.10)
  153. * - when either of these is low an unmaskable interrupt to cpu
  154. * is generated
  155. */
  156. #define PWRMG_STBY (0x10) /* state of nSTANDBY signal to CPLD (R)
  157. 0 = low, 1 = high */
  158. #define PWRMG_SPND (0x04) /* state of nSUSPEND signal to CPLD (R)
  159. 0 = low, 1 = high */
  160. /* Extended GPIO Register (section 3.1.12) */
  161. #define EXTGPIO_STATUS1 (0x04) /* Status 1 output (RW) (uP_STATUS_1)
  162. 0 = set pin low, 1 = set pin high */
  163. #define EXTGPIO_STATUS2 (0x02) /* Status 2 output (RW) (uP_STATUS_2)
  164. 0 = set pin low, 1 = set pin high */
  165. #define EXTGPIO_GPIO1 (0x01) /* General purpose output (RW) (CPLD_GPIO_1)
  166. 0 = set pin low, 1 = set pin high */
  167. /* GPIO Data Register (section 3.1.13) */
  168. #define GPIODATA_GPIO2 (0x01) /* General purpose input/output (RW) (CPLD_GPIO_2)
  169. 0 = set low (output) / read low (input)
  170. 1 = set high (output) / read high (input) */
  171. /* GPIO Direction Register (section 3.1.14) */
  172. #define GPIODIR_GPDR0 (0x01) /* GPIO2 direction (RW)
  173. 0 = output, 1 = input */
  174. #endif /* __LH7A400_H__ */