utx8245.h 16 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2002
  6. * Gregory E. Allen, gallen@arlut.utexas.edu
  7. * Matthew E. Karger, karger@arlut.utexas.edu
  8. * Applied Research Laboratories, The University of Texas at Austin
  9. *
  10. * See file CREDITS for list of people who contributed to this
  11. * project.
  12. *
  13. * This program is free software; you can redistribute it and/or
  14. * modify it under the terms of the GNU General Public License as
  15. * published by the Free Software Foundation; either version 2 of
  16. * the License, or (at your option) any later version.
  17. *
  18. * This program is distributed in the hope that it will be useful,
  19. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  20. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  21. * GNU General Public License for more details.
  22. *
  23. * You should have received a copy of the GNU General Public License
  24. * along with this program; if not, write to the Free Software
  25. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  26. * MA 02111-1307 USA
  27. */
  28. /*
  29. *
  30. * Configuration settings for the utx8245 board.
  31. *
  32. */
  33. /* ------------------------------------------------------------------------- */
  34. /*
  35. * board/config.h - configuration options, board specific
  36. */
  37. #ifndef __CONFIG_H
  38. #define __CONFIG_H
  39. /*
  40. * High Level Configuration Options
  41. * (easy to change)
  42. */
  43. #define CONFIG_MPC824X 1
  44. #define CONFIG_MPC8245 1
  45. #define CONFIG_UTX8245 1
  46. #define DEBUG 1
  47. #define CONFIG_IDENT_STRING " [UTX5] "
  48. #define CONFIG_CONS_INDEX 1
  49. #define CONFIG_BAUDRATE 57600
  50. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  51. #define CONFIG_BOOTDELAY 2
  52. #define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n", bootdelay
  53. #define CONFIG_BOOTCOMMAND "run nfsboot" /* autoboot command */
  54. #define CONFIG_BOOTARGS "root=/dev/ram console=ttyS0,57600" /* RAMdisk */
  55. #define CONFIG_ETHADDR 00:AA:00:14:00:05 /* UTX5 */
  56. #define CONFIG_SERVERIP 10.8.17.105 /* Spree */
  57. #define CONFIG_SYS_TFTP_LOADADDR 10000
  58. #define CONFIG_EXTRA_ENV_SETTINGS \
  59. "kernel_addr=FFA00000\0" \
  60. "ramdisk_addr=FF800000\0" \
  61. "u-boot_startaddr=FFB00000\0" \
  62. "u-boot_endaddr=FFB2FFFF\0" \
  63. "nfsargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/nfs rw \
  64. nfsroot=${nfsrootip}:${rootpath} ip=dhcp\0" \
  65. "ramargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/ram0\0" \
  66. "smargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/mtdblock1 ro\0" \
  67. "fwargs=setenv bootargs console=ttyS0,${baudrate} root=/dev/sda2 ro\0" \
  68. "nfsboot=run nfsargs;bootm ${kernel_addr}\0" \
  69. "ramboot=run ramargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  70. "smboot=run smargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  71. "fwboot=run fwargs;bootm ${kernel_addr} ${ramdisk_addr}\0" \
  72. "update_u-boot=tftp ${loadaddr} /bdi2000/u-boot.bin;protect off \
  73. ${u-boot_startaddr} ${u-boot_endaddr};era ${u-boot_startaddr} \
  74. ${u-boot_endaddr};cp.b ${loadaddr} ${u-boot_startaddr} ${filesize};\
  75. protect on ${u-boot_startaddr} ${u-boot_endaddr}"
  76. #define CONFIG_ENV_OVERWRITE
  77. /*
  78. * BOOTP options
  79. */
  80. #define CONFIG_BOOTP_BOOTFILESIZE
  81. #define CONFIG_BOOTP_BOOTPATH
  82. #define CONFIG_BOOTP_GATEWAY
  83. #define CONFIG_BOOTP_HOSTNAME
  84. /*
  85. * Command line configuration.
  86. */
  87. #include <config_cmd_default.h>
  88. #define CONFIG_CMD_BDI
  89. #define CONFIG_CMD_PCI
  90. #define CONFIG_CMD_FLASH
  91. #define CONFIG_CMD_MEMORY
  92. #define CONFIG_CMD_SAVEENV
  93. #define CONFIG_CMD_CONSOLE
  94. #define CONFIG_CMD_LOADS
  95. #define CONFIG_CMD_LOADB
  96. #define CONFIG_CMD_IMI
  97. #define CONFIG_CMD_CACHE
  98. #define CONFIG_CMD_REGINFO
  99. #define CONFIG_CMD_NET
  100. #define CONFIG_CMD_DHCP
  101. #define CONFIG_CMD_I2C
  102. #define CONFIG_CMD_DATE
  103. /*
  104. * Miscellaneous configurable options
  105. */
  106. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  107. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  108. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  109. /* Print Buffer Size */
  110. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  111. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  112. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  113. #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
  114. /*-----------------------------------------------------------------------
  115. * PCI configuration
  116. *-----------------------------------------------------------------------
  117. */
  118. #define CONFIG_PCI /* include pci support */
  119. #undef CONFIG_PCI_PNP
  120. #define CONFIG_PCI_SCAN_SHOW
  121. #define CONFIG_NET_MULTI
  122. #define CONFIG_EEPRO100
  123. #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  124. #define CONFIG_EEPRO100_SROM_WRITE
  125. #define PCI_ENET0_IOADDR 0xF0000000
  126. #define PCI_ENET0_MEMADDR 0xF0000000
  127. #define PCI_FIREWIRE_IOADDR 0xF1000000
  128. #define PCI_FIREWIRE_MEMADDR 0xF1000000
  129. /*
  130. #define PCI_ENET0_IOADDR 0xFE000000
  131. #define PCI_ENET0_MEMADDR 0x80000000
  132. #define PCI_FIREWIRE_IOADDR 0x81000000
  133. #define PCI_FIREWIRE_MEMADDR 0x81000000
  134. */
  135. /*-----------------------------------------------------------------------
  136. * Start addresses for the final memory configuration
  137. * (Set up by the startup code)
  138. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  139. */
  140. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  141. #define CONFIG_SYS_MAX_RAM_SIZE 0x10000000 /* 256MB */
  142. /*#define CONFIG_SYS_VERY_BIG_RAM 1 */
  143. /* FLASH_BASE is FF800000, with 4MB on RCS0, but the reset vector
  144. * is actually located at FFF00100. Therefore, U-Boot is
  145. * physically located at 0xFFB0_0000, but is also mirrored at
  146. * 0xFFF0_0000.
  147. */
  148. #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
  149. #define CONFIG_SYS_EUMB_ADDR 0xFC000000
  150. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  151. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  152. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  153. /*#define CONFIG_SYS_DRAM_TEST 1 */
  154. #define CONFIG_SYS_MEMTEST_START 0x00003000 /* memtest works on 0...256 MB */
  155. #define CONFIG_SYS_MEMTEST_END 0x0ff8ffa7 /* in SDRAM, skips exception */
  156. /* vectors and U-Boot */
  157. /*--------------------------------------------------------------------
  158. * Definitions for initial stack pointer and data area
  159. *------------------------------------------------------------------*/
  160. #define CONFIG_SYS_INIT_DATA_SIZE 128 /* Size in bytes reserved for */
  161. /* initial data */
  162. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
  163. #define CONFIG_SYS_INIT_RAM_END 0x1000
  164. #define CONFIG_SYS_INIT_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_INIT_DATA_SIZE)
  165. #define CONFIG_SYS_GBL_DATA_SIZE 128
  166. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  167. /*--------------------------------------------------------------------
  168. * NS16550 Configuration
  169. *------------------------------------------------------------------*/
  170. #define CONFIG_SYS_NS16550
  171. #define CONFIG_SYS_NS16550_SERIAL
  172. #define CONFIG_SYS_NS16550_REG_SIZE 1
  173. #if (CONFIG_CONS_INDEX == 1 || CONFIG_CONS_INDEX == 2)
  174. # define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  175. #else
  176. # define CONFIG_SYS_NS16550_CLK 33000000
  177. #endif
  178. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
  179. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
  180. #define CONFIG_SYS_NS16550_COM3 0xFF000000
  181. #define CONFIG_SYS_NS16550_COM4 0xFF000008
  182. /*--------------------------------------------------------------------
  183. * Low Level Configuration Settings
  184. * (address mappings, register initial values, etc.)
  185. * You should know what you are doing if you make changes here.
  186. * For the detail description refer to the MPC8240 user's manual.
  187. *------------------------------------------------------------------*/
  188. #define CONFIG_SYS_CLK_FREQ 33000000
  189. #define CONFIG_SYS_HZ 1000
  190. /*#define CONFIG_SYS_ETH_DEV_FN 0x7800 */
  191. /*#define CONFIG_SYS_ETH_IOBASE 0x00104000 */
  192. /*--------------------------------------------------------------------
  193. * I2C Configuration
  194. *------------------------------------------------------------------*/
  195. #if 1
  196. #define CONFIG_HARD_I2C 1 /* To enable I2C support */
  197. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  198. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  199. #define CONFIG_SYS_I2C_SLAVE 0x7F
  200. #endif
  201. #define CONFIG_RTC_PCF8563 1 /* enable I2C support for */
  202. /* Philips PCF8563 RTC */
  203. #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
  204. /*--------------------------------------------------------------------
  205. * Memory Control Configuration Register values
  206. * - see sec. 4.12 of MPC8245 UM
  207. *------------------------------------------------------------------*/
  208. /**** MCCR1 ****/
  209. #define CONFIG_SYS_ROMNAL 0
  210. #define CONFIG_SYS_ROMFAL 10 /* (tacc=70ns)*mem_freq - 2,
  211. mem_freq = 100MHz */
  212. #define CONFIG_SYS_BANK7_ROW 0 /* SDRAM bank 7-0 row address */
  213. #define CONFIG_SYS_BANK6_ROW 0 /* bit count */
  214. #define CONFIG_SYS_BANK5_ROW 0
  215. #define CONFIG_SYS_BANK4_ROW 0
  216. #define CONFIG_SYS_BANK3_ROW 0
  217. #define CONFIG_SYS_BANK2_ROW 0
  218. #define CONFIG_SYS_BANK1_ROW 2
  219. #define CONFIG_SYS_BANK0_ROW 2
  220. /**** MCCR2, refresh interval clock cycles ****/
  221. #define CONFIG_SYS_REFINT 480 /* 33 MHz SDRAM clock was 480 */
  222. /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4. */
  223. #define CONFIG_SYS_BSTOPRE 1023 /* burst to precharge[0..9], */
  224. /* sets open page interval */
  225. /**** MCCR3 ****/
  226. #define CONFIG_SYS_REFREC 7 /* Refresh to activate interval, trc */
  227. /**** MCCR4 ****/
  228. #define CONFIG_SYS_PRETOACT 2 /* trp */
  229. #define CONFIG_SYS_ACTTOPRE 7 /* trcd + (burst length - 1) + trdl */
  230. #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
  231. #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type, sequential */
  232. #define CONFIG_SYS_ACTORW 2 /* trcd min */
  233. #define CONFIG_SYS_DBUS_SIZE2 1 /* set for 8-bit RCS1, clear for 32,64 */
  234. #define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
  235. #define CONFIG_SYS_EXTROM 0 /* we don't need extended ROM space */
  236. #define CONFIG_SYS_REGDIMM 0
  237. /* calculate according to formula in sec. 6-22 of 8245 UM */
  238. #define CONFIG_SYS_PGMAX 50 /* how long the 8245 retains the */
  239. /* currently accessed page in memory */
  240. /* was 45 */
  241. #define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note */
  242. /* bits 7,6, and 3-0 MUST be 0 */
  243. #if 0
  244. #define CONFIG_SYS_DLL_MAX_DELAY 0x04
  245. #else
  246. #define CONFIG_SYS_DLL_MAX_DELAY 0
  247. #endif
  248. #if 0 /* need for 33MHz SDRAM */
  249. #define CONFIG_SYS_DLL_EXTEND 0x80
  250. #else
  251. #define CONFIG_SYS_DLL_EXTEND 0
  252. #endif
  253. #define CONFIG_SYS_PCI_HOLD_DEL 0x20
  254. /* Memory bank settings.
  255. * Only bits 20-29 are actually used from these values to set the
  256. * start/end addresses. The upper two bits will always be 0, and the lower
  257. * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
  258. * address. Refer to the MPC8245 user manual.
  259. */
  260. #define CONFIG_SYS_BANK0_START 0x00000000
  261. #define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE/2 - 1)
  262. #define CONFIG_SYS_BANK0_ENABLE 1
  263. #define CONFIG_SYS_BANK1_START CONFIG_SYS_MAX_RAM_SIZE/2
  264. #define CONFIG_SYS_BANK1_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
  265. #define CONFIG_SYS_BANK1_ENABLE 1
  266. #define CONFIG_SYS_BANK2_START 0x3ff00000 /* not available in this design */
  267. #define CONFIG_SYS_BANK2_END 0x3fffffff
  268. #define CONFIG_SYS_BANK2_ENABLE 0
  269. #define CONFIG_SYS_BANK3_START 0x3ff00000
  270. #define CONFIG_SYS_BANK3_END 0x3fffffff
  271. #define CONFIG_SYS_BANK3_ENABLE 0
  272. #define CONFIG_SYS_BANK4_START 0x3ff00000
  273. #define CONFIG_SYS_BANK4_END 0x3fffffff
  274. #define CONFIG_SYS_BANK4_ENABLE 0
  275. #define CONFIG_SYS_BANK5_START 0x3ff00000
  276. #define CONFIG_SYS_BANK5_END 0x3fffffff
  277. #define CONFIG_SYS_BANK5_ENABLE 0
  278. #define CONFIG_SYS_BANK6_START 0x3ff00000
  279. #define CONFIG_SYS_BANK6_END 0x3fffffff
  280. #define CONFIG_SYS_BANK6_ENABLE 0
  281. #define CONFIG_SYS_BANK7_START 0x3ff00000
  282. #define CONFIG_SYS_BANK7_END 0x3fffffff
  283. #define CONFIG_SYS_BANK7_ENABLE 0
  284. /*--------------------------------------------------------------------*/
  285. /* 4.4 - Output Driver Control Register */
  286. /*--------------------------------------------------------------------*/
  287. #define CONFIG_SYS_ODCR 0xe5
  288. /*--------------------------------------------------------------------*/
  289. /* 4.8 - Error Handling Registers */
  290. /*-------------------------------CONFIG_SYS_SDMODE_BURSTLEN-------------------------------------*/
  291. #define CONFIG_SYS_ERRENR1 0x11 /* enable SDRAM refresh overflow error */
  292. /* SDRAM 0-256 MB */
  293. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  294. /*#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_CACHEINHIBIT) */
  295. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  296. /* stack in dcache */
  297. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
  298. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
  299. #define CONFIG_SYS_IBAT2L (CONFIG_SYS_SDRAM_BASE + 0x10000000 | BATL_PP_10 | BATL_MEMCOHERENCE)
  300. #define CONFIG_SYS_IBAT2U (CONFIG_SYS_SDRAM_BASE + 0x10000000| BATU_BL_256M | BATU_VS | BATU_VP)
  301. /* PCI memory */
  302. /*#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT) */
  303. /*#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP) */
  304. /*Flash, config addrs, etc. */
  305. #define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
  306. #define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  307. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  308. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  309. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  310. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  311. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  312. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  313. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  314. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  315. /*
  316. * For booting Linux, the board info and command line data
  317. * have to be in the first 8 MB of memory, since this is
  318. * the maximum mapped by the Linux kernel during initialization.
  319. */
  320. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  321. /*-----------------------------------------------------------------------
  322. * FLASH organization
  323. *----------------------------------------------------------------------*/
  324. #define CONFIG_SYS_FLASH_BASE 0xFF800000
  325. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
  326. /* NOTE: environment is not EMBEDDED in the u-boot code.
  327. It's stored in flash in its own separate sector. */
  328. #define CONFIG_ENV_IS_IN_FLASH 1
  329. #if 1 /* AMD AM29LV033C */
  330. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
  331. #define CONFIG_ENV_ADDR 0xFFBF0000 /* flash sector SA63 */
  332. #define CONFIG_ENV_SECT_SIZE (64*1024) /* Size of the Environment Sector */
  333. #else /* AMD AM29LV116D */
  334. #define CONFIG_SYS_MAX_FLASH_SECT 35 /* Max number of sectors in one bank */
  335. #define CONFIG_ENV_ADDR 0xFF9FA000 /* flash sector SA33 */
  336. #define CONFIG_ENV_SECT_SIZE (8*1024) /* Size of the Environment Sector */
  337. #endif /* #if */
  338. #define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE /* Size of the Environment */
  339. #define CONFIG_ENV_OFFSET 0 /* starting right at the beginning */
  340. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  341. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  342. #if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
  343. #undef CONFIG_SYS_RAMBOOT
  344. #else
  345. #define CONFIG_SYS_RAMBOOT
  346. #endif
  347. /*-----------------------------------------------------------------------
  348. * Cache Configuration
  349. */
  350. #define CONFIG_SYS_CACHELINE_SIZE 32
  351. #if defined(CONFIG_CMD_KGDB)
  352. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  353. #endif
  354. /*
  355. * Internal Definitions
  356. *
  357. * Boot Flags
  358. */
  359. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  360. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  361. #endif /* __CONFIG_H */