sh7785lcr.h 6.0 KB

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  1. /*
  2. * Configuation settings for the Renesas Technology R0P7785LC0011RL board
  3. *
  4. * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. #ifndef __SH7785LCR_H
  25. #define __SH7785LCR_H
  26. #undef DEBUG
  27. #define CONFIG_SH 1
  28. #define CONFIG_SH4A 1
  29. #define CONFIG_CPU_SH7785 1
  30. #define CONFIG_SH7785LCR 1
  31. #define CONFIG_CMD_FLASH
  32. #define CONFIG_CMD_MEMORY
  33. #define CONFIG_CMD_PCI
  34. #define CONFIG_CMD_NET
  35. #define CONFIG_CMD_PING
  36. #define CONFIG_CMD_NFS
  37. #define CONFIG_CMD_DFL
  38. #define CONFIG_CMD_SDRAM
  39. #define CONFIG_CMD_RUN
  40. #define CONFIG_CMD_SAVEENV
  41. #define CONFIG_CMD_USB
  42. #define CONFIG_USB_STORAGE
  43. #define CONFIG_CMD_EXT2
  44. #define CONFIG_CMD_FAT
  45. #define CONFIG_DOS_PARTITION
  46. #define CONFIG_MAC_PARTITION
  47. #define CONFIG_BAUDRATE 115200
  48. #define CONFIG_BOOTDELAY 3
  49. #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp"
  50. #define CONFIG_EXTRA_ENV_SETTINGS \
  51. "bootdevice=0:1\0" \
  52. "usbload=usb reset;usbboot;usb stop;bootm\0"
  53. #define CONFIG_VERSION_VARIABLE
  54. #undef CONFIG_SHOW_BOOT_PROGRESS
  55. /* MEMORY */
  56. #if defined(CONFIG_SH_32BIT)
  57. #define SH7785LCR_SDRAM_PHYS_BASE (0x48000000)
  58. #define SH7785LCR_SDRAM_BASE (0x88000000)
  59. #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024)
  60. #define SH7785LCR_FLASH_BASE_1 (0xa0000000)
  61. #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
  62. #define SH7785LCR_USB_BASE (0xa6000000)
  63. #else
  64. #define SH7785LCR_SDRAM_BASE (0x08000000)
  65. #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024)
  66. #define SH7785LCR_FLASH_BASE_1 (0xa0000000)
  67. #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024)
  68. #define SH7785LCR_USB_BASE (0xb4000000)
  69. #endif
  70. #define CONFIG_SYS_LONGHELP
  71. #define CONFIG_SYS_PROMPT "=> "
  72. #define CONFIG_SYS_CBSIZE 256
  73. #define CONFIG_SYS_PBSIZE 256
  74. #define CONFIG_SYS_MAXARGS 16
  75. #define CONFIG_SYS_BARGSIZE 512
  76. #define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
  77. /* SCIF */
  78. #define CONFIG_SCIF_CONSOLE 1
  79. #define CONFIG_CONS_SCIF1 1
  80. #define CONFIG_SCIF_EXT_CLOCK 1
  81. #undef CONFIG_SYS_CONSOLE_INFO_QUIET
  82. #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
  83. #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
  84. #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE)
  85. #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
  86. (SH7785LCR_SDRAM_SIZE) - \
  87. 4 * 1024 * 1024)
  88. #undef CONFIG_SYS_ALT_MEMTEST
  89. #undef CONFIG_SYS_MEMTEST_SCRATCH
  90. #undef CONFIG_SYS_LOADS_BAUD_CHANGE
  91. #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE)
  92. #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE)
  93. #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
  94. #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1)
  95. #define CONFIG_SYS_MONITOR_LEN (512 * 1024)
  96. #define CONFIG_SYS_MALLOC_LEN (512 * 1024)
  97. #define CONFIG_SYS_GBL_DATA_SIZE (256)
  98. #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
  99. /* FLASH */
  100. #define CONFIG_FLASH_CFI_DRIVER
  101. #define CONFIG_SYS_FLASH_CFI
  102. #undef CONFIG_SYS_FLASH_QUIET_TEST
  103. #define CONFIG_SYS_FLASH_EMPTY_INFO
  104. #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1)
  105. #define CONFIG_SYS_MAX_FLASH_SECT 512
  106. #define CONFIG_SYS_MAX_FLASH_BANKS 1
  107. #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \
  108. (0 * SH7785LCR_FLASH_BANK_SIZE) }
  109. #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
  110. #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
  111. #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
  112. #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
  113. #undef CONFIG_SYS_FLASH_PROTECTION
  114. #undef CONFIG_SYS_DIRECT_FLASH_TFTP
  115. /* R8A66597 */
  116. #define CONFIG_USB_R8A66597_HCD
  117. #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE
  118. #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
  119. #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
  120. #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
  121. /* PCI Controller */
  122. #define CONFIG_PCI
  123. #define CONFIG_SH4_PCI
  124. #define CONFIG_SH7780_PCI
  125. #if defined(CONFIG_SH_32BIT)
  126. #define CONFIG_SH7780_PCI_LSR 0x1ff00001
  127. #define CONFIG_SH7780_PCI_LAR 0x5f000000
  128. #define CONFIG_SH7780_PCI_BAR 0x5f000000
  129. #else
  130. #define CONFIG_SH7780_PCI_LSR 0x07f00001
  131. #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE
  132. #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE
  133. #endif
  134. #define CONFIG_PCI_PNP
  135. #define CONFIG_PCI_SCAN_SHOW 1
  136. #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */
  137. #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS
  138. #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */
  139. #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */
  140. #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS
  141. #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */
  142. #if defined(CONFIG_SH_32BIT)
  143. #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE
  144. #else
  145. #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE
  146. #endif
  147. #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE
  148. #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE
  149. /* Network device (RTL8169) support */
  150. #define CONFIG_NET_MULTI
  151. #define CONFIG_RTL8169
  152. /* ENV setting */
  153. #define CONFIG_ENV_IS_IN_FLASH
  154. #define CONFIG_ENV_OVERWRITE 1
  155. #define CONFIG_ENV_SECT_SIZE (256 * 1024)
  156. #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
  157. #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
  158. #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
  159. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
  160. /* Board Clock */
  161. /* The SCIF used external clock. system clock only used timer. */
  162. #define CONFIG_SYS_CLK_FREQ 50000000
  163. #define CONFIG_SYS_TMU_CLK_DIV 4
  164. #define CONFIG_SYS_HZ 1000
  165. #endif /* __SH7785LCR_H */