p3mx.h 18 KB

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  1. /*
  2. * (C) Copyright 2006
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * Based on original work by
  6. * Roel Loeffen, (C) Copyright 2006 Prodrive B.V.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /************************************************************************
  27. * p3mx.h - configuration for Prodrive P3M750 & P3M7448 boards
  28. *
  29. * The defines:
  30. * CONFIG_P3M750 or
  31. * CONFIG_P3M7448
  32. * are written into include/config.h by the "make xxx_config" command
  33. ***********************************************************************/
  34. #ifndef __CONFIG_H
  35. #define __CONFIG_H
  36. /*-----------------------------------------------------------------------
  37. * High Level Configuration Options
  38. *----------------------------------------------------------------------*/
  39. #define CONFIG_P3Mx /* used for both board versions */
  40. #if defined (CONFIG_P3M750)
  41. #define CONFIG_750FX /* 750GL/GX/FX */
  42. #define CONFIG_HIGH_BATS /* High BATs supported */
  43. #define CONFIG_SYS_BOARD_NAME "P3M750"
  44. #define CONFIG_SYS_BUS_CLK 100000000
  45. #define CONFIG_SYS_TCLK 100000000
  46. #elif defined (CONFIG_P3M7448)
  47. #define CONFIG_74xx
  48. #define CONFIG_SYS_BOARD_NAME "P3M7448"
  49. #define CONFIG_SYS_BUS_CLK 133333333
  50. #define CONFIG_SYS_TCLK 133333333
  51. #endif
  52. #define CONFIG_SYS_GT_DUAL_CPU /* also for JTAG even with one cpu */
  53. /* which initialization functions to call for this board */
  54. #define CONFIG_SYS_BOARD_ASM_INIT 1
  55. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  56. #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r() */
  57. /*-----------------------------------------------------------------------
  58. * Base addresses -- Note these are effective addresses where the
  59. * actual resources get mapped (not physical addresses)
  60. *----------------------------------------------------------------------*/
  61. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  62. #ifdef CONFIG_P3M750
  63. #define CONFIG_SYS_SDRAM1_BASE 0x10000000 /* each 256 MByte */
  64. #endif
  65. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  66. #if defined (CONFIG_P3M750)
  67. #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of flash banks */
  68. #define CONFIG_SYS_BOOT_SIZE _8M /* boot flash */
  69. #elif defined (CONFIG_P3M7448)
  70. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of flash banks */
  71. #define CONFIG_SYS_BOOT_SIZE _16M /* boot flash */
  72. #endif
  73. #define CONFIG_SYS_BOOT_SPACE CONFIG_SYS_FLASH_BASE /* BOOT_CS0 flash 0 */
  74. #define CONFIG_SYS_MONITOR_BASE 0xfff00000
  75. #define CONFIG_SYS_RESET_ADDRESS 0xfff00100
  76. #define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc */
  77. #define CONFIG_SYS_MISC_REGION_BASE 0xf0000000
  78. #define CONFIG_SYS_DFL_GT_REGS 0xf1000000 /* boot time GT_REGS */
  79. #define CONFIG_SYS_GT_REGS 0xf1000000 /* GT Registers are mapped here */
  80. #define CONFIG_SYS_INT_SRAM_BASE 0x42000000 /* GT offers 256k internal SRAM */
  81. /*-----------------------------------------------------------------------
  82. * Initial RAM & stack pointer (placed in internal SRAM)
  83. *----------------------------------------------------------------------*/
  84. /*
  85. * When locking data in cache you should point the CONFIG_SYS_INIT_RAM_ADDRESS
  86. * To an unused memory region. The stack will remain in cache until RAM
  87. * is initialized
  88. */
  89. #undef CONFIG_SYS_INIT_RAM_LOCK
  90. #define CONFIG_SYS_INIT_RAM_ADDR 0x42000000
  91. #define CONFIG_SYS_INIT_RAM_END 0x1000
  92. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for init data */
  93. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  94. /*-----------------------------------------------------------------------
  95. * Serial Port
  96. *----------------------------------------------------------------------*/
  97. #define CONFIG_MPSC /* MV64460 Serial */
  98. #define CONFIG_MPSC_PORT 0
  99. #define CONFIG_BAUDRATE 115200 /* console baudrate */
  100. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  101. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  102. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  103. /*-----------------------------------------------------------------------
  104. * Ethernet
  105. *----------------------------------------------------------------------*/
  106. /* Change the default ethernet port, use this define (options: 0, 1, 2) */
  107. #define CONFIG_SYS_ETH_PORT ETH_0
  108. #define CONFIG_NET_MULTI
  109. #define MV_ETH_DEVS 2
  110. #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
  111. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  112. /*-----------------------------------------------------------------------
  113. * FLASH related
  114. *----------------------------------------------------------------------*/
  115. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  116. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  117. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  118. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  119. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  120. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  121. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  122. #define CONFIG_SYS_FLASH_PROTECTION 1 /* use hardware flash protection */
  123. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  124. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  125. #if defined (CONFIG_P3M750)
  126. #define CONFIG_ENV_SECT_SIZE 0x20000 /* one sector (1 device) */
  127. #elif defined (CONFIG_P3M7448)
  128. #define CONFIG_ENV_SECT_SIZE 0x40000 /* two sectors (2 devices parallel */
  129. #endif
  130. #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
  131. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
  132. /*-----------------------------------------------------------------------
  133. * DDR SDRAM
  134. *----------------------------------------------------------------------*/
  135. #define CONFIG_MV64460_ECC
  136. /*-----------------------------------------------------------------------
  137. * I2C
  138. *----------------------------------------------------------------------*/
  139. #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed default */
  140. /* I2C RTC */
  141. #define CONFIG_RTC_M41T11 1
  142. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  143. #define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with linux */
  144. /*-----------------------------------------------------------------------
  145. * PCI stuff
  146. *----------------------------------------------------------------------*/
  147. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  148. #define PCI_HOST_FORCE 1 /* configure as pci host */
  149. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  150. #undef CONFIG_PCI /* include pci support */
  151. #ifdef CONFIG_PCI
  152. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  153. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  154. #define CONFIG_PCI_SCAN_SHOW /* show devices on bus */
  155. #endif /* CONFIG_PCI */
  156. /* PCI MEMORY MAP section */
  157. #define CONFIG_SYS_PCI0_MEM_BASE 0x80000000
  158. #define CONFIG_SYS_PCI0_MEM_SIZE _128M
  159. #define CONFIG_SYS_PCI1_MEM_BASE 0x88000000
  160. #define CONFIG_SYS_PCI1_MEM_SIZE _128M
  161. #define CONFIG_SYS_PCI0_0_MEM_SPACE (CONFIG_SYS_PCI0_MEM_BASE)
  162. #define CONFIG_SYS_PCI1_0_MEM_SPACE (CONFIG_SYS_PCI1_MEM_BASE)
  163. /* PCI I/O MAP section */
  164. #define CONFIG_SYS_PCI0_IO_BASE 0xfa000000
  165. #define CONFIG_SYS_PCI0_IO_SIZE _16M
  166. #define CONFIG_SYS_PCI1_IO_BASE 0xfb000000
  167. #define CONFIG_SYS_PCI1_IO_SIZE _16M
  168. #define CONFIG_SYS_PCI0_IO_SPACE (CONFIG_SYS_PCI0_IO_BASE)
  169. #define CONFIG_SYS_PCI0_IO_SPACE_PCI 0x00000000
  170. #define CONFIG_SYS_PCI1_IO_SPACE (CONFIG_SYS_PCI1_IO_BASE)
  171. #define CONFIG_SYS_PCI1_IO_SPACE_PCI 0x00000000
  172. #define CONFIG_SYS_ISA_IO_BASE_ADDRESS (CONFIG_SYS_PCI0_IO_BASE)
  173. #define CONFIG_SYS_PCI_IDSEL 0x30
  174. #undef CONFIG_BOOTARGS
  175. #define CONFIG_EXTRA_ENV_SETTINGS_COMMON \
  176. "netdev=eth0\0" \
  177. "nfsargs=setenv bootargs root=/dev/nfs rw " \
  178. "nfsroot=${serverip}:${rootpath}\0" \
  179. "ramargs=setenv bootargs root=/dev/ram rw\0" \
  180. "addip=setenv bootargs ${bootargs} " \
  181. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
  182. ":${hostname}:${netdev}:off panic=1\0" \
  183. "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
  184. "flash_nfs=run nfsargs addip addtty;" \
  185. "bootm ${kernel_addr}\0" \
  186. "flash_self=run ramargs addip addtty;" \
  187. "bootm ${kernel_addr} ${ramdisk_addr}\0" \
  188. "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
  189. "bootm\0" \
  190. "rootpath=/opt/eldk/ppc_6xx\0" \
  191. "u-boot=p3mx/u-boot/u-boot.bin\0" \
  192. "load=tftp 100000 ${u-boot}\0" \
  193. "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \
  194. "cp.b 100000 fff00000 40000;" \
  195. "setenv filesize;saveenv\0" \
  196. "upd=run load update\0" \
  197. "serverip=11.0.0.152\0"
  198. #if defined (CONFIG_P3M750)
  199. #define CONFIG_EXTRA_ENV_SETTINGS \
  200. CONFIG_EXTRA_ENV_SETTINGS_COMMON \
  201. "hostname=p3m750\0" \
  202. "bootfile=/tftpboot/p3mx/vxWorks.st\0" \
  203. "kernel_addr=fc000000\0" \
  204. "ramdisk_addr=fc180000\0" \
  205. "vxfile=p3m750/vxWorks\0" \
  206. "vxuser=ddg\0" \
  207. "vxpass=ddg\0" \
  208. "vxtarget=target\0" \
  209. "vxflags=0x8\0" \
  210. "vxargs=setenv bootargs mgi(0,0)host:${vxfile} h=${serverip} " \
  211. "e=${ipaddr} u=${vxuser} pw=${vxpass} tn=${vxtarget} " \
  212. "f=${vxflags}\0"
  213. #elif defined (CONFIG_P3M7448)
  214. #define CONFIG_EXTRA_ENV_SETTINGS \
  215. CONFIG_EXTRA_ENV_SETTINGS_COMMON \
  216. "hostname=p3m7448\0"
  217. #endif
  218. #if defined (CONFIG_P3M750)
  219. #define CONFIG_BOOTCOMMAND "tftp;run vxargs;bootvx"
  220. #elif defined (CONFIG_P3M7448)
  221. #define CONFIG_BOOTCOMMAND " "
  222. #endif
  223. #define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */
  224. /*
  225. * BOOTP options
  226. */
  227. #define CONFIG_BOOTP_SUBNETMASK
  228. #define CONFIG_BOOTP_GATEWAY
  229. #define CONFIG_BOOTP_HOSTNAME
  230. #define CONFIG_BOOTP_BOOTPATH
  231. #define CONFIG_BOOTP_BOOTFILESIZE
  232. /*
  233. * Command line configuration.
  234. */
  235. #include <config_cmd_default.h>
  236. #define CONFIG_CMD_ASKENV
  237. #define CONFIG_CMD_DATE
  238. #define CONFIG_CMD_DIAG
  239. #define CONFIG_CMD_ELF
  240. #define CONFIG_CMD_I2C
  241. #define CONFIG_CMD_IRQ
  242. #define CONFIG_CMD_MII
  243. #define CONFIG_CMD_NET
  244. #define CONFIG_CMD_NFS
  245. #define CONFIG_CMD_PING
  246. #define CONFIG_CMD_REGINFO
  247. #define CONFIG_CMD_PCI
  248. #define CONFIG_CMD_CACHE
  249. #define CONFIG_CMD_SDRAM
  250. /*-----------------------------------------------------------------------
  251. * Miscellaneous configurable options
  252. *----------------------------------------------------------------------*/
  253. #define CONFIG_SYS_HUSH_PARSER
  254. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  255. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  256. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  257. #if defined(CONFIG_CMD_KGDB)
  258. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  259. #else
  260. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  261. #endif
  262. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  263. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  264. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  265. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  266. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  267. #define CONFIG_SYS_LOAD_ADDR 0x08000000 /* default load address */
  268. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  269. #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
  270. #define CONFIG_LOOPW 1 /* enable loopw command */
  271. #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
  272. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  273. #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
  274. /*-----------------------------------------------------------------------
  275. * Marvell MV64460 config settings
  276. *----------------------------------------------------------------------*/
  277. /* Reset values for Port behavior (8bit/ 32bit, etc.) only corrected device width */
  278. #if defined (CONFIG_P3M750)
  279. #define CONFIG_SYS_BOOT_PAR 0x8FDFF87F /* 16 bit flash, disable burst*/
  280. #elif defined (CONFIG_P3M7448)
  281. #define CONFIG_SYS_BOOT_PAR 0x8FEFFFFF /* 32 bit flash, burst enabled */
  282. #endif
  283. /*
  284. * MPP[0] Serial Port 0 TxD TxD OUT Connected to P14 (buffered)
  285. * MPP[1] Serial Port 0 RxD RxD IN Connected to P14 (buffered)
  286. * MPP[2] NC
  287. * MPP[3] Serial Port 1 TxD TxD OUT Connected to P14 (buffered)
  288. * MPP[4] PCI Monarch# GPIO IN Connected to P12
  289. * MPP[5] Serial Port 1 RxD RxD IN Connected to P14 (buffered)
  290. * MPP[6] PMC Carrier Interrupt 0 Int IN Connected to P14
  291. * MPP[7] PMC Carrier Interrupt 1 Int IN Connected to P14
  292. * MPP[8] Reserved Do not use
  293. * MPP[9] Reserved Do not use
  294. * MPP[10] Reserved Do not use
  295. * MPP[11] Reserved Do not use
  296. * MPP[12] Phy 0 Interrupt Int IN
  297. * MPP[13] Phy 1 Interrupt Int IN
  298. * MPP[14] NC
  299. * MPP[15] NC
  300. * MPP[16] PCI Interrupt C Int IN Connected to P11
  301. * MPP[17] PCI Interrupt D Int IN Connected to P11
  302. * MPP[18] Watchdog NMI# GPIO IN Connected to MPP[24]
  303. * MPP[19] Watchdog Expired# WDE OUT Connected to rst logic
  304. * MPP[20] Watchdog Status WD_STS IN Read back of rst by watchdog
  305. * MPP[21] NC
  306. * MPP[22] GP LED Green GPIO OUT
  307. * MPP[23] GP LED Red GPIO OUT
  308. * MPP[24] Watchdog NMI# Int OUT
  309. * MPP[25] NC
  310. * MPP[26] NC
  311. * MPP[27] PCI Interrupt A Int IN Connected to P11
  312. * MPP[28] NC
  313. * MPP[29] PCI Interrupt B Int IN Connected to P11
  314. * MPP[30] Module reset GPIO OUT Board reset
  315. * MPP[31] PCI EReady GPIO IN Connected to P12
  316. */
  317. #define CONFIG_SYS_MPP_CONTROL_0 0x00303022
  318. #define CONFIG_SYS_MPP_CONTROL_1 0x00000000
  319. #define CONFIG_SYS_MPP_CONTROL_2 0x00004000
  320. #define CONFIG_SYS_MPP_CONTROL_3 0x00000004
  321. #define CONFIG_SYS_GPP_LEVEL_CONTROL 0x280730D0
  322. /*----------------------------------------------------------------------
  323. * Initial BAT mappings
  324. */
  325. /* NOTES:
  326. * 1) GUARDED and WRITE_THRU not allowed in IBATS
  327. * 2) CACHEINHIBIT and WRITETHROUGH not allowed together in same BAT
  328. */
  329. /* SDRAM */
  330. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  331. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  332. #define CONFIG_SYS_DBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
  333. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  334. /* init ram */
  335. #define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW | BATL_MEMCOHERENCE)
  336. #define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_256K | BATU_VS | BATU_VP)
  337. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  338. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  339. /* PCI0, PCI1 in one BAT */
  340. #define CONFIG_SYS_IBAT2L BATL_NO_ACCESS
  341. #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U
  342. #define CONFIG_SYS_DBAT2L (CONFIG_SYS_PCI0_MEM_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  343. #define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI0_MEM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  344. /* GT regs, bootrom, all the devices, PCI I/O */
  345. #define CONFIG_SYS_IBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW)
  346. #define CONFIG_SYS_IBAT3U (CONFIG_SYS_MISC_REGION_BASE | BATU_VS | BATU_VP | BATU_BL_256M)
  347. #define CONFIG_SYS_DBAT3L (CONFIG_SYS_MISC_REGION_BASE | BATL_CACHEINHIBIT | BATL_PP_RW | BATL_GUARDEDSTORAGE)
  348. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  349. #define CONFIG_SYS_IBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT)
  350. #define CONFIG_SYS_IBAT4U (CONFIG_SYS_SDRAM1_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
  351. #define CONFIG_SYS_DBAT4L (CONFIG_SYS_SDRAM1_BASE | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  352. #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
  353. /* set rest out of range for Linux !!!!!!!!!!! */
  354. /* IBAT5 and DBAT5 */
  355. #define CONFIG_SYS_IBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  356. #define CONFIG_SYS_IBAT5U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  357. #define CONFIG_SYS_DBAT5L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  358. #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
  359. /* IBAT6 and DBAT6 */
  360. #define CONFIG_SYS_IBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  361. #define CONFIG_SYS_IBAT6U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  362. #define CONFIG_SYS_DBAT6L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  363. #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
  364. /* IBAT7 and DBAT7 */
  365. #define CONFIG_SYS_IBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT)
  366. #define CONFIG_SYS_IBAT7U (0x20000000 | BATU_BL_256M | BATU_VS | BATU_VP)
  367. #define CONFIG_SYS_DBAT7L (0x20000000 | BATL_PP_RW | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
  368. #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
  369. /*
  370. * For booting Linux, the board info and command line data
  371. * have to be in the first 8 MB of memory, since this is
  372. * the maximum mapped by the Linux kernel during initialization.
  373. */
  374. #define CONFIG_SYS_BOOTMAPSZ (8<<20) /* Initial Memory map for Linux */
  375. #define CONFIG_SYS_VXWORKS_MAC_PTR 0x42010000 /* use some memory in SRAM that's not used!!! */
  376. /*-----------------------------------------------------------------------
  377. * Cache Configuration
  378. */
  379. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
  380. #if defined(CONFIG_CMD_KGDB)
  381. #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  382. #endif
  383. /*-----------------------------------------------------------------------
  384. * L2CR setup -- make sure this is right for your board!
  385. * look in include/mpc74xx.h for the defines used here
  386. */
  387. #define CONFIG_SYS_L2
  388. #if defined (CONFIG_750CX) || defined (CONFIG_750FX)
  389. #define L2_INIT 0
  390. #else
  391. #define L2_INIT (L2CR_L2SIZ_2M | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
  392. L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
  393. #endif
  394. #define L2_ENABLE (L2_INIT | L2CR_L2E)
  395. /*
  396. * Internal Definitions
  397. *
  398. * Boot Flags
  399. */
  400. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  401. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  402. #endif /* __CONFIG_H */