omap3_beagle.h 10 KB

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  1. /*
  2. * (C) Copyright 2006-2008
  3. * Texas Instruments.
  4. * Richard Woodruff <r-woodruff2@ti.com>
  5. * Syed Mohammed Khasim <x0khasim@ti.com>
  6. *
  7. * Configuration settings for the TI OMAP3530 Beagle board.
  8. *
  9. * See file CREDITS for list of people who contributed to this
  10. * project.
  11. *
  12. * This program is free software; you can redistribute it and/or
  13. * modify it under the terms of the GNU General Public License as
  14. * published by the Free Software Foundation; either version 2 of
  15. * the License, or (at your option) any later version.
  16. *
  17. * This program is distributed in the hope that it will be useful,
  18. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  20. * GNU General Public License for more details.
  21. *
  22. * You should have received a copy of the GNU General Public License
  23. * along with this program; if not, write to the Free Software
  24. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25. * MA 02111-1307 USA
  26. */
  27. #ifndef __CONFIG_H
  28. #define __CONFIG_H
  29. /*
  30. * High Level Configuration Options
  31. */
  32. #define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */
  33. #define CONFIG_OMAP 1 /* in a TI OMAP core */
  34. #define CONFIG_OMAP34XX 1 /* which is a 34XX */
  35. #define CONFIG_OMAP3430 1 /* which is in a 3430 */
  36. #define CONFIG_OMAP3_BEAGLE 1 /* working with BEAGLE */
  37. #define CONFIG_SDRC /* The chip has SDRC controller */
  38. #include <asm/arch/cpu.h> /* get chip and board defs */
  39. #include <asm/arch/omap3.h>
  40. /*
  41. * Display CPU and Board information
  42. */
  43. #define CONFIG_DISPLAY_CPUINFO 1
  44. #define CONFIG_DISPLAY_BOARDINFO 1
  45. /* Clock Defines */
  46. #define V_OSCK 26000000 /* Clock output from T2 */
  47. #define V_SCLK (V_OSCK >> 1)
  48. #undef CONFIG_USE_IRQ /* no support for IRQs */
  49. #define CONFIG_MISC_INIT_R
  50. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  51. #define CONFIG_SETUP_MEMORY_TAGS 1
  52. #define CONFIG_INITRD_TAG 1
  53. #define CONFIG_REVISION_TAG 1
  54. /*
  55. * Size of malloc() pool
  56. */
  57. #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
  58. /* Sector */
  59. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  60. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* bytes reserved for */
  61. /* initial data */
  62. /*
  63. * Hardware drivers
  64. */
  65. /*
  66. * NS16550 Configuration
  67. */
  68. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  69. #define CONFIG_SYS_NS16550
  70. #define CONFIG_SYS_NS16550_SERIAL
  71. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  72. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  73. /*
  74. * select serial console configuration
  75. */
  76. #define CONFIG_CONS_INDEX 3
  77. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  78. #define CONFIG_SERIAL3 3 /* UART3 on Beagle Rev 2 */
  79. /* allow to overwrite serial and ethaddr */
  80. #define CONFIG_ENV_OVERWRITE
  81. #define CONFIG_BAUDRATE 115200
  82. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  83. 115200}
  84. #define CONFIG_MMC 1
  85. #define CONFIG_OMAP3_MMC 1
  86. #define CONFIG_DOS_PARTITION 1
  87. /* DDR - I use Micron DDR */
  88. #define CONFIG_OMAP3_MICRON_DDR 1
  89. /* USB */
  90. #define CONFIG_MUSB_UDC 1
  91. #define CONFIG_USB_OMAP3 1
  92. #define CONFIG_TWL4030_USB 1
  93. /* USB device configuration */
  94. #define CONFIG_USB_DEVICE 1
  95. #define CONFIG_USB_TTY 1
  96. #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
  97. /* Change these to suit your needs */
  98. #define CONFIG_USBD_VENDORID 0x0451
  99. #define CONFIG_USBD_PRODUCTID 0x5678
  100. #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
  101. #define CONFIG_USBD_PRODUCT_NAME "Beagle"
  102. /* commands to include */
  103. #include <config_cmd_default.h>
  104. #define CONFIG_CMD_EXT2 /* EXT2 Support */
  105. #define CONFIG_CMD_FAT /* FAT support */
  106. #define CONFIG_CMD_JFFS2 /* JFFS2 Support */
  107. #define CONFIG_CMD_MTDPARTS /* Enable MTD parts commands */
  108. #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
  109. #define MTDIDS_DEFAULT "nand0=nand"
  110. #define MTDPARTS_DEFAULT "mtdparts=nand:512k(x-loader),"\
  111. "1920k(u-boot),128k(u-boot-env),"\
  112. "4m(kernel),-(fs)"
  113. #define CONFIG_CMD_I2C /* I2C serial bus support */
  114. #define CONFIG_CMD_MMC /* MMC support */
  115. #define CONFIG_CMD_NAND /* NAND support */
  116. #undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
  117. #undef CONFIG_CMD_FPGA /* FPGA configuration Support */
  118. #undef CONFIG_CMD_IMI /* iminfo */
  119. #undef CONFIG_CMD_IMLS /* List all found images */
  120. #undef CONFIG_CMD_NET /* bootp, tftpboot, rarpboot */
  121. #undef CONFIG_CMD_NFS /* NFS support */
  122. #define CONFIG_SYS_NO_FLASH
  123. #define CONFIG_HARD_I2C 1
  124. #define CONFIG_SYS_I2C_SPEED 100000
  125. #define CONFIG_SYS_I2C_SLAVE 1
  126. #define CONFIG_SYS_I2C_BUS 0
  127. #define CONFIG_SYS_I2C_BUS_SELECT 1
  128. #define CONFIG_DRIVER_OMAP34XX_I2C 1
  129. /*
  130. * TWL4030
  131. */
  132. #define CONFIG_TWL4030_POWER 1
  133. #define CONFIG_TWL4030_LED 1
  134. /*
  135. * Board NAND Info.
  136. */
  137. #define CONFIG_NAND_OMAP_GPMC
  138. #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */
  139. /* to access nand */
  140. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  141. /* to access nand at */
  142. /* CS0 */
  143. #define GPMC_NAND_ECC_LP_x16_LAYOUT 1
  144. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */
  145. /* devices */
  146. #define CONFIG_JFFS2_NAND
  147. /* nand device jffs2 lives on */
  148. #define CONFIG_JFFS2_DEV "nand0"
  149. /* start of jffs2 partition */
  150. #define CONFIG_JFFS2_PART_OFFSET 0x680000
  151. #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* size of jffs2 */
  152. /* partition */
  153. /* Environment information */
  154. #define CONFIG_BOOTDELAY 10
  155. #define CONFIG_EXTRA_ENV_SETTINGS \
  156. "loadaddr=0x82000000\0" \
  157. "usbtty=cdc_acm\0" \
  158. "console=ttyS2,115200n8\0" \
  159. "vram=12M\0" \
  160. "dvimode=1024x768MR-16@60\0" \
  161. "defaultdisplay=dvi\0" \
  162. "mmcroot=/dev/mmcblk0p2 rw\0" \
  163. "mmcrootfstype=ext3 rootwait\0" \
  164. "nandroot=/dev/mtdblock4 rw\0" \
  165. "nandrootfstype=jffs2\0" \
  166. "mmcargs=setenv bootargs console=${console} " \
  167. "vram=${vram} " \
  168. "omapfb.mode=dvi:${dvimode} " \
  169. "omapfb.debug=y " \
  170. "omapdss.def_disp=${defaultdisplay} " \
  171. "root=${mmcroot} " \
  172. "rootfstype=${mmcrootfstype}\0" \
  173. "nandargs=setenv bootargs console=${console} " \
  174. "vram=${vram} " \
  175. "omapfb.mode=dvi:${dvimode} " \
  176. "omapfb.debug=y " \
  177. "omapdss.def_disp=${defaultdisplay} " \
  178. "root=${nandroot} " \
  179. "rootfstype=${nandrootfstype}\0" \
  180. "loadbootscript=fatload mmc 0 ${loadaddr} boot.scr\0" \
  181. "bootscript=echo Running bootscript from mmc ...; " \
  182. "source ${loadaddr}\0" \
  183. "loaduimage=fatload mmc 0 ${loadaddr} uImage\0" \
  184. "mmcboot=echo Booting from mmc ...; " \
  185. "run mmcargs; " \
  186. "bootm ${loadaddr}\0" \
  187. "nandboot=echo Booting from nand ...; " \
  188. "run nandargs; " \
  189. "nand read ${loadaddr} 280000 400000; " \
  190. "bootm ${loadaddr}\0" \
  191. #define CONFIG_BOOTCOMMAND \
  192. "if mmc init; then " \
  193. "if run loadbootscript; then " \
  194. "run bootscript; " \
  195. "else " \
  196. "if run loaduimage; then " \
  197. "run mmcboot; " \
  198. "else run nandboot; " \
  199. "fi; " \
  200. "fi; " \
  201. "else run nandboot; fi"
  202. #define CONFIG_AUTO_COMPLETE 1
  203. /*
  204. * Miscellaneous configurable options
  205. */
  206. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  207. #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
  208. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  209. #define CONFIG_SYS_PROMPT "OMAP3 beagleboard.org # "
  210. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  211. /* Print Buffer Size */
  212. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
  213. sizeof(CONFIG_SYS_PROMPT) + 16)
  214. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  215. /* Boot Argument Buffer Size */
  216. #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
  217. #define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0) /* memtest */
  218. /* works on */
  219. #define CONFIG_SYS_MEMTEST_END (OMAP34XX_SDRC_CS0 + \
  220. 0x01F00000) /* 31MB */
  221. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */
  222. /* load address */
  223. /*
  224. * OMAP3 has 12 GP timers, they can be driven by the system clock
  225. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  226. * This rate is divided by a local divisor.
  227. */
  228. #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
  229. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  230. #define CONFIG_SYS_HZ 1000
  231. /*-----------------------------------------------------------------------
  232. * Stack sizes
  233. *
  234. * The stack sizes are set up in start.S using the settings below
  235. */
  236. #define CONFIG_STACKSIZE (128 << 10) /* regular stack 128 KiB */
  237. #ifdef CONFIG_USE_IRQ
  238. #define CONFIG_STACKSIZE_IRQ (4 << 10) /* IRQ stack 4 KiB */
  239. #define CONFIG_STACKSIZE_FIQ (4 << 10) /* FIQ stack 4 KiB */
  240. #endif
  241. /*-----------------------------------------------------------------------
  242. * Physical Memory Map
  243. */
  244. #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */
  245. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  246. #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */
  247. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  248. /* SDRAM Bank Allocation method */
  249. #define SDRC_R_B_C 1
  250. /*-----------------------------------------------------------------------
  251. * FLASH and environment organization
  252. */
  253. /* **** PISMO SUPPORT *** */
  254. /* Configure the PISMO */
  255. #define PISMO1_NAND_SIZE GPMC_SIZE_128M
  256. #define PISMO1_ONEN_SIZE GPMC_SIZE_128M
  257. #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors on */
  258. /* one chip */
  259. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  260. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  261. #define CONFIG_SYS_FLASH_BASE boot_flash_base
  262. /* Monitor at start of flash */
  263. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  264. #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP
  265. #define CONFIG_ENV_IS_IN_NAND 1
  266. #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */
  267. #define SMNAND_ENV_OFFSET 0x260000 /* environment starts here */
  268. #define CONFIG_SYS_ENV_SECT_SIZE boot_flash_sec
  269. #define CONFIG_ENV_OFFSET boot_flash_off
  270. #define CONFIG_ENV_ADDR SMNAND_ENV_OFFSET
  271. /*-----------------------------------------------------------------------
  272. * CFI FLASH driver setup
  273. */
  274. /* timeout values are in ticks */
  275. #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  276. #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  277. /* Flash banks JFFS2 should use */
  278. #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  279. CONFIG_SYS_MAX_NAND_DEVICE)
  280. #define CONFIG_SYS_JFFS2_MEM_NAND
  281. /* use flash_info[2] */
  282. #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  283. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  284. #ifndef __ASSEMBLY__
  285. extern unsigned int boot_flash_base;
  286. extern volatile unsigned int boot_flash_env_addr;
  287. extern unsigned int boot_flash_off;
  288. extern unsigned int boot_flash_sec;
  289. extern unsigned int boot_flash_type;
  290. #endif
  291. #endif /* __CONFIG_H */