lpd7a404-10.h 2.7 KB

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  1. /*
  2. * See file CREDITS for list of people who contributed to this
  3. * project.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. /*
  21. * Logic LH7A400-10 card engine
  22. */
  23. #ifndef __LPD7A404_10_H
  24. #define __LPD7A404_10_H
  25. #define CONFIG_ARM920T 1 /* arm920t core */
  26. #define CONFIG_LH7A40X 1 /* Sharp LH7A40x SoC family */
  27. #define CONFIG_LH7A404 1 /* Sharp LH7A404 SoC */
  28. /* The system clock PLL input frequency */
  29. #define CONFIG_SYS_CLK_FREQ 14745600 /* System Clock PLL Input (Hz) */
  30. /* ticks per second */
  31. #define CONFIG_SYS_HZ (508469)
  32. /*-----------------------------------------------------------------------
  33. * Stack sizes
  34. *
  35. * The stack sizes are set up in start.S using the settings below
  36. */
  37. #define CONFIG_STACKSIZE (128*1024) /* regular stack */
  38. #ifdef CONFIG_USE_IRQ
  39. #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
  40. #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
  41. #endif
  42. /*-----------------------------------------------------------------------
  43. * Physical Memory Map
  44. */
  45. #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */
  46. #define PHYS_SDRAM_1 0xc0000000 /* SDRAM Bank #1 */
  47. #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */
  48. #define CONFIG_SYS_FLASH_BASE 0x00000000 /* Flash Bank #1 */
  49. /*-----------------------------------------------------------------------
  50. * FLASH and environment organization
  51. */
  52. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  53. #define CONFIG_SYS_MAX_FLASH_SECT (64) /* max number of sectors on one chip */
  54. /* timeout values are in ticks */
  55. #define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
  56. #define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */
  57. /*----------------------------------------------------------------------
  58. * Using SMC91C111 LAN chip
  59. *
  60. * Default IO base of chip is 0x300, Card Engine has this address lines
  61. * (LAN chip) tied to Vcc, so we just care about the chip select
  62. */
  63. #define CONFIG_NET_MULTI
  64. #define CONFIG_SMC91111
  65. #define CONFIG_SMC91111_BASE (0x70000000)
  66. #undef CONFIG_SMC_USE_32_BIT
  67. #endif /* __LPD7A404_10_H */