canyonlands.h 34 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Stefan Roese, DENX Software Engineering, sr@denx.de.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18. * MA 02111-1307 USA
  19. */
  20. /************************************************************************
  21. * canyonlands.h - configuration for Canyonlands (460EX)
  22. ***********************************************************************/
  23. #ifndef __CONFIG_H
  24. #define __CONFIG_H
  25. /*-----------------------------------------------------------------------
  26. * High Level Configuration Options
  27. *----------------------------------------------------------------------*/
  28. /*
  29. * This config file is used for Canyonlands (460EX) Glacier (460GT)
  30. * and Arches dual (460GT)
  31. */
  32. #ifdef CONFIG_CANYONLANDS
  33. #define CONFIG_460EX 1 /* Specific PPC460EX */
  34. #define CONFIG_HOSTNAME canyonlands
  35. #else
  36. #define CONFIG_460GT 1 /* Specific PPC460GT */
  37. #ifdef CONFIG_GLACIER
  38. #define CONFIG_HOSTNAME glacier
  39. #else
  40. #define CONFIG_HOSTNAME arches
  41. #define CONFIG_USE_NETDEV eth1
  42. #define CONFIG_BD_NUM_CPUS 2
  43. #endif
  44. #endif
  45. #define CONFIG_440 1
  46. #define CONFIG_4xx 1 /* ... PPC4xx family */
  47. /*
  48. * Include common defines/options for all AMCC eval boards
  49. */
  50. #include "amcc-common.h"
  51. #define CONFIG_SYS_CLK_FREQ 66666667 /* external freq to pll */
  52. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  53. #define CONFIG_BOARD_EARLY_INIT_R 1 /* Call board_early_init_r */
  54. #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
  55. #define CONFIG_BOARD_TYPES 1 /* support board types */
  56. /*-----------------------------------------------------------------------
  57. * Base addresses -- Note these are effective addresses where the
  58. * actual resources get mapped (not physical addresses)
  59. *----------------------------------------------------------------------*/
  60. #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
  61. #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
  62. #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  63. #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
  64. #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000 /* smallest incr for PCIe port */
  65. #define CONFIG_SYS_PCIE_BASE 0xc4000000 /* PCIe UTL regs */
  66. #define CONFIG_SYS_PCIE0_CFGBASE 0xc0000000
  67. #define CONFIG_SYS_PCIE1_CFGBASE 0xc1000000
  68. #define CONFIG_SYS_PCIE0_XCFGBASE 0xc3000000
  69. #define CONFIG_SYS_PCIE1_XCFGBASE 0xc3001000
  70. /*
  71. * BCSR bits as defined in the Canyonlands board user manual.
  72. */
  73. #define BCSR_USBCTRL_OTG_RST 0x32
  74. #define BCSR_USBCTRL_HOST_RST 0x01
  75. #define BCSR_SELECT_PCIE 0x10
  76. #define CONFIG_SYS_PCIE0_UTLBASE 0xc08010000ULL /* 36bit physical addr */
  77. /* base address of inbound PCIe window */
  78. #define CONFIG_SYS_PCIE_INBOUND_BASE 0x000000000ULL /* 36bit physical addr */
  79. /* EBC stuff */
  80. #if !defined(CONFIG_ARCHES)
  81. #define CONFIG_SYS_BCSR_BASE 0xE1000000
  82. #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* later mapped to this addr */
  83. #define CONFIG_SYS_FLASH_SIZE (64 << 20)
  84. #else
  85. #define CONFIG_SYS_FPGA_BASE 0xE1000000
  86. #define CONFIG_SYS_CPLD_ADDR (CONFIG_SYS_FPGA_BASE + 0x00080000)
  87. #define CONFIG_SYS_CPLD_DATA (CONFIG_SYS_FPGA_BASE + 0x00080002)
  88. #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* later mapped to this addr */
  89. #define CONFIG_SYS_FLASH_SIZE (32 << 20)
  90. #endif
  91. #define CONFIG_SYS_NAND_ADDR 0xE0000000
  92. #define CONFIG_SYS_BOOT_BASE_ADDR 0xFF000000 /* EBC Boot Space: 0xFF000000 */
  93. #define CONFIG_SYS_FLASH_BASE_PHYS_H 0x4
  94. #define CONFIG_SYS_FLASH_BASE_PHYS_L 0xCC000000
  95. #define CONFIG_SYS_FLASH_BASE_PHYS (((u64)CONFIG_SYS_FLASH_BASE_PHYS_H << 32) | \
  96. (u64)CONFIG_SYS_FLASH_BASE_PHYS_L)
  97. #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */
  98. #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */
  99. #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000
  100. #define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */
  101. #define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */
  102. /*-----------------------------------------------------------------------
  103. * Initial RAM & stack pointer (placed in OCM)
  104. *----------------------------------------------------------------------*/
  105. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_BASE /* OCM */
  106. #define CONFIG_SYS_INIT_RAM_END (4 << 10)
  107. #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data */
  108. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  109. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  110. /*-----------------------------------------------------------------------
  111. * Serial Port
  112. *----------------------------------------------------------------------*/
  113. #undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */
  114. /*-----------------------------------------------------------------------
  115. * Environment
  116. *----------------------------------------------------------------------*/
  117. /*
  118. * Define here the location of the environment variables (FLASH).
  119. */
  120. #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  121. #define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
  122. #define CONFIG_SYS_NOR_CS 0 /* NOR chip connected to CSx */
  123. #define CONFIG_SYS_NAND_CS 3 /* NAND chip connected to CSx */
  124. #else
  125. #define CONFIG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */
  126. #define CONFIG_SYS_NOR_CS 3 /* NOR chip connected to CSx */
  127. #define CONFIG_SYS_NAND_CS 0 /* NAND chip connected to CSx */
  128. #define CONFIG_ENV_IS_EMBEDDED 1 /* use embedded environment */
  129. #endif
  130. /*
  131. * IPL (Initial Program Loader, integrated inside CPU)
  132. * Will load first 4k from NAND (SPL) into cache and execute it from there.
  133. *
  134. * SPL (Secondary Program Loader)
  135. * Will load special U-Boot version (NUB) from NAND and execute it. This SPL
  136. * has to fit into 4kByte. It sets up the CPU and configures the SDRAM
  137. * controller and the NAND controller so that the special U-Boot image can be
  138. * loaded from NAND to SDRAM.
  139. *
  140. * NUB (NAND U-Boot)
  141. * This NAND U-Boot (NUB) is a special U-Boot version which can be started
  142. * from RAM. Therefore it mustn't (re-)configure the SDRAM controller.
  143. *
  144. * On 440EPx the SPL is copied to SDRAM before the NAND controller is
  145. * set up. While still running from cache, I experienced problems accessing
  146. * the NAND controller. sr - 2006-08-25
  147. *
  148. * This is the first official implementation of booting from 2k page sized
  149. * NAND devices (e.g. Micron 29F2G08AA 256Mbit * 8)
  150. */
  151. #define CONFIG_SYS_NAND_BOOT_SPL_SRC 0xfffff000 /* SPL location */
  152. #define CONFIG_SYS_NAND_BOOT_SPL_SIZE (4 << 10) /* SPL size */
  153. #define CONFIG_SYS_NAND_BOOT_SPL_DST (CONFIG_SYS_OCM_BASE + (12 << 10)) /* Copy SPL here */
  154. #define CONFIG_SYS_NAND_U_BOOT_DST 0x01000000 /* Load NUB to this addr */
  155. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST /* Start NUB from */
  156. /* this addr */
  157. #define CONFIG_SYS_NAND_BOOT_SPL_DELTA (CONFIG_SYS_NAND_BOOT_SPL_SRC - CONFIG_SYS_NAND_BOOT_SPL_DST)
  158. /*
  159. * Define the partitioning of the NAND chip (only RAM U-Boot is needed here)
  160. */
  161. #define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10) /* Offset to RAM U-Boot image */
  162. #define CONFIG_SYS_NAND_U_BOOT_SIZE (1 << 20) /* Size of RAM U-Boot image */
  163. /*
  164. * Now the NAND chip has to be defined (no autodetection used!)
  165. */
  166. #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) /* NAND chip page size */
  167. #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) /* NAND chip block size */
  168. #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / CONFIG_SYS_NAND_PAGE_SIZE)
  169. /* NAND chip page count */
  170. #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 /* Location of bad block marker*/
  171. #define CONFIG_SYS_NAND_5_ADDR_CYCLE /* Fifth addr used (<=128MB) */
  172. #define CONFIG_SYS_NAND_ECCSIZE 256
  173. #define CONFIG_SYS_NAND_ECCBYTES 3
  174. #define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / CONFIG_SYS_NAND_ECCSIZE)
  175. #define CONFIG_SYS_NAND_OOBSIZE 64
  176. #define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * CONFIG_SYS_NAND_ECCSTEPS)
  177. #define CONFIG_SYS_NAND_ECCPOS {40, 41, 42, 43, 44, 45, 46, 47, \
  178. 48, 49, 50, 51, 52, 53, 54, 55, \
  179. 56, 57, 58, 59, 60, 61, 62, 63}
  180. #ifdef CONFIG_ENV_IS_IN_NAND
  181. /*
  182. * For NAND booting the environment is embedded in the U-Boot image. Please take
  183. * look at the file board/amcc/canyonlands/u-boot-nand.lds for details.
  184. */
  185. #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
  186. #define CONFIG_ENV_OFFSET (CONFIG_SYS_NAND_U_BOOT_OFFS + CONFIG_ENV_SIZE)
  187. #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)
  188. #endif
  189. /*-----------------------------------------------------------------------
  190. * FLASH related
  191. *----------------------------------------------------------------------*/
  192. #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
  193. #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
  194. #define CONFIG_SYS_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */
  195. #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
  196. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  197. #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
  198. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  199. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  200. #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
  201. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  202. #ifdef CONFIG_ENV_IS_IN_FLASH
  203. #define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
  204. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
  205. #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
  206. /* Address and size of Redundant Environment Sector */
  207. #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
  208. #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
  209. #endif /* CONFIG_ENV_IS_IN_FLASH */
  210. /*-----------------------------------------------------------------------
  211. * NAND-FLASH related
  212. *----------------------------------------------------------------------*/
  213. #define CONFIG_SYS_MAX_NAND_DEVICE 1
  214. #define CONFIG_SYS_NAND_BASE (CONFIG_SYS_NAND_ADDR + CONFIG_SYS_NAND_CS)
  215. #define CONFIG_SYS_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */
  216. /*------------------------------------------------------------------------------
  217. * DDR SDRAM
  218. *----------------------------------------------------------------------------*/
  219. #if !defined(CONFIG_NAND_U_BOOT)
  220. #if !defined(CONFIG_ARCHES)
  221. /*
  222. * NAND booting U-Boot version uses a fixed initialization, since the whole
  223. * I2C SPD DIMM autodetection/calibration doesn't fit into the 4k of boot
  224. * code.
  225. */
  226. #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
  227. #define SPD_EEPROM_ADDRESS {0x50, 0x51} /* SPD i2c spd addresses*/
  228. #define CONFIG_DDR_ECC 1 /* with ECC support */
  229. #define CONFIG_DDR_RQDC_FIXED 0x80000038 /* fixed value for RQDC */
  230. #else /* defined(CONFIG_ARCHES) */
  231. #define CONFIG_AUTOCALIB "silent\0" /* default is non-verbose */
  232. #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION /* IBM DDR autocalibration */
  233. #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION /* dynamic DDR autocal debug */
  234. #undef CONFIG_PPC4xx_DDR_METHOD_A
  235. /* DDR1/2 SDRAM Device Control Register Data Values */
  236. /* Memory Queue */
  237. #define CONFIG_SYS_SDRAM_R0BAS 0x0000f000
  238. #define CONFIG_SYS_SDRAM_R1BAS 0x00000000
  239. #define CONFIG_SYS_SDRAM_R2BAS 0x00000000
  240. #define CONFIG_SYS_SDRAM_R3BAS 0x00000000
  241. #define CONFIG_SYS_SDRAM_PLBADDULL 0x00000000
  242. #define CONFIG_SYS_SDRAM_PLBADDUHB 0x00000008
  243. #define CONFIG_SYS_SDRAM_CONF1LL 0x00001080
  244. #define CONFIG_SYS_SDRAM_CONF1HB 0x00001080
  245. #define CONFIG_SYS_SDRAM_CONFPATHB 0x10a68000
  246. /* SDRAM Controller */
  247. #define CONFIG_SYS_SDRAM0_MB0CF 0x00000701
  248. #define CONFIG_SYS_SDRAM0_MB1CF 0x00000000
  249. #define CONFIG_SYS_SDRAM0_MB2CF 0x00000000
  250. #define CONFIG_SYS_SDRAM0_MB3CF 0x00000000
  251. #define CONFIG_SYS_SDRAM0_MCOPT1 0x05322000
  252. #define CONFIG_SYS_SDRAM0_MCOPT2 0x00000000
  253. #define CONFIG_SYS_SDRAM0_MODT0 0x01000000
  254. #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
  255. #define CONFIG_SYS_SDRAM0_MODT2 0x00000000
  256. #define CONFIG_SYS_SDRAM0_MODT3 0x00000000
  257. #define CONFIG_SYS_SDRAM0_CODT 0x00800021
  258. #define CONFIG_SYS_SDRAM0_RTR 0x06180000
  259. #define CONFIG_SYS_SDRAM0_INITPLR0 0xb5380000
  260. #define CONFIG_SYS_SDRAM0_INITPLR1 0x82100400
  261. #define CONFIG_SYS_SDRAM0_INITPLR2 0x80820000
  262. #define CONFIG_SYS_SDRAM0_INITPLR3 0x80830000
  263. #define CONFIG_SYS_SDRAM0_INITPLR4 0x80810040
  264. #define CONFIG_SYS_SDRAM0_INITPLR5 0x80800532
  265. #define CONFIG_SYS_SDRAM0_INITPLR6 0x82100400
  266. #define CONFIG_SYS_SDRAM0_INITPLR7 0x8a080000
  267. #define CONFIG_SYS_SDRAM0_INITPLR8 0x8a080000
  268. #define CONFIG_SYS_SDRAM0_INITPLR9 0x8a080000
  269. #define CONFIG_SYS_SDRAM0_INITPLR10 0x8a080000
  270. #define CONFIG_SYS_SDRAM0_INITPLR11 0x80000432
  271. #define CONFIG_SYS_SDRAM0_INITPLR12 0x808103c0
  272. #define CONFIG_SYS_SDRAM0_INITPLR13 0x80810040
  273. #define CONFIG_SYS_SDRAM0_INITPLR14 0x00000000
  274. #define CONFIG_SYS_SDRAM0_INITPLR15 0x00000000
  275. #define CONFIG_SYS_SDRAM0_RQDC 0x80000038
  276. #define CONFIG_SYS_SDRAM0_RFDC 0x00000257
  277. #define CONFIG_SYS_SDRAM0_RDCC 0x40000000
  278. #define CONFIG_SYS_SDRAM0_DLCR 0x03000091
  279. #define CONFIG_SYS_SDRAM0_CLKTR 0x40000000
  280. #define CONFIG_SYS_SDRAM0_WRDTR 0x82000823
  281. #define CONFIG_SYS_SDRAM0_SDTR1 0x80201000
  282. #define CONFIG_SYS_SDRAM0_SDTR2 0x42204243
  283. #define CONFIG_SYS_SDRAM0_SDTR3 0x090c0d1a
  284. #define CONFIG_SYS_SDRAM0_MMODE 0x00000432
  285. #define CONFIG_SYS_SDRAM0_MEMODE 0x00000004
  286. #endif /* !defined(CONFIG_ARCHES) */
  287. #endif /* !defined(CONFIG_NAND_U_BOOT) */
  288. #define CONFIG_SYS_MBYTES_SDRAM 512 /* 512MB */
  289. /*-----------------------------------------------------------------------
  290. * I2C
  291. *----------------------------------------------------------------------*/
  292. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed */
  293. #define CONFIG_SYS_I2C_MULTI_EEPROMS
  294. #define CONFIG_SYS_I2C_EEPROM_ADDR (0xa8>>1)
  295. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  296. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
  297. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
  298. /* I2C bootstrap EEPROM */
  299. #if defined(CONFIG_ARCHES)
  300. #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x54
  301. #else
  302. #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR 0x52
  303. #endif
  304. #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET 0
  305. #define CONFIG_4xx_CONFIG_BLOCKSIZE 16
  306. /* I2C SYSMON (LM75, AD7414 is almost compatible) */
  307. #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
  308. #define CONFIG_DTT_AD7414 1 /* use AD7414 */
  309. #define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
  310. #define CONFIG_SYS_DTT_MAX_TEMP 70
  311. #define CONFIG_SYS_DTT_LOW_TEMP -30
  312. #define CONFIG_SYS_DTT_HYSTERESIS 3
  313. #if defined(CONFIG_ARCHES)
  314. #define CONFIG_SYS_I2C_DTT_ADDR 0x4a /* AD7414 I2C address */
  315. #endif
  316. #if !defined(CONFIG_ARCHES)
  317. /* RTC configuration */
  318. #define CONFIG_RTC_M41T62 1
  319. #define CONFIG_SYS_I2C_RTC_ADDR 0x68
  320. #endif
  321. /*-----------------------------------------------------------------------
  322. * Ethernet
  323. *----------------------------------------------------------------------*/
  324. #define CONFIG_IBM_EMAC4_V4 1
  325. #define CONFIG_HAS_ETH0
  326. #define CONFIG_HAS_ETH1
  327. #if !defined(CONFIG_ARCHES)
  328. #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */
  329. #define CONFIG_PHY1_ADDR 1
  330. /* Only Glacier (460GT) has 4 EMAC interfaces */
  331. #ifdef CONFIG_460GT
  332. #define CONFIG_PHY2_ADDR 2
  333. #define CONFIG_PHY3_ADDR 3
  334. #define CONFIG_HAS_ETH2
  335. #define CONFIG_HAS_ETH3
  336. #endif
  337. #else /* defined(CONFIG_ARCHES) */
  338. #define CONFIG_FIXED_PHY 0xFFFFFFFF
  339. #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY
  340. #define CONFIG_PHY1_ADDR 0
  341. #define CONFIG_PHY2_ADDR 1
  342. #define CONFIG_HAS_ETH2
  343. #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \
  344. {devnum, speed, duplex}
  345. #define CONFIG_SYS_FIXED_PHY_PORTS \
  346. CONFIG_SYS_FIXED_PHY_PORT(0, 1000, FULL)
  347. #define CONFIG_M88E1112_PHY
  348. /*
  349. * For the GPCS_PHYx_ADDR PHY address, choose some PHY address not
  350. * used by CONFIG_PHYx_ADDR
  351. */
  352. #define CONFIG_GPCS_PHY_ADDR 0xA
  353. #define CONFIG_GPCS_PHY1_ADDR 0xB
  354. #define CONFIG_GPCS_PHY2_ADDR 0xC
  355. #endif /* !defined(CONFIG_ARCHES) */
  356. #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
  357. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  358. #define CONFIG_PHY_DYNAMIC_ANEG 1
  359. /*-----------------------------------------------------------------------
  360. * USB-OHCI
  361. *----------------------------------------------------------------------*/
  362. /* Only Canyonlands (460EX) has USB */
  363. #ifdef CONFIG_460EX
  364. #define CONFIG_USB_OHCI_NEW
  365. #define CONFIG_USB_STORAGE
  366. #undef CONFIG_SYS_OHCI_BE_CONTROLLER /* 460EX has little endian descriptors */
  367. #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS /* 460EX has little endian register */
  368. #define CONFIG_SYS_OHCI_USE_NPS /* force NoPowerSwitching mode */
  369. #define CONFIG_SYS_USB_OHCI_REGS_BASE (CONFIG_SYS_AHB_BASE | 0xd0000)
  370. #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ppc440"
  371. #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15
  372. #define CONFIG_SYS_USB_OHCI_BOARD_INIT
  373. #endif
  374. /*
  375. * Default environment variables
  376. */
  377. #if !defined(CONFIG_ARCHES)
  378. #define CONFIG_EXTRA_ENV_SETTINGS \
  379. CONFIG_AMCC_DEF_ENV \
  380. CONFIG_AMCC_DEF_ENV_POWERPC \
  381. CONFIG_AMCC_DEF_ENV_NOR_UPD \
  382. CONFIG_AMCC_DEF_ENV_NAND_UPD \
  383. "kernel_addr=fc000000\0" \
  384. "fdt_addr=fc1e0000\0" \
  385. "ramdisk_addr=fc200000\0" \
  386. "pciconfighost=1\0" \
  387. "pcie_mode=RP:RP\0" \
  388. ""
  389. #else /* defined(CONFIG_ARCHES) */
  390. #define CONFIG_EXTRA_ENV_SETTINGS \
  391. CONFIG_AMCC_DEF_ENV \
  392. CONFIG_AMCC_DEF_ENV_POWERPC \
  393. CONFIG_AMCC_DEF_ENV_NOR_UPD \
  394. "kernel_addr=fe000000\0" \
  395. "fdt_addr=fe1e0000\0" \
  396. "ramdisk_addr=fe200000\0" \
  397. "pciconfighost=1\0" \
  398. "pcie_mode=RP:RP\0" \
  399. "ethprime=ppc_4xx_eth1\0" \
  400. ""
  401. #endif /* !defined(CONFIG_ARCHES) */
  402. /*
  403. * Commands additional to the ones defined in amcc-common.h
  404. */
  405. #define CONFIG_CMD_CHIP_CONFIG
  406. #if defined(CONFIG_ARCHES)
  407. #define CONFIG_CMD_DTT
  408. #define CONFIG_CMD_PCI
  409. #define CONFIG_CMD_SDRAM
  410. #elif defined(CONFIG_CANYONLANDS)
  411. #define CONFIG_CMD_DATE
  412. #define CONFIG_CMD_DTT
  413. #define CONFIG_CMD_EXT2
  414. #define CONFIG_CMD_FAT
  415. #define CONFIG_CMD_NAND
  416. #define CONFIG_CMD_PCI
  417. #define CONFIG_CMD_SATA
  418. #define CONFIG_CMD_SDRAM
  419. #define CONFIG_CMD_SNTP
  420. #define CONFIG_CMD_USB
  421. #elif defined(CONFIG_GLACIER)
  422. #define CONFIG_CMD_DATE
  423. #define CONFIG_CMD_DTT
  424. #define CONFIG_CMD_NAND
  425. #define CONFIG_CMD_PCI
  426. #define CONFIG_CMD_SDRAM
  427. #define CONFIG_CMD_SNTP
  428. #else
  429. #error "board type not defined"
  430. #endif
  431. /* Partitions */
  432. #define CONFIG_MAC_PARTITION
  433. #define CONFIG_DOS_PARTITION
  434. #define CONFIG_ISO_PARTITION
  435. /*-----------------------------------------------------------------------
  436. * PCI stuff
  437. *----------------------------------------------------------------------*/
  438. /* General PCI */
  439. #define CONFIG_PCI /* include pci support */
  440. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  441. #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  442. #define CONFIG_PCI_CONFIG_HOST_BRIDGE
  443. /* Board-specific PCI */
  444. #define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
  445. #undef CONFIG_SYS_PCI_MASTER_INIT
  446. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
  447. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
  448. #ifdef CONFIG_460GT
  449. #if defined(CONFIG_ARCHES)
  450. /*-----------------------------------------------------------------------
  451. * RapidIO I/O and Registers
  452. *----------------------------------------------------------------------*/
  453. #define CONFIG_RAPIDIO
  454. #define CONFIG_SYS_460GT_SRIO_ERRATA_1
  455. #define SRGPL0_REG_BAR 0x0000000DAA000000ull /* 16MB */
  456. #define SRGPL0_CFG_BAR 0x0000000DAB000000ull /* 16MB */
  457. #define SRGPL0_MNT_BAR 0x0000000DAC000000ull /* 16MB */
  458. #define SRGPL0_MSG_BAR 0x0000000DAD000000ull /* 16MB */
  459. #define SRGPL0_OUT_BAR 0x0000000DB0000000ull /* 256MB */
  460. #define CONFIG_SYS_SRGPL0_REG_BAR 0xAA000000 /* 16MB */
  461. #define CONFIG_SYS_SRGPL0_CFG_BAR 0xAB000000 /* 16MB */
  462. #define CONFIG_SYS_SRGPL0_MNT_BAR 0xAC000000 /* 16MB */
  463. #define CONFIG_SYS_SRGPL0_MSG_BAR 0xAD000000 /* 16MB */
  464. #define CONFIG_SYS_I2ODMA_BASE 0xCF000000
  465. #define CONFIG_SYS_I2ODMA_PHYS_ADDR 0x0000000400100000ull
  466. #define CONFIG_PPC4XX_RAPIDIO_PROMISCUOUS_MODE
  467. #undef CONFIG_PPC4XX_RAPIDIO_DEBUG
  468. #undef CONFIG_PPC4XX_RAPIDIO_IN_BAR_USE_OCM
  469. #define CONFIG_PPC4XX_RAPIDIO_USE_HB_PLB
  470. #undef CONFIG_PPC4XX_RAPIDIO_LOOPBACK
  471. #endif /* CONFIG_ARCHES */
  472. #endif /* CONFIG_460GT */
  473. /*
  474. * SATA driver setup
  475. */
  476. #ifdef CONFIG_CMD_SATA
  477. #define CONFIG_SATA_DWC
  478. #define CONFIG_LIBATA
  479. #define SATA_BASE_ADDR 0xe20d1000 /* PPC460EX SATA Base Address */
  480. #define SATA_DMA_REG_ADDR 0xe20d0800 /* PPC460EX SATA Base Address */
  481. #define CONFIG_SYS_SATA_MAX_DEVICE 1 /* SATA MAX DEVICE */
  482. /* Convert sectorsize to wordsize */
  483. #define ATA_SECTOR_WORDS (ATA_SECT_SIZE/2)
  484. #endif
  485. /*-----------------------------------------------------------------------
  486. * External Bus Controller (EBC) Setup
  487. *----------------------------------------------------------------------*/
  488. /*
  489. * Canyonlands has 64MBytes of NOR FLASH (Spansion 29GL512), but the
  490. * boot EBC mapping only supports a maximum of 16MBytes
  491. * (4.ff00.0000 - 4.ffff.ffff).
  492. * To solve this problem, the FLASH has to get remapped to another
  493. * EBC address which accepts bigger regions:
  494. *
  495. * 0xfc00.0000 -> 4.cc00.0000
  496. *
  497. * Arches has 32MBytes of NOR FLASH (Spansion 29GL256), it will be
  498. * remapped to:
  499. *
  500. * 0xfe00.0000 -> 4.ce00.0000
  501. */
  502. #if defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  503. /* Memory Bank 3 (NOR-FLASH) initialization */
  504. #define CONFIG_SYS_EBC_PB3AP 0x10055e00
  505. #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
  506. /* Memory Bank 0 (NAND-FLASH) initialization */
  507. #define CONFIG_SYS_EBC_PB0AP 0x018003c0
  508. #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
  509. #else
  510. /* Memory Bank 0 (NOR-FLASH) initialization */
  511. #define CONFIG_SYS_EBC_PB0AP 0x10055e00
  512. #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_BOOT_BASE_ADDR | 0x9a000)
  513. #if !defined(CONFIG_ARCHES)
  514. /* Memory Bank 3 (NAND-FLASH) initialization */
  515. #define CONFIG_SYS_EBC_PB3AP 0x018003c0
  516. #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_NAND_ADDR | 0x1E000) /* BAS=NAND,BS=1MB,BU=R/W,BW=32bit*/
  517. #endif
  518. #endif /*defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
  519. #if !defined(CONFIG_ARCHES)
  520. /* Memory Bank 2 (CPLD) initialization */
  521. #define CONFIG_SYS_EBC_PB2AP 0x00804240
  522. #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_BCSR_BASE | 0x18000) /* BAS=CPLD,BS=1M,BU=RW,BW=32bit */
  523. #else /* defined(CONFIG_ARCHES) */
  524. /* Memory Bank 1 (FPGA) initialization */
  525. #define CONFIG_SYS_EBC_PB1AP 0x7f8ffe80
  526. #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_FPGA_BASE | 0x3a000) /* BAS=FPGA,BS=2MB,BU=R/W,BW=16bit*/
  527. #endif /* !defined(CONFIG_ARCHES) */
  528. #define CONFIG_SYS_EBC_CFG 0xbfc00000
  529. /*
  530. * Arches doesn't use PerCS3 but GPIO43, so let's configure the GPIO
  531. * pin multiplexing correctly
  532. */
  533. #if defined(CONFIG_ARCHES)
  534. #define GPIO43_USE GPIO_SEL /* On Arches this pin is used as GPIO */
  535. #else
  536. #define GPIO43_USE GPIO_ALT1 /* On Glacier this pin is used as ALT1 -> PerCS3 */
  537. #endif
  538. /*
  539. * PPC4xx GPIO Configuration
  540. */
  541. #ifdef CONFIG_460EX
  542. /* 460EX: Use USB configuration */
  543. #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
  544. { \
  545. /* GPIO Core 0 */ \
  546. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
  547. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
  548. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
  549. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
  550. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
  551. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
  552. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
  553. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
  554. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
  555. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
  556. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
  557. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
  558. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
  559. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
  560. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
  561. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
  562. {GPIO0_BASE, GPIO_IN , GPIO_SEL, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
  563. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
  564. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
  565. {GPIO0_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
  566. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
  567. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
  568. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
  569. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
  570. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
  571. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
  572. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
  573. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
  574. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
  575. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
  576. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
  577. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
  578. }, \
  579. { \
  580. /* GPIO Core 1 */ \
  581. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
  582. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
  583. {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
  584. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
  585. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
  586. {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
  587. {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
  588. {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
  589. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
  590. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
  591. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
  592. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
  593. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
  594. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
  595. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
  596. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
  597. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
  598. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
  599. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
  600. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
  601. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
  602. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
  603. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
  604. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
  605. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
  606. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
  607. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
  608. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
  609. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
  610. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
  611. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
  612. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
  613. } \
  614. }
  615. #else
  616. /* 460GT: Use EMAC2+3 configuration */
  617. #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
  618. { \
  619. /* GPIO Core 0 */ \
  620. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 GMC1TxD(0) USB2HostD(0) */ \
  621. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 GMC1TxD(1) USB2HostD(1) */ \
  622. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 GMC1TxD(2) USB2HostD(2) */ \
  623. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 GMC1TxD(3) USB2HostD(3) */ \
  624. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 GMC1TxD(4) USB2HostD(4) */ \
  625. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 GMC1TxD(5) USB2HostD(5) */ \
  626. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 GMC1TxD(6) USB2HostD(6) */ \
  627. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 GMC1TxD(7) USB2HostD(7) */ \
  628. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 GMC1RxD(0) USB2OTGD(0) */ \
  629. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 GMC1RxD(1) USB2OTGD(1) */ \
  630. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 GMC1RxD(2) USB2OTGD(2) */ \
  631. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 GMC1RxD(3) USB2OTGD(3) */ \
  632. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO12 GMC1RxD(4) USB2OTGD(4) */ \
  633. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO13 GMC1RxD(5) USB2OTGD(5) */ \
  634. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO14 GMC1RxD(6) USB2OTGD(6) */ \
  635. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO15 GMC1RxD(7) USB2OTGD(7) */ \
  636. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMC1TxER USB2HostStop */ \
  637. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMC1CD USB2HostNext */ \
  638. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMC1RxER USB2HostDir */ \
  639. {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMC1TxEN USB2OTGStop */ \
  640. {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 GMC1CRS USB2OTGNext */ \
  641. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 GMC1RxDV USB2OTGDir */ \
  642. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO22 NFRDY */ \
  643. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 NFREN */ \
  644. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 NFWEN */ \
  645. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 NFCLE */ \
  646. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 NFALE */ \
  647. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO27 IRQ(0) */ \
  648. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO28 IRQ(1) */ \
  649. {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO29 IRQ(2) */ \
  650. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO30 PerPar0 DMAReq2 IRQ(7)*/ \
  651. {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO31 PerPar1 DMAAck2 IRQ(8)*/ \
  652. }, \
  653. { \
  654. /* GPIO Core 1 */ \
  655. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 PerPar2 EOT2/TC2 IRQ(9)*/ \
  656. {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 PerPar3 DMAReq3 IRQ(4)*/ \
  657. {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_1}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
  658. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
  659. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N DMAAck3 UART3_SIN*/ \
  660. {GPIO1_BASE, GPIO_BI , GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EOT3/TC3 UART3_SOUT*/ \
  661. {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
  662. {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
  663. {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 IRQ(3) */ \
  664. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 CS(1) */ \
  665. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 CS(2) */ \
  666. {GPIO1_BASE, GPIO_OUT, GPIO43_USE, GPIO_OUT_0},/* GPIO43 CS(3) DMAReq1 IRQ(10)*/ \
  667. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO44 CS(4) DMAAck1 IRQ(11)*/ \
  668. {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO45 CS(5) EOT/TC1 IRQ(12)*/ \
  669. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 PerAddr(5) DMAReq0 IRQ(13)*/ \
  670. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 PerAddr(6) DMAAck0 IRQ(14)*/ \
  671. {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 PerAddr(7) EOT/TC0 IRQ(15)*/ \
  672. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49 Unselect via TraceSelect Bit */ \
  673. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
  674. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
  675. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
  676. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
  677. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
  678. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55 Unselect via TraceSelect Bit */ \
  679. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
  680. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57 Unselect via TraceSelect Bit */ \
  681. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
  682. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
  683. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
  684. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
  685. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
  686. {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
  687. } \
  688. }
  689. #endif
  690. #endif /* __CONFIG_H */