W7OLMC.h 12 KB

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  1. /*
  2. * (C) Copyright 2001
  3. * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405GP 1 /* This is a PPC405GP CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC405 family */
  34. #define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
  35. #define CONFIG_W7OLMC 1 /* ...specifically an LMC */
  36. #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
  37. #define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
  38. #define CONFIG_MISC_INIT_R 1 /* and misc_init_r() */
  39. #define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
  40. #define CONFIG_BAUDRATE 9600
  41. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  42. #if 1
  43. #define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
  44. #else
  45. #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
  46. #endif
  47. #undef CONFIG_BOOTARGS
  48. #define CONFIG_LOADADDR F0080000
  49. #define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
  50. #define CONFIG_OVERWRITE_ETHADDR_ONCE
  51. #define CONFIG_IPADDR 192.168.1.1
  52. #define CONFIG_NETMASK 255.255.255.0
  53. #define CONFIG_SERVERIP 192.168.1.2
  54. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  55. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* disallow baudrate change */
  56. #define CONFIG_PPC4xx_EMAC
  57. #define CONFIG_MII 1 /* MII PHY management */
  58. #define CONFIG_PHY_ADDR 0 /* PHY address */
  59. #define CONFIG_NET_MULTI
  60. #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
  61. /*
  62. * BOOTP options
  63. */
  64. #define CONFIG_BOOTP_BOOTFILESIZE
  65. #define CONFIG_BOOTP_BOOTPATH
  66. #define CONFIG_BOOTP_GATEWAY
  67. #define CONFIG_BOOTP_HOSTNAME
  68. /*
  69. * Command line configuration.
  70. */
  71. #include <config_cmd_default.h>
  72. #define CONFIG_CMD_PCI
  73. #define CONFIG_CMD_IRQ
  74. #define CONFIG_CMD_ASKENV
  75. #define CONFIG_CMD_DHCP
  76. #define CONFIG_CMD_BEDBUG
  77. #define CONFIG_CMD_DATE
  78. #define CONFIG_CMD_I2C
  79. #define CONFIG_CMD_EEPROM
  80. #define CONFIG_CMD_ELF
  81. #define CONFIG_CMD_BSP
  82. #define CONFIG_CMD_REGINFO
  83. #undef CONFIG_WATCHDOG /* watchdog disabled */
  84. #define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
  85. #define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
  86. #define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
  87. /*
  88. * Miscellaneous configurable options
  89. */
  90. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  91. #define CONFIG_SYS_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
  92. #undef CONFIG_SYS_HUSH_PARSER /* No hush parse for U-Boot */
  93. #ifdef CONFIG_SYS_HUSH_PARSER
  94. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  95. #endif
  96. #if defined(CONFIG_CMD_KGDB)
  97. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  98. #else
  99. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  100. #endif
  101. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  102. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  103. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  104. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  105. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  106. #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
  107. #define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
  108. #define CONFIG_SYS_BASE_BAUD 384000
  109. /* The following table includes the supported baudrates */
  110. #define CONFIG_SYS_BAUDRATE_TABLE {9600}
  111. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  112. #define CONFIG_SYS_EXTBDINFO 1 /* use extended board_info (bd_t) */
  113. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  114. /*-----------------------------------------------------------------------
  115. * PCI stuff
  116. *-----------------------------------------------------------------------
  117. */
  118. #define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
  119. #define PCI_HOST_FORCE 1 /* configure as pci host */
  120. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  121. #define CONFIG_PCI /* include pci support */
  122. #define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
  123. #define CONFIG_PCI_PNP /* pci plug-and-play */
  124. /* resource configuration */
  125. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
  126. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
  127. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  128. #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  129. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  130. #define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
  131. #define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
  132. #define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
  133. /*-----------------------------------------------------------------------
  134. * Set up values for external bus controller
  135. * used by cpu_init.c
  136. *-----------------------------------------------------------------------
  137. */
  138. /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
  139. #undef CONFIG_USE_PERWE
  140. /* use on chip memory ( OCM ) for temperary stack until sdram is tested */
  141. #define CONFIG_SYS_TEMP_STACK_OCM 1
  142. /* bank 0 is boot flash */
  143. /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
  144. #define CONFIG_SYS_W7O_EBC_PB0AP 0x03050440
  145. /* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
  146. #define CONFIG_SYS_W7O_EBC_PB0CR 0xFFE38000
  147. /* bank 1 is main flash */
  148. /* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
  149. #define CONFIG_SYS_EBC_PB1AP 0x05850240
  150. /* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
  151. #define CONFIG_SYS_EBC_PB1CR 0xF00FC000
  152. /* bank 2 is RTC/NVRAM */
  153. /* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
  154. #define CONFIG_SYS_EBC_PB2AP 0x03000440
  155. /* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
  156. #define CONFIG_SYS_EBC_PB2CR 0xFC018000
  157. /* bank 3 is FPGA 0 */
  158. /* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
  159. #define CONFIG_SYS_EBC_PB3AP 0x02000400
  160. /* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
  161. #define CONFIG_SYS_EBC_PB3CR 0xFD01A000
  162. /* bank 4 is FPGA 1 */
  163. /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
  164. #define CONFIG_SYS_EBC_PB4AP 0x02000400
  165. /* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
  166. #define CONFIG_SYS_EBC_PB4CR 0xFD11A000
  167. /* bank 5 is FPGA 2 */
  168. /* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
  169. #define CONFIG_SYS_EBC_PB5AP 0x02000400
  170. /* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
  171. #define CONFIG_SYS_EBC_PB5CR 0xFD21A000
  172. /* bank 6 is unused */
  173. /* PB6AP = 0 */
  174. #define CONFIG_SYS_EBC_PB6AP 0x00000000
  175. /* PB6CR = 0 */
  176. #define CONFIG_SYS_EBC_PB6CR 0x00000000
  177. /* bank 7 is LED register */
  178. /* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
  179. #define CONFIG_SYS_W7O_EBC_PB7AP 0x03050440
  180. /* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
  181. #define CONFIG_SYS_W7O_EBC_PB7CR 0xFE01C000
  182. /*-----------------------------------------------------------------------
  183. * Start addresses for the final memory configuration
  184. * (Set up by the startup code)
  185. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  186. */
  187. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  188. #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
  189. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  190. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  191. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  192. /*
  193. * For booting Linux, the board info and command line data
  194. * have to be in the first 8 MB of memory, since this is
  195. * the maximum mapped by the Linux kernel during initialization.
  196. */
  197. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  198. /*-----------------------------------------------------------------------
  199. * FLASH organization
  200. */
  201. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
  202. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
  203. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
  204. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
  205. #define CONFIG_SYS_FLASH_PROTECTION 1 /* Use real Flash protection */
  206. #if 1 /* Use NVRAM for environment variables */
  207. /*-----------------------------------------------------------------------
  208. * NVRAM organization
  209. */
  210. #define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
  211. #define CONFIG_SYS_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
  212. #define CONFIG_SYS_NVRAM_SIZE (32*1024) /* NVRAM size */
  213. #define CONFIG_ENV_SIZE 0x1000 /* Size of Environment vars */
  214. /*define CONFIG_ENV_ADDR \
  215. (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) Env */
  216. #define CONFIG_ENV_ADDR CONFIG_SYS_NVRAM_BASE_ADDR
  217. #else /* Use Boot Flash for environment variables */
  218. /*-----------------------------------------------------------------------
  219. * Flash EEPROM for environment
  220. */
  221. #define CONFIG_ENV_IS_IN_FLASH 1
  222. #define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
  223. #define CONFIG_ENV_SIZE 0x10000 /* Total Size of env. sector */
  224. #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
  225. #endif
  226. /*-----------------------------------------------------------------------
  227. * I2C EEPROM (CAT24WC08) for environment
  228. */
  229. #define CONFIG_HARD_I2C /* I2c with hardware support */
  230. #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
  231. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  232. #define CONFIG_SYS_I2C_SLAVE 0x7F
  233. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
  234. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
  235. /* mask of address bits that overflow into the "EEPROM chip address" */
  236. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  237. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
  238. /* 16 byte page write mode using*/
  239. /* last 4 bits of the address */
  240. #define CONFIG_SYS_I2C_MULTI_EEPROMS
  241. /*-----------------------------------------------------------------------
  242. * Definitions for Serial Presence Detect EEPROM address
  243. * (to get SDRAM settings)
  244. */
  245. #define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
  246. /*
  247. * Init Memory Controller:
  248. */
  249. #define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
  250. #define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
  251. /* On Chip Memory location */
  252. #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
  253. #define CONFIG_SYS_OCM_DATA_SIZE 0x1000
  254. /*-----------------------------------------------------------------------
  255. * Definitions for initial stack pointer and data area (in RAM)
  256. */
  257. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
  258. #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
  259. #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  260. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  261. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  262. /*
  263. * Internal Definitions
  264. *
  265. * Boot Flags
  266. */
  267. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  268. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  269. #if defined(CONFIG_CMD_KGDB)
  270. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  271. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  272. #endif
  273. /*
  274. * FPGA(s) configuration
  275. */
  276. #define CONFIG_SYS_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
  277. #define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */
  278. #define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
  279. #define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
  280. #define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
  281. #endif /* __CONFIG_H */