SPD823TS.h 15 KB

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  1. /*
  2. * (C) Copyright 2000
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_MPC823 1 /* This is a MPC823 CPU */
  33. #define CONFIG_SPD823TS 1 /* ...on a SPD823TS board */
  34. #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
  35. #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
  36. #undef CONFIG_8xx_CONS_SMC2
  37. #undef CONFIG_8xx_CONS_NONE
  38. #define CONFIG_BAUDRATE 115200
  39. #if 0
  40. #define CONFIG_BOOTDELAY -1 /* autoboot disabled */
  41. #else
  42. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  43. #endif
  44. #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
  45. #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
  46. #define CONFIG_BOOTARGS "root=/dev/nfs rw " \
  47. "nfsroot=10.0.0.2:/opt/eldk/ppc_8xx " \
  48. "nfsaddrs=10.0.0.99:10.0.0.2"
  49. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  50. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  51. #undef CONFIG_WATCHDOG /* watchdog disabled */
  52. /*
  53. * Command line configuration.
  54. */
  55. #include <config_cmd_default.h>
  56. #define CONFIG_CMD_IDE
  57. #undef CONFIG_CMD_SAVEENV
  58. #undef CONFIG_CMD_FLASH
  59. #define CONFIG_MAC_PARTITION
  60. #define CONFIG_DOS_PARTITION
  61. /*
  62. * BOOTP options
  63. */
  64. #define CONFIG_BOOTP_SUBNETMASK
  65. #define CONFIG_BOOTP_GATEWAY
  66. #define CONFIG_BOOTP_HOSTNAME
  67. #define CONFIG_BOOTP_BOOTPATH
  68. #define CONFIG_BOOTP_BOOTFILESIZE
  69. /*----------------------------------------------------------------------*/
  70. #define CONFIG_ETHADDR 00:D0:93:00:01:CB
  71. #define CONFIG_IPADDR 10.0.0.98
  72. #define CONFIG_SERVERIP 10.0.0.1
  73. #undef CONFIG_BOOTCOMMAND
  74. #define CONFIG_BOOTCOMMAND "tftp 200000 uImage;bootm 200000"
  75. /*----------------------------------------------------------------------*/
  76. /*
  77. * Miscellaneous configurable options
  78. */
  79. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  80. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  81. #if defined(CONFIG_CMD_KGDB)
  82. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  83. #else
  84. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  85. #endif
  86. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  87. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  88. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  89. #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
  90. #define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15MB in DRAM */
  91. #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
  92. #define CONFIG_SYS_PIO_MODE 0 /* IDE interface in PIO Mode 0 */
  93. #define CONFIG_SYS_PC_IDE_RESET ((ushort)0x0008) /* PC 12 */
  94. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  95. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  96. /*
  97. * Low Level Configuration Settings
  98. * (address mappings, register initial values, etc.)
  99. * You should know what you are doing if you make changes here.
  100. */
  101. /*-----------------------------------------------------------------------
  102. * Internal Memory Mapped Register
  103. */
  104. #define CONFIG_SYS_IMMR 0xFFF00000 /* was: 0xFF000000 */
  105. /*-----------------------------------------------------------------------
  106. * Definitions for initial stack pointer and data area (in DPRAM)
  107. */
  108. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  109. #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  110. #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  111. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  112. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  113. /*-----------------------------------------------------------------------
  114. * Start addresses for the final memory configuration
  115. * (Set up by the startup code)
  116. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  117. */
  118. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  119. #define CONFIG_SYS_FLASH_BASE 0xFF000000
  120. #ifdef DEBUG
  121. #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
  122. #else
  123. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  124. #endif
  125. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  126. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
  127. /*
  128. * For booting Linux, the board info and command line data
  129. * have to be in the first 8 MB of memory, since this is
  130. * the maximum mapped by the Linux kernel during initialization.
  131. */
  132. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  133. /*-----------------------------------------------------------------------
  134. * FLASH organization
  135. */
  136. #define CONFIG_SYS_MAX_FLASH_BANKS 0 /* max number of memory banks */
  137. #define CONFIG_SYS_MAX_FLASH_SECT 0 /* max number of sectors on one chip */
  138. #define CONFIG_SYS_FLASH_ERASE_TOUT 0 /* Timeout for Flash Erase (in ms) */
  139. #define CONFIG_SYS_FLASH_WRITE_TOUT 0 /* Timeout for Flash Write (in ms) */
  140. #define CONFIG_ENV_IS_IN_FLASH 1
  141. #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
  142. #define CONFIG_ENV_SIZE 0x0800 /* Total Size of Environment Sector */
  143. /*-----------------------------------------------------------------------
  144. * Cache Configuration
  145. */
  146. #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
  147. #if defined(CONFIG_CMD_KGDB)
  148. #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
  149. #endif
  150. /*-----------------------------------------------------------------------
  151. * SYPCR - System Protection Control 11-9
  152. * SYPCR can only be written once after reset!
  153. *-----------------------------------------------------------------------
  154. * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
  155. */
  156. #if defined(CONFIG_WATCHDOG)
  157. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
  158. SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
  159. #else
  160. #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
  161. #endif
  162. /*-----------------------------------------------------------------------
  163. * SIUMCR - SIU Module Configuration 11-6
  164. *-----------------------------------------------------------------------
  165. * PCMCIA config., multi-function pin tri-state
  166. */
  167. /* 0x00000040 */
  168. #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC00 | SIUMCR_GB5E)
  169. /*-----------------------------------------------------------------------
  170. * TBSCR - Time Base Status and Control 11-26
  171. *-----------------------------------------------------------------------
  172. * Clear Reference Interrupt Status, Timebase freezing enabled
  173. */
  174. #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
  175. /*-----------------------------------------------------------------------
  176. * PISCR - Periodic Interrupt Status and Control 11-31
  177. *-----------------------------------------------------------------------
  178. * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
  179. */
  180. #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
  181. /*-----------------------------------------------------------------------
  182. * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
  183. *-----------------------------------------------------------------------
  184. * Reset PLL lock status sticky bit, timer expired status bit and timer
  185. * interrupt status bit, set PLL multiplication factor !
  186. */
  187. /* 0x00b0c0c0 */
  188. #define CONFIG_SYS_PLPRCR \
  189. ( (11 << PLPRCR_MF_SHIFT) | \
  190. PLPRCR_SPLSS | PLPRCR_TEXPS | /*PLPRCR_TMIST|*/ \
  191. /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL | \
  192. PLPRCR_CSR | PLPRCR_LOLRE /*|PLPRCR_FIOPD*/ \
  193. )
  194. /*-----------------------------------------------------------------------
  195. * SCCR - System Clock and reset Control Register 15-27
  196. *-----------------------------------------------------------------------
  197. * Set clock output, timebase and RTC source and divider,
  198. * power management and some other internal clocks
  199. */
  200. #define SCCR_MASK SCCR_EBDF11
  201. /* 0x01800014 */
  202. #define CONFIG_SYS_SCCR (SCCR_COM00 | /*SCCR_TBS|*/ \
  203. SCCR_RTDIV | SCCR_RTSEL | \
  204. /*SCCR_CRQEN|*/ /*SCCR_PRQEN|*/ \
  205. SCCR_EBDF00 | SCCR_DFSYNC00 | \
  206. SCCR_DFBRG00 | SCCR_DFNL000 | \
  207. SCCR_DFNH000 | SCCR_DFLCD101 | \
  208. SCCR_DFALCD00)
  209. /*-----------------------------------------------------------------------
  210. * RTCSC - Real-Time Clock Status and Control Register
  211. *-----------------------------------------------------------------------
  212. */
  213. /* 0x00C3 */
  214. #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
  215. /*-----------------------------------------------------------------------
  216. * RCCR - RISC Controller Configuration Register
  217. *-----------------------------------------------------------------------
  218. */
  219. /* TIMEP=2 */
  220. #define CONFIG_SYS_RCCR 0x0200
  221. /*-----------------------------------------------------------------------
  222. * RMDS - RISC Microcode Development Support Control Register
  223. *-----------------------------------------------------------------------
  224. */
  225. #define CONFIG_SYS_RMDS 0
  226. /*-----------------------------------------------------------------------
  227. * SDSR - SDMA Status Register
  228. *-----------------------------------------------------------------------
  229. */
  230. #define CONFIG_SYS_SDSR ((u_char)0x83)
  231. /*-----------------------------------------------------------------------
  232. * SDMR - SDMA Mask Register
  233. *-----------------------------------------------------------------------
  234. */
  235. #define CONFIG_SYS_SDMR ((u_char)0x00)
  236. /*-----------------------------------------------------------------------
  237. *
  238. * Interrupt Levels
  239. *-----------------------------------------------------------------------
  240. */
  241. #define CONFIG_SYS_CPM_INTERRUPT 13 /* SIU_LEVEL6 */
  242. /*-----------------------------------------------------------------------
  243. * PCMCIA stuff
  244. *-----------------------------------------------------------------------
  245. *
  246. */
  247. #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
  248. #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
  249. #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
  250. #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
  251. #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
  252. #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
  253. #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
  254. #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
  255. /*-----------------------------------------------------------------------
  256. * IDE/ATA stuff
  257. *-----------------------------------------------------------------------
  258. */
  259. #define CONFIG_IDE_8xx_DIRECT 1 /* PCMCIA interface required */
  260. #define CONFIG_IDE_LED 1 /* LED for ide supported */
  261. #define CONFIG_IDE_RESET 1 /* reset for ide supported */
  262. #define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
  263. #define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
  264. #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100000
  265. #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
  266. #define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00
  267. #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O */
  268. #define CONFIG_SYS_ATA_REG_OFFSET 0x0080 /* Offset for normal register accesses */
  269. #define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 /* Offset for alternate registers */
  270. /*-----------------------------------------------------------------------
  271. *
  272. *-----------------------------------------------------------------------
  273. *
  274. */
  275. #define CONFIG_SYS_DER 0
  276. /*
  277. * Init Memory Controller:
  278. *
  279. * BR0/1 and OR0/1 (FLASH)
  280. */
  281. #define FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank #0 */
  282. #define FLASH_BASE1_PRELIM 0xFF080000 /* FLASH bank #1 */
  283. /* used to re-map FLASH both when starting from SRAM or FLASH:
  284. * restrict access enough to keep SRAM working (if any)
  285. * but not too much to meddle with FLASH accesses
  286. */
  287. /* EPROMs are 512kb */
  288. #define CONFIG_SYS_REMAP_OR_AM 0xFFF80000 /* OR addr mask */
  289. #define CONFIG_SYS_PRELIM_OR_AM 0xFFF80000 /* OR addr mask */
  290. /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
  291. #define CONFIG_SYS_OR_TIMING_FLASH (/* OR_CSNT_SAM | */ OR_ACS_DIV4 | OR_BI | \
  292. OR_SCY_5_CLK | OR_EHTR)
  293. #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  294. #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
  295. /* 16 bit, bank valid */
  296. #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
  297. #define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
  298. #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM
  299. /* 16 bit, bank valid */
  300. #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
  301. /*
  302. * BR2-5 and OR2-5 (SRAM/SDRAM/PER8/SHARC)
  303. *
  304. */
  305. #define SRAM_BASE 0xFE200000 /* SRAM bank */
  306. #define SRAM_OR_AM 0xFFE00000 /* SRAM is 2 MB */
  307. #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */
  308. #define SDRAM_PRELIM_OR_AM 0xF8000000 /* map max. 128 MB */
  309. #define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB SDRAM */
  310. #define PER8_BASE 0xFE000000 /* PER8 bank */
  311. #define PER8_OR_AM 0xFFF00000 /* PER8 is 1 MB */
  312. #define SHARC_BASE 0xFE400000 /* SHARC bank */
  313. #define SHARC_OR_AM 0xFFC00000 /* SHARC is 4 MB */
  314. /* SRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  315. #define CONFIG_SYS_OR_TIMING_SRAM 0x00000D42 /* SRAM-Timing */
  316. #define CONFIG_SYS_OR2 (SRAM_OR_AM | CONFIG_SYS_OR_TIMING_SRAM )
  317. #define CONFIG_SYS_BR2 ((SRAM_BASE & BR_BA_MSK) | BR_PS_16 | BR_V )
  318. /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
  319. #define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 /* SDRAM-Timing */
  320. #define CONFIG_SYS_OR3_PRELIM (SDRAM_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM )
  321. #define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V )
  322. #define CONFIG_SYS_OR_TIMING_PER8 0x00000F32 /* PER8-Timing */
  323. #define CONFIG_SYS_OR4 (PER8_OR_AM | CONFIG_SYS_OR_TIMING_PER8 )
  324. #define CONFIG_SYS_BR4 ((PER8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V )
  325. #define CONFIG_SYS_OR_TIMING_SHARC 0x00000700 /* SHARC-Timing */
  326. #define CONFIG_SYS_OR5 (SHARC_OR_AM | CONFIG_SYS_OR_TIMING_SHARC )
  327. #define CONFIG_SYS_BR5 ((SHARC_BASE & BR_BA_MSK) | BR_PS_32 | BR_MS_UPMA | BR_V )
  328. /*
  329. * Memory Periodic Timer Prescaler
  330. */
  331. /* periodic timer for refresh */
  332. #define CONFIG_SYS_MBMR_PTB 204
  333. /* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
  334. #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
  335. #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
  336. /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
  337. #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
  338. #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
  339. /*
  340. * MBMR settings for SDRAM
  341. */
  342. /* 8 column SDRAM */
  343. #define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
  344. MBMR_AMB_TYPE_0 | MBMR_DSB_1_CYCL | MBMR_G0CLB_A11 | \
  345. MBMR_RLFB_1X | MBMR_WLFB_1X | MBMR_TLFB_4X)
  346. /*
  347. * Internal Definitions
  348. *
  349. * Boot Flags
  350. */
  351. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  352. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  353. #endif /* __CONFIG_H */