MPC8560ADS.h 16 KB

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  1. /*
  2. * Copyright 2004 Freescale Semiconductor.
  3. * (C) Copyright 2002,2003 Motorola,Inc.
  4. * Xianghua Xiao <X.Xiao@motorola.com>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. /*
  25. * mpc8560ads board configuration file
  26. *
  27. * Please refer to doc/README.mpc85xx for more info.
  28. *
  29. * Make sure you change the MAC address and other network params first,
  30. * search for CONFIG_ETHADDR, CONFIG_SERVERIP, etc in this file.
  31. */
  32. #ifndef __CONFIG_H
  33. #define __CONFIG_H
  34. /* High Level Configuration Options */
  35. #define CONFIG_BOOKE 1 /* BOOKE */
  36. #define CONFIG_E500 1 /* BOOKE e500 family */
  37. #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
  38. #define CONFIG_CPM2 1 /* has CPM2 */
  39. #define CONFIG_MPC8560ADS 1 /* MPC8560ADS board specific */
  40. #define CONFIG_MPC8560 1
  41. #define CONFIG_PCI
  42. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  43. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  44. #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
  45. #define CONFIG_ENV_OVERWRITE
  46. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  47. #define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
  48. /*
  49. * sysclk for MPC85xx
  50. *
  51. * Two valid values are:
  52. * 33000000
  53. * 66000000
  54. *
  55. * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz
  56. * is likely the desired value here, so that is now the default.
  57. * The board, however, can run at 66MHz. In any event, this value
  58. * must match the settings of some switches. Details can be found
  59. * in the README.mpc85xxads.
  60. */
  61. #ifndef CONFIG_SYS_CLK_FREQ
  62. #define CONFIG_SYS_CLK_FREQ 33000000
  63. #endif
  64. /*
  65. * These can be toggled for performance analysis, otherwise use default.
  66. */
  67. #define CONFIG_L2_CACHE /* toggle L2 cache */
  68. #define CONFIG_BTB /* toggle branch predition */
  69. #define CONFIG_SYS_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */
  70. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
  71. #define CONFIG_SYS_MEMTEST_END 0x00400000
  72. /*
  73. * Base addresses -- Note these are effective addresses where the
  74. * actual resources get mapped (not physical addresses)
  75. */
  76. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  77. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  78. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  79. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  80. /* DDR Setup */
  81. #define CONFIG_FSL_DDR1
  82. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  83. #define CONFIG_DDR_SPD
  84. #undef CONFIG_FSL_DDR_INTERACTIVE
  85. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  86. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  87. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  88. #define CONFIG_NUM_DDR_CONTROLLERS 1
  89. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  90. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  91. /* I2C addresses of SPD EEPROMs */
  92. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  93. /* These are used when DDR doesn't use SPD. */
  94. #define CONFIG_SYS_SDRAM_SIZE 128 /* DDR is 128MB */
  95. #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 /* 0-128MB */
  96. #define CONFIG_SYS_DDR_CS0_CONFIG 0x80000002
  97. #define CONFIG_SYS_DDR_TIMING_1 0x37344321
  98. #define CONFIG_SYS_DDR_TIMING_2 0x00000800 /* P9-45,may need tuning */
  99. #define CONFIG_SYS_DDR_CONTROL 0xc2000000 /* unbuffered,no DYN_PWR */
  100. #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */
  101. #define CONFIG_SYS_DDR_INTERVAL 0x05200100 /* autocharge,no open page */
  102. /*
  103. * SDRAM on the Local Bus
  104. */
  105. #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
  106. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  107. #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
  108. #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
  109. #define CONFIG_SYS_OR0_PRELIM 0xff006ff7 /* 16MB Flash */
  110. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
  111. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* sectors per device */
  112. #undef CONFIG_SYS_FLASH_CHECKSUM
  113. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  114. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  115. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  116. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  117. #define CONFIG_SYS_RAMBOOT
  118. #else
  119. #undef CONFIG_SYS_RAMBOOT
  120. #endif
  121. #define CONFIG_FLASH_CFI_DRIVER
  122. #define CONFIG_SYS_FLASH_CFI
  123. #define CONFIG_SYS_FLASH_EMPTY_INFO
  124. #undef CONFIG_CLOCKS_IN_MHZ
  125. /*
  126. * Local Bus Definitions
  127. */
  128. /*
  129. * Base Register 2 and Option Register 2 configure SDRAM.
  130. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  131. *
  132. * For BR2, need:
  133. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  134. * port-size = 32-bits = BR2[19:20] = 11
  135. * no parity checking = BR2[21:22] = 00
  136. * SDRAM for MSEL = BR2[24:26] = 011
  137. * Valid = BR[31] = 1
  138. *
  139. * 0 4 8 12 16 20 24 28
  140. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  141. *
  142. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  143. * FIXME: the top 17 bits of BR2.
  144. */
  145. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  146. /*
  147. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  148. *
  149. * For OR2, need:
  150. * 64MB mask for AM, OR2[0:7] = 1111 1100
  151. * XAM, OR2[17:18] = 11
  152. * 9 columns OR2[19-21] = 010
  153. * 13 rows OR2[23-25] = 100
  154. * EAD set for extra time OR[31] = 1
  155. *
  156. * 0 4 8 12 16 20 24 28
  157. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  158. */
  159. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  160. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  161. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  162. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  163. #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal*/
  164. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_BSMA1516 \
  165. | LSDMR_RFCR5 \
  166. | LSDMR_PRETOACT3 \
  167. | LSDMR_ACTTORW3 \
  168. | LSDMR_BL8 \
  169. | LSDMR_WRC2 \
  170. | LSDMR_CL3 \
  171. | LSDMR_RFEN \
  172. )
  173. /*
  174. * SDRAM Controller configuration sequence.
  175. */
  176. #define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL)
  177. #define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  178. #define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH)
  179. #define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW)
  180. #define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL)
  181. /*
  182. * 32KB, 8-bit wide for ADS config reg
  183. */
  184. #define CONFIG_SYS_BR4_PRELIM 0xf8000801
  185. #define CONFIG_SYS_OR4_PRELIM 0xffffe1f1
  186. #define CONFIG_SYS_BCSR (CONFIG_SYS_BR4_PRELIM & 0xffff8000)
  187. #define CONFIG_SYS_INIT_RAM_LOCK 1
  188. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  189. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
  190. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  191. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  192. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  193. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  194. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  195. /* Serial Port */
  196. #define CONFIG_CONS_ON_SCC /* define if console on SCC */
  197. #undef CONFIG_CONS_NONE /* define if console on something else */
  198. #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
  199. #define CONFIG_BAUDRATE 115200
  200. #define CONFIG_SYS_BAUDRATE_TABLE \
  201. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  202. /* Use the HUSH parser */
  203. #define CONFIG_SYS_HUSH_PARSER
  204. #ifdef CONFIG_SYS_HUSH_PARSER
  205. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  206. #endif
  207. /* pass open firmware flat tree */
  208. #define CONFIG_OF_LIBFDT 1
  209. #define CONFIG_OF_BOARD_SETUP 1
  210. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  211. /*
  212. * I2C
  213. */
  214. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  215. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  216. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  217. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  218. #define CONFIG_SYS_I2C_SLAVE 0x7F
  219. #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  220. #define CONFIG_SYS_I2C_OFFSET 0x3000
  221. /* RapidIO MMU */
  222. #define CONFIG_SYS_RIO_MEM_VIRT 0xc0000000 /* base address */
  223. #define CONFIG_SYS_RIO_MEM_BUS 0xc0000000 /* base address */
  224. #define CONFIG_SYS_RIO_MEM_PHYS 0xc0000000
  225. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 128M */
  226. /*
  227. * General PCI
  228. * Memory space is mapped 1-1, but I/O space must start from 0.
  229. */
  230. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  231. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  232. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  233. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  234. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  235. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  236. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  237. #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */
  238. #if defined(CONFIG_PCI)
  239. #define CONFIG_NET_MULTI
  240. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  241. #undef CONFIG_EEPRO100
  242. #undef CONFIG_TULIP
  243. #if !defined(CONFIG_PCI_PNP)
  244. #define PCI_ENET0_IOADDR 0xe0000000
  245. #define PCI_ENET0_MEMADDR 0xe0000000
  246. #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
  247. #endif
  248. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  249. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
  250. #endif /* CONFIG_PCI */
  251. #ifdef CONFIG_TSEC_ENET
  252. #ifndef CONFIG_NET_MULTI
  253. #define CONFIG_NET_MULTI 1
  254. #endif
  255. #ifndef CONFIG_MII
  256. #define CONFIG_MII 1 /* MII PHY management */
  257. #endif
  258. #define CONFIG_TSEC1 1
  259. #define CONFIG_TSEC1_NAME "TSEC0"
  260. #define CONFIG_TSEC2 1
  261. #define CONFIG_TSEC2_NAME "TSEC1"
  262. #define TSEC1_PHY_ADDR 0
  263. #define TSEC2_PHY_ADDR 1
  264. #define TSEC1_PHYIDX 0
  265. #define TSEC2_PHYIDX 0
  266. #define TSEC1_FLAGS TSEC_GIGABIT
  267. #define TSEC2_FLAGS TSEC_GIGABIT
  268. /* Options are: TSEC[0-1] */
  269. #define CONFIG_ETHPRIME "TSEC0"
  270. #endif /* CONFIG_TSEC_ENET */
  271. #ifdef CONFIG_ETHER_ON_FCC /* CPM FCC Ethernet */
  272. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  273. #define CONFIG_ETHER_INDEX 2 /* which channel for ether */
  274. #if (CONFIG_ETHER_INDEX == 2)
  275. /*
  276. * - Rx-CLK is CLK13
  277. * - Tx-CLK is CLK14
  278. * - Select bus for bd/buffers
  279. * - Full duplex
  280. */
  281. #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  282. #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  283. #define CONFIG_SYS_CPMFCR_RAMTYPE 0
  284. #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
  285. #define FETH2_RST 0x01
  286. #elif (CONFIG_ETHER_INDEX == 3)
  287. /* need more definitions here for FE3 */
  288. #define FETH3_RST 0x80
  289. #endif /* CONFIG_ETHER_INDEX */
  290. #ifndef CONFIG_MII
  291. #define CONFIG_MII 1 /* MII PHY management */
  292. #endif
  293. #define CONFIG_BITBANGMII /* bit-bang MII PHY management */
  294. /*
  295. * GPIO pins used for bit-banged MII communications
  296. */
  297. #define MDIO_PORT 2 /* Port C */
  298. #define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
  299. (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
  300. #define MDC_DECLARE MDIO_DECLARE
  301. #define MDIO_ACTIVE (iop->pdir |= 0x00400000)
  302. #define MDIO_TRISTATE (iop->pdir &= ~0x00400000)
  303. #define MDIO_READ ((iop->pdat & 0x00400000) != 0)
  304. #define MDIO(bit) if(bit) iop->pdat |= 0x00400000; \
  305. else iop->pdat &= ~0x00400000
  306. #define MDC(bit) if(bit) iop->pdat |= 0x00200000; \
  307. else iop->pdat &= ~0x00200000
  308. #define MIIDELAY udelay(1)
  309. #endif
  310. /*
  311. * Environment
  312. */
  313. #ifndef CONFIG_SYS_RAMBOOT
  314. #define CONFIG_ENV_IS_IN_FLASH 1
  315. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  316. #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  317. #define CONFIG_ENV_SIZE 0x2000
  318. #else
  319. #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
  320. #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
  321. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
  322. #define CONFIG_ENV_SIZE 0x2000
  323. #endif
  324. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  325. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  326. /*
  327. * BOOTP options
  328. */
  329. #define CONFIG_BOOTP_BOOTFILESIZE
  330. #define CONFIG_BOOTP_BOOTPATH
  331. #define CONFIG_BOOTP_GATEWAY
  332. #define CONFIG_BOOTP_HOSTNAME
  333. /*
  334. * Command line configuration.
  335. */
  336. #include <config_cmd_default.h>
  337. #define CONFIG_CMD_PING
  338. #define CONFIG_CMD_I2C
  339. #define CONFIG_CMD_ELF
  340. #define CONFIG_CMD_IRQ
  341. #define CONFIG_CMD_SETEXPR
  342. #define CONFIG_CMD_REGINFO
  343. #if defined(CONFIG_PCI)
  344. #define CONFIG_CMD_PCI
  345. #endif
  346. #if defined(CONFIG_ETHER_ON_FCC)
  347. #define CONFIG_CMD_MII
  348. #endif
  349. #if defined(CONFIG_SYS_RAMBOOT)
  350. #undef CONFIG_CMD_SAVEENV
  351. #undef CONFIG_CMD_LOADS
  352. #endif
  353. #undef CONFIG_WATCHDOG /* watchdog disabled */
  354. /*
  355. * Miscellaneous configurable options
  356. */
  357. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  358. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  359. #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
  360. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  361. #if defined(CONFIG_CMD_KGDB)
  362. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  363. #else
  364. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  365. #endif
  366. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  367. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  368. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  369. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  370. /*
  371. * For booting Linux, the board info and command line data
  372. * have to be in the first 16 MB of memory, since this is
  373. * the maximum mapped by the Linux kernel during initialization.
  374. */
  375. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  376. /*
  377. * Internal Definitions
  378. *
  379. * Boot Flags
  380. */
  381. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  382. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  383. #if defined(CONFIG_CMD_KGDB)
  384. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  385. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  386. #endif
  387. /*
  388. * Environment Configuration
  389. */
  390. /* The mac addresses for all ethernet interface */
  391. #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
  392. #define CONFIG_HAS_ETH0
  393. #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  394. #define CONFIG_HAS_ETH1
  395. #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  396. #define CONFIG_HAS_ETH2
  397. #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
  398. #define CONFIG_HAS_ETH3
  399. #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
  400. #endif
  401. #define CONFIG_IPADDR 192.168.1.253
  402. #define CONFIG_HOSTNAME unknown
  403. #define CONFIG_ROOTPATH /nfsroot
  404. #define CONFIG_BOOTFILE your.uImage
  405. #define CONFIG_SERVERIP 192.168.1.1
  406. #define CONFIG_GATEWAYIP 192.168.1.1
  407. #define CONFIG_NETMASK 255.255.255.0
  408. #define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */
  409. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  410. #undef CONFIG_BOOTARGS /* the boot command will set bootargs */
  411. #define CONFIG_BAUDRATE 115200
  412. #define CONFIG_EXTRA_ENV_SETTINGS \
  413. "netdev=eth0\0" \
  414. "consoledev=ttyCPM\0" \
  415. "ramdiskaddr=1000000\0" \
  416. "ramdiskfile=your.ramdisk.u-boot\0" \
  417. "fdtaddr=400000\0" \
  418. "fdtfile=mpc8560ads.dtb\0"
  419. #define CONFIG_NFSBOOTCOMMAND \
  420. "setenv bootargs root=/dev/nfs rw " \
  421. "nfsroot=$serverip:$rootpath " \
  422. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  423. "console=$consoledev,$baudrate $othbootargs;" \
  424. "tftp $loadaddr $bootfile;" \
  425. "tftp $fdtaddr $fdtfile;" \
  426. "bootm $loadaddr - $fdtaddr"
  427. #define CONFIG_RAMBOOTCOMMAND \
  428. "setenv bootargs root=/dev/ram rw " \
  429. "console=$consoledev,$baudrate $othbootargs;" \
  430. "tftp $ramdiskaddr $ramdiskfile;" \
  431. "tftp $loadaddr $bootfile;" \
  432. "tftp $fdtaddr $fdtfile;" \
  433. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  434. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  435. #endif /* __CONFIG_H */