MPC8548CDS.h 17 KB

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  1. /*
  2. * Copyright 2004, 2007 Freescale Semiconductor.
  3. *
  4. * See file CREDITS for list of people who contributed to this
  5. * project.
  6. *
  7. * This program is free software; you can redistribute it and/or
  8. * modify it under the terms of the GNU General Public License as
  9. * published by the Free Software Foundation; either version 2 of
  10. * the License, or (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20. * MA 02111-1307 USA
  21. */
  22. /*
  23. * mpc8548cds board configuration file
  24. *
  25. * Please refer to doc/README.mpc85xxcds for more info.
  26. *
  27. */
  28. #ifndef __CONFIG_H
  29. #define __CONFIG_H
  30. /* High Level Configuration Options */
  31. #define CONFIG_BOOKE 1 /* BOOKE */
  32. #define CONFIG_E500 1 /* BOOKE e500 family */
  33. #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41/48 */
  34. #define CONFIG_MPC8548 1 /* MPC8548 specific */
  35. #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */
  36. #define CONFIG_PCI /* enable any pci type devices */
  37. #define CONFIG_PCI1 /* PCI controller 1 */
  38. #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
  39. #undef CONFIG_RIO
  40. #undef CONFIG_PCI2
  41. #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */
  42. #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */
  43. #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
  44. #define CONFIG_TSEC_ENET /* tsec ethernet support */
  45. #define CONFIG_ENV_OVERWRITE
  46. #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */
  47. #define CONFIG_FSL_LAW 1 /* Use common FSL init code */
  48. #define CONFIG_FSL_VIA
  49. #ifndef __ASSEMBLY__
  50. extern unsigned long get_clock_freq(void);
  51. #endif
  52. #define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
  53. /*
  54. * These can be toggled for performance analysis, otherwise use default.
  55. */
  56. #define CONFIG_L2_CACHE /* toggle L2 cache */
  57. #define CONFIG_BTB /* toggle branch predition */
  58. /*
  59. * Only possible on E500 Version 2 or newer cores.
  60. */
  61. #define CONFIG_ENABLE_36BIT_PHYS 1
  62. #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
  63. #define CONFIG_SYS_MEMTEST_END 0x00400000
  64. /*
  65. * Base addresses -- Note these are effective addresses where the
  66. * actual resources get mapped (not physical addresses)
  67. */
  68. #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
  69. #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
  70. #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
  71. #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
  72. /* DDR Setup */
  73. #define CONFIG_FSL_DDR2
  74. #undef CONFIG_FSL_DDR_INTERACTIVE
  75. #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
  76. #define CONFIG_DDR_SPD
  77. #define CONFIG_DDR_DLL /* possible DLL fix needed */
  78. #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
  79. #define CONFIG_MEM_INIT_VALUE 0xDeadBeef
  80. #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
  81. #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
  82. #define CONFIG_NUM_DDR_CONTROLLERS 1
  83. #define CONFIG_DIMM_SLOTS_PER_CTLR 1
  84. #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
  85. /* I2C addresses of SPD EEPROMs */
  86. #define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
  87. /* Make sure required options are set */
  88. #ifndef CONFIG_SPD_EEPROM
  89. #error ("CONFIG_SPD_EEPROM is required")
  90. #endif
  91. #undef CONFIG_CLOCKS_IN_MHZ
  92. /*
  93. * Local Bus Definitions
  94. */
  95. /*
  96. * FLASH on the Local Bus
  97. * Two banks, 8M each, using the CFI driver.
  98. * Boot from BR0/OR0 bank at 0xff00_0000
  99. * Alternate BR1/OR1 bank at 0xff80_0000
  100. *
  101. * BR0, BR1:
  102. * Base address 0 = 0xff00_0000 = BR0[0:16] = 1111 1111 0000 0000 0
  103. * Base address 1 = 0xff80_0000 = BR1[0:16] = 1111 1111 1000 0000 0
  104. * Port Size = 16 bits = BRx[19:20] = 10
  105. * Use GPCM = BRx[24:26] = 000
  106. * Valid = BRx[31] = 1
  107. *
  108. * 0 4 8 12 16 20 24 28
  109. * 1111 1111 1000 0000 0001 0000 0000 0001 = ff801001 BR0
  110. * 1111 1111 0000 0000 0001 0000 0000 0001 = ff001001 BR1
  111. *
  112. * OR0, OR1:
  113. * Addr Mask = 8M = ORx[0:16] = 1111 1111 1000 0000 0
  114. * Reserved ORx[17:18] = 11, confusion here?
  115. * CSNT = ORx[20] = 1
  116. * ACS = half cycle delay = ORx[21:22] = 11
  117. * SCY = 6 = ORx[24:27] = 0110
  118. * TRLX = use relaxed timing = ORx[29] = 1
  119. * EAD = use external address latch delay = OR[31] = 1
  120. *
  121. * 0 4 8 12 16 20 24 28
  122. * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65 ORx
  123. */
  124. #define CONFIG_SYS_BOOT_BLOCK 0xff000000 /* boot TLB block */
  125. #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
  126. #define CONFIG_SYS_BR0_PRELIM 0xff801001
  127. #define CONFIG_SYS_BR1_PRELIM 0xff001001
  128. #define CONFIG_SYS_OR0_PRELIM 0xff806e65
  129. #define CONFIG_SYS_OR1_PRELIM 0xff806e65
  130. #define CONFIG_SYS_FLASH_BANKS_LIST {0xff800000, CONFIG_SYS_FLASH_BASE}
  131. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
  132. #define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
  133. #undef CONFIG_SYS_FLASH_CHECKSUM
  134. #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
  135. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
  136. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
  137. #define CONFIG_FLASH_CFI_DRIVER
  138. #define CONFIG_SYS_FLASH_CFI
  139. #define CONFIG_SYS_FLASH_EMPTY_INFO
  140. /*
  141. * SDRAM on the Local Bus
  142. */
  143. #define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */
  144. #define CONFIG_SYS_LBC_CACHE_SIZE 64
  145. #define CONFIG_SYS_LBC_NONCACHE_BASE 0xf8000000 /* Localbus non-cacheable */
  146. #define CONFIG_SYS_LBC_NONCACHE_SIZE 64
  147. #define CONFIG_SYS_LBC_SDRAM_BASE CONFIG_SYS_LBC_CACHE_BASE /* Localbus SDRAM */
  148. #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
  149. /*
  150. * Base Register 2 and Option Register 2 configure SDRAM.
  151. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  152. *
  153. * For BR2, need:
  154. * Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
  155. * port-size = 32-bits = BR2[19:20] = 11
  156. * no parity checking = BR2[21:22] = 00
  157. * SDRAM for MSEL = BR2[24:26] = 011
  158. * Valid = BR[31] = 1
  159. *
  160. * 0 4 8 12 16 20 24 28
  161. * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  162. *
  163. * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  164. * FIXME: the top 17 bits of BR2.
  165. */
  166. #define CONFIG_SYS_BR2_PRELIM 0xf0001861
  167. /*
  168. * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
  169. *
  170. * For OR2, need:
  171. * 64MB mask for AM, OR2[0:7] = 1111 1100
  172. * XAM, OR2[17:18] = 11
  173. * 9 columns OR2[19-21] = 010
  174. * 13 rows OR2[23-25] = 100
  175. * EAD set for extra time OR[31] = 1
  176. *
  177. * 0 4 8 12 16 20 24 28
  178. * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  179. */
  180. #define CONFIG_SYS_OR2_PRELIM 0xfc006901
  181. #define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
  182. #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
  183. #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
  184. #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/
  185. /*
  186. * Common settings for all Local Bus SDRAM commands.
  187. * At run time, either BSMA1516 (for CPU 1.1)
  188. * or BSMA1617 (for CPU 1.0) (old)
  189. * is OR'ed in too.
  190. */
  191. #define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \
  192. | LSDMR_PRETOACT7 \
  193. | LSDMR_ACTTORW7 \
  194. | LSDMR_BL8 \
  195. | LSDMR_WRC4 \
  196. | LSDMR_CL3 \
  197. | LSDMR_RFEN \
  198. )
  199. /*
  200. * The CADMUS registers are connected to CS3 on CDS.
  201. * The new memory map places CADMUS at 0xf8000000.
  202. *
  203. * For BR3, need:
  204. * Base address of 0xf8000000 = BR[0:16] = 1111 1000 0000 0000 0
  205. * port-size = 8-bits = BR[19:20] = 01
  206. * no parity checking = BR[21:22] = 00
  207. * GPMC for MSEL = BR[24:26] = 000
  208. * Valid = BR[31] = 1
  209. *
  210. * 0 4 8 12 16 20 24 28
  211. * 1111 1000 0000 0000 0000 1000 0000 0001 = f8000801
  212. *
  213. * For OR3, need:
  214. * 1 MB mask for AM, OR[0:16] = 1111 1111 1111 0000 0
  215. * disable buffer ctrl OR[19] = 0
  216. * CSNT OR[20] = 1
  217. * ACS OR[21:22] = 11
  218. * XACS OR[23] = 1
  219. * SCY 15 wait states OR[24:27] = 1111 max is suboptimal but safe
  220. * SETA OR[28] = 0
  221. * TRLX OR[29] = 1
  222. * EHTR OR[30] = 1
  223. * EAD extra time OR[31] = 1
  224. *
  225. * 0 4 8 12 16 20 24 28
  226. * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  227. */
  228. #define CONFIG_FSL_CADMUS
  229. #define CADMUS_BASE_ADDR 0xf8000000
  230. #define CONFIG_SYS_BR3_PRELIM 0xf8000801
  231. #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
  232. #define CONFIG_SYS_INIT_RAM_LOCK 1
  233. #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
  234. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
  235. #define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 /* relocate boot L2SRAM */
  236. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
  237. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  238. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  239. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
  240. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
  241. /* Serial Port */
  242. #define CONFIG_CONS_INDEX 2
  243. #undef CONFIG_SERIAL_SOFTWARE_FIFO
  244. #define CONFIG_SYS_NS16550
  245. #define CONFIG_SYS_NS16550_SERIAL
  246. #define CONFIG_SYS_NS16550_REG_SIZE 1
  247. #define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
  248. #define CONFIG_SYS_BAUDRATE_TABLE \
  249. {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
  250. #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
  251. #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
  252. /* Use the HUSH parser */
  253. #define CONFIG_SYS_HUSH_PARSER
  254. #ifdef CONFIG_SYS_HUSH_PARSER
  255. #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
  256. #endif
  257. /* pass open firmware flat tree */
  258. #define CONFIG_OF_LIBFDT 1
  259. #define CONFIG_OF_BOARD_SETUP 1
  260. #define CONFIG_OF_STDOUT_VIA_ALIAS 1
  261. /*
  262. * I2C
  263. */
  264. #define CONFIG_FSL_I2C /* Use FSL common I2C driver */
  265. #define CONFIG_HARD_I2C /* I2C with hardware support*/
  266. #undef CONFIG_SOFT_I2C /* I2C bit-banged */
  267. #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
  268. #define CONFIG_SYS_I2C_SLAVE 0x7F
  269. #define CONFIG_SYS_I2C_NOPROBES {0x69} /* Don't probe these addrs */
  270. #define CONFIG_SYS_I2C_OFFSET 0x3000
  271. /* EEPROM */
  272. #define CONFIG_ID_EEPROM
  273. #define CONFIG_SYS_I2C_EEPROM_CCID
  274. #define CONFIG_SYS_ID_EEPROM
  275. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
  276. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
  277. /*
  278. * General PCI
  279. * Memory space is mapped 1-1, but I/O space must start from 0.
  280. */
  281. #define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */
  282. #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
  283. #define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000
  284. #define CONFIG_SYS_PCI1_MEM_BUS 0x80000000
  285. #define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000
  286. #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
  287. #define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000
  288. #define CONFIG_SYS_PCI1_IO_BUS 0x00000000
  289. #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
  290. #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
  291. #ifdef CONFIG_PCI2
  292. #define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000
  293. #define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000
  294. #define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000
  295. #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
  296. #define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000
  297. #define CONFIG_SYS_PCI2_IO_BUS 0x00000000
  298. #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000
  299. #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */
  300. #endif
  301. #ifdef CONFIG_PCIE1
  302. #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000
  303. #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000
  304. #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000
  305. #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
  306. #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000
  307. #define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
  308. #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000
  309. #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */
  310. #endif
  311. #ifdef CONFIG_RIO
  312. /*
  313. * RapidIO MMU
  314. */
  315. #define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000
  316. #define CONFIG_SYS_RIO_MEM_BUS 0xC0000000
  317. #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */
  318. #endif
  319. #ifdef CONFIG_LEGACY
  320. #define BRIDGE_ID 17
  321. #define VIA_ID 2
  322. #else
  323. #define BRIDGE_ID 28
  324. #define VIA_ID 4
  325. #endif
  326. #if defined(CONFIG_PCI)
  327. #define CONFIG_NET_MULTI
  328. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  329. #undef CONFIG_EEPRO100
  330. #undef CONFIG_TULIP
  331. #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
  332. #endif /* CONFIG_PCI */
  333. #if defined(CONFIG_TSEC_ENET)
  334. #ifndef CONFIG_NET_MULTI
  335. #define CONFIG_NET_MULTI 1
  336. #endif
  337. #define CONFIG_MII 1 /* MII PHY management */
  338. #define CONFIG_TSEC1 1
  339. #define CONFIG_TSEC1_NAME "eTSEC0"
  340. #define CONFIG_TSEC2 1
  341. #define CONFIG_TSEC2_NAME "eTSEC1"
  342. #define CONFIG_TSEC3 1
  343. #define CONFIG_TSEC3_NAME "eTSEC2"
  344. #define CONFIG_TSEC4
  345. #define CONFIG_TSEC4_NAME "eTSEC3"
  346. #undef CONFIG_MPC85XX_FEC
  347. #define TSEC1_PHY_ADDR 0
  348. #define TSEC2_PHY_ADDR 1
  349. #define TSEC3_PHY_ADDR 2
  350. #define TSEC4_PHY_ADDR 3
  351. #define TSEC1_PHYIDX 0
  352. #define TSEC2_PHYIDX 0
  353. #define TSEC3_PHYIDX 0
  354. #define TSEC4_PHYIDX 0
  355. #define TSEC1_FLAGS TSEC_GIGABIT
  356. #define TSEC2_FLAGS TSEC_GIGABIT
  357. #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  358. #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
  359. /* Options are: eTSEC[0-3] */
  360. #define CONFIG_ETHPRIME "eTSEC0"
  361. #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
  362. #endif /* CONFIG_TSEC_ENET */
  363. /*
  364. * Environment
  365. */
  366. #define CONFIG_ENV_IS_IN_FLASH 1
  367. #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x40000)
  368. #define CONFIG_ENV_SECT_SIZE 0x40000 /* 256K(one sector) for env */
  369. #define CONFIG_ENV_SIZE 0x2000
  370. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  371. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  372. /*
  373. * BOOTP options
  374. */
  375. #define CONFIG_BOOTP_BOOTFILESIZE
  376. #define CONFIG_BOOTP_BOOTPATH
  377. #define CONFIG_BOOTP_GATEWAY
  378. #define CONFIG_BOOTP_HOSTNAME
  379. /*
  380. * Command line configuration.
  381. */
  382. #include <config_cmd_default.h>
  383. #define CONFIG_CMD_PING
  384. #define CONFIG_CMD_I2C
  385. #define CONFIG_CMD_MII
  386. #define CONFIG_CMD_ELF
  387. #define CONFIG_CMD_IRQ
  388. #define CONFIG_CMD_SETEXPR
  389. #define CONFIG_CMD_REGINFO
  390. #if defined(CONFIG_PCI)
  391. #define CONFIG_CMD_PCI
  392. #endif
  393. #undef CONFIG_WATCHDOG /* watchdog disabled */
  394. /*
  395. * Miscellaneous configurable options
  396. */
  397. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  398. #define CONFIG_CMDLINE_EDITING /* Command-line editing */
  399. #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
  400. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  401. #if defined(CONFIG_CMD_KGDB)
  402. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  403. #else
  404. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  405. #endif
  406. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  407. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  408. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  409. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
  410. /*
  411. * For booting Linux, the board info and command line data
  412. * have to be in the first 16 MB of memory, since this is
  413. * the maximum mapped by the Linux kernel during initialization.
  414. */
  415. #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/
  416. /*
  417. * Internal Definitions
  418. *
  419. * Boot Flags
  420. */
  421. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  422. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  423. #if defined(CONFIG_CMD_KGDB)
  424. #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
  425. #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
  426. #endif
  427. /*
  428. * Environment Configuration
  429. */
  430. /* The mac addresses for all ethernet interface */
  431. #if defined(CONFIG_TSEC_ENET)
  432. #define CONFIG_HAS_ETH0
  433. #define CONFIG_ETHADDR 00:E0:0C:00:00:FD
  434. #define CONFIG_HAS_ETH1
  435. #define CONFIG_ETH1ADDR 00:E0:0C:00:01:FD
  436. #define CONFIG_HAS_ETH2
  437. #define CONFIG_ETH2ADDR 00:E0:0C:00:02:FD
  438. #define CONFIG_HAS_ETH3
  439. #define CONFIG_ETH3ADDR 00:E0:0C:00:03:FD
  440. #endif
  441. #define CONFIG_IPADDR 192.168.1.253
  442. #define CONFIG_HOSTNAME unknown
  443. #define CONFIG_ROOTPATH /nfsroot
  444. #define CONFIG_BOOTFILE 8548cds/uImage.uboot
  445. #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */
  446. #define CONFIG_SERVERIP 192.168.1.1
  447. #define CONFIG_GATEWAYIP 192.168.1.1
  448. #define CONFIG_NETMASK 255.255.255.0
  449. #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/
  450. #define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
  451. #undef CONFIG_BOOTARGS /* the boot command will set bootargs*/
  452. #define CONFIG_BAUDRATE 115200
  453. #define CONFIG_EXTRA_ENV_SETTINGS \
  454. "netdev=eth0\0" \
  455. "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
  456. "tftpflash=tftpboot $loadaddr $uboot; " \
  457. "protect off " MK_STR(TEXT_BASE) " +$filesize; " \
  458. "erase " MK_STR(TEXT_BASE) " +$filesize; " \
  459. "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \
  460. "protect on " MK_STR(TEXT_BASE) " +$filesize; " \
  461. "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \
  462. "consoledev=ttyS1\0" \
  463. "ramdiskaddr=2000000\0" \
  464. "ramdiskfile=ramdisk.uboot\0" \
  465. "fdtaddr=c00000\0" \
  466. "fdtfile=mpc8548cds.dtb\0"
  467. #define CONFIG_NFSBOOTCOMMAND \
  468. "setenv bootargs root=/dev/nfs rw " \
  469. "nfsroot=$serverip:$rootpath " \
  470. "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
  471. "console=$consoledev,$baudrate $othbootargs;" \
  472. "tftp $loadaddr $bootfile;" \
  473. "tftp $fdtaddr $fdtfile;" \
  474. "bootm $loadaddr - $fdtaddr"
  475. #define CONFIG_RAMBOOTCOMMAND \
  476. "setenv bootargs root=/dev/ram rw " \
  477. "console=$consoledev,$baudrate $othbootargs;" \
  478. "tftp $ramdiskaddr $ramdiskfile;" \
  479. "tftp $loadaddr $bootfile;" \
  480. "tftp $fdtaddr $fdtfile;" \
  481. "bootm $loadaddr $ramdiskaddr $fdtaddr"
  482. #define CONFIG_BOOTCOMMAND CONFIG_NFSBOOTCOMMAND
  483. #endif /* __CONFIG_H */