MOUSSE.h 12 KB

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  1. /*
  2. * (C) Copyright 2000, 2001
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * (C) Copyright 2001
  6. * James F. Dougherty (jfd@cs.stanford.edu)
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. *
  28. * Configuration settings for the MOUSSE board.
  29. * See also: http://www.vooha.com/
  30. *
  31. */
  32. /* ------------------------------------------------------------------------- */
  33. /*
  34. * board/config.h - configuration options, board specific
  35. */
  36. #ifndef __CONFIG_H
  37. #define __CONFIG_H
  38. /*
  39. * High Level Configuration Options
  40. * (easy to change)
  41. */
  42. #define CONFIG_MPC824X 1
  43. #define CONFIG_MPC8240 1
  44. #define CONFIG_MOUSSE 1
  45. #define CONFIG_SYS_ADDR_MAP_B 1
  46. #define CONFIG_CONS_INDEX 1
  47. #define CONFIG_BAUDRATE 9600
  48. #if 1
  49. #define CONFIG_BOOTCOMMAND "tftp 100000 vmlinux.img;bootm" /* autoboot command */
  50. #else
  51. #define CONFIG_BOOTCOMMAND "bootm ffe10000"
  52. #endif
  53. #define CONFIG_BOOTARGS "console=ttyS0 root=/dev/nfs rw nfsroot=209.128.93.133:/boot nfsaddrs=209.128.93.133:209.128.93.138"
  54. #define CONFIG_BOOTDELAY 3
  55. /*
  56. * BOOTP options
  57. */
  58. #define CONFIG_BOOTP_BOOTFILESIZE
  59. #define CONFIG_BOOTP_BOOTPATH
  60. #define CONFIG_BOOTP_GATEWAY
  61. #define CONFIG_BOOTP_HOSTNAME
  62. /*
  63. * Command line configuration.
  64. */
  65. #include <config_cmd_default.h>
  66. #define CONFIG_CMD_ASKENV
  67. #define CONFIG_CMD_DATE
  68. #define CONFIG_ENV_OVERWRITE 1
  69. #define CONFIG_ETH_ADDR "00:10:18:10:00:06"
  70. #define CONFIG_DOS_PARTITION 1 /* MSDOS bootable partitiion support */
  71. #include "../board/mousse/mousse.h"
  72. /*
  73. * Miscellaneous configurable options
  74. */
  75. #undef CONFIG_SYS_LONGHELP /* undef to save memory */
  76. #define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */
  77. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  78. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
  79. #define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
  80. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  81. #define CONFIG_SYS_LOAD_ADDR 0x00100000 /* Default load address */
  82. /*-----------------------------------------------------------------------
  83. * Start addresses for the final memory configuration
  84. * (Set up by the startup code)
  85. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  86. */
  87. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  88. #ifdef DEBUG
  89. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_SDRAM_BASE
  90. #else
  91. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  92. #endif
  93. #ifdef DEBUG
  94. #define CONFIG_SYS_MONITOR_LEN (4 << 20) /* lots of mem ... */
  95. #else
  96. #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512K PLCC bootrom */
  97. #endif
  98. #define CONFIG_SYS_MALLOC_LEN (2*(4096 << 10)) /* 2*4096kB for malloc() */
  99. #define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
  100. #define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
  101. #define CONFIG_SYS_EUMB_ADDR 0xFC000000
  102. #define CONFIG_SYS_ISA_MEM 0xFD000000
  103. #define CONFIG_SYS_ISA_IO 0xFE000000
  104. #define CONFIG_SYS_FLASH_BASE 0xFFF00000
  105. #define CONFIG_SYS_FLASH_SIZE ((uint)(512 * 1024))
  106. #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
  107. #define FLASH_BASE0_PRELIM 0xFFF00000 /* 512K PLCC FLASH/AM29F040*/
  108. #define FLASH_BASE0_SIZE 0x80000 /* 512K */
  109. #define FLASH_BASE1_PRELIM 0xFFE10000 /* AMD 29LV160DB
  110. 1MB - 64K FLASH0 SEG =960K
  111. (size=0xf0000)*/
  112. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  113. /*
  114. * NS16550 Configuration
  115. */
  116. #define CONFIG_SYS_NS16550
  117. #define CONFIG_SYS_NS16550_SERIAL
  118. #define CONFIG_SYS_NS16550_REG_SIZE 1
  119. #define CONFIG_SYS_NS16550_CLK 18432000
  120. #define CONFIG_SYS_NS16550_COM1 0xFFE08080
  121. /*-----------------------------------------------------------------------
  122. * Definitions for initial stack pointer and data area (in DPRAM)
  123. */
  124. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_SDRAM_BASE + CONFIG_SYS_MONITOR_LEN
  125. #define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
  126. #define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
  127. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  128. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  129. /*
  130. * Low Level Configuration Settings
  131. * (address mappings, register initial values, etc.)
  132. * You should know what you are doing if you make changes here.
  133. * For the detail description refer to the MPC8240 user's manual.
  134. */
  135. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  136. #define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 2
  137. #define CONFIG_SYS_HZ 1000
  138. #define CONFIG_SYS_ETH_DEV_FN 0x00
  139. #define CONFIG_SYS_ETH_IOBASE 0x00104000
  140. /* Bit-field values for MCCR1.
  141. */
  142. #define CONFIG_SYS_ROMNAL 8
  143. #define CONFIG_SYS_ROMFAL 8
  144. /* Bit-field values for MCCR2.
  145. */
  146. #define CONFIG_SYS_REFINT 0xf5 /* Refresh interval */
  147. /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
  148. */
  149. #define CONFIG_SYS_BSTOPRE 0x79
  150. #ifdef INCLUDE_ECC
  151. #define USE_ECC 1
  152. #else /* INCLUDE_ECC */
  153. #define USE_ECC 0
  154. #endif /* INCLUDE_ECC */
  155. /* Bit-field values for MCCR3.
  156. */
  157. #define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
  158. #define CONFIG_SYS_RDLAT (4+USE_ECC) /* Data latancy from read command */
  159. /* Bit-field values for MCCR4.
  160. */
  161. #define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
  162. #define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
  163. #define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
  164. #define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
  165. #define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length */
  166. #define CONFIG_SYS_ACTORW 2
  167. #define CONFIG_SYS_REGISTERD_TYPE_BUFFER (1-USE_ECC)
  168. /* Memory bank settings.
  169. * Only bits 20-29 are actually used from these vales to set the
  170. * start/end addresses. The upper two bits will always be 0, and the lower
  171. * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
  172. * address. Refer to the MPC8240 book.
  173. */
  174. #define CONFIG_SYS_RAM_SIZE 0x04000000 /* 64MB */
  175. #define CONFIG_SYS_BANK0_START 0x00000000
  176. #define CONFIG_SYS_BANK0_END (CONFIG_SYS_RAM_SIZE - 1)
  177. #define CONFIG_SYS_BANK0_ENABLE 1
  178. #define CONFIG_SYS_BANK1_START 0x3ff00000
  179. #define CONFIG_SYS_BANK1_END 0x3fffffff
  180. #define CONFIG_SYS_BANK1_ENABLE 0
  181. #define CONFIG_SYS_BANK2_START 0x3ff00000
  182. #define CONFIG_SYS_BANK2_END 0x3fffffff
  183. #define CONFIG_SYS_BANK2_ENABLE 0
  184. #define CONFIG_SYS_BANK3_START 0x3ff00000
  185. #define CONFIG_SYS_BANK3_END 0x3fffffff
  186. #define CONFIG_SYS_BANK3_ENABLE 0
  187. #define CONFIG_SYS_BANK4_START 0x3ff00000
  188. #define CONFIG_SYS_BANK4_END 0x3fffffff
  189. #define CONFIG_SYS_BANK4_ENABLE 0
  190. #define CONFIG_SYS_BANK5_START 0x3ff00000
  191. #define CONFIG_SYS_BANK5_END 0x3fffffff
  192. #define CONFIG_SYS_BANK5_ENABLE 0
  193. #define CONFIG_SYS_BANK6_START 0x3ff00000
  194. #define CONFIG_SYS_BANK6_END 0x3fffffff
  195. #define CONFIG_SYS_BANK6_ENABLE 0
  196. #define CONFIG_SYS_BANK7_START 0x3ff00000
  197. #define CONFIG_SYS_BANK7_END 0x3fffffff
  198. #define CONFIG_SYS_BANK7_ENABLE 0
  199. #define CONFIG_SYS_ODCR 0x7f
  200. #define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory
  201. see 8240 book for details*/
  202. #define PCI_MEM_SPACE1_START 0x80000000
  203. #define PCI_MEM_SPACE2_START 0xfd000000
  204. /* IBAT/DBAT Configuration */
  205. /* Ram: 64MB, starts at address-0, r/w instruction/data */
  206. #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_64M | BATU_VS | BATU_VP)
  207. #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
  208. #define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
  209. #define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
  210. /* MPLD/Port-X I/O Space : data and instruction read/write, cache-inhibit */
  211. #define CONFIG_SYS_IBAT1U (PORTX_DEV_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
  212. #if 0
  213. #define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 | BATL_MEMCOHERENCE |\
  214. BATL_WRITETHROUGH | BATL_CACHEINHIBIT)
  215. #else
  216. #define CONFIG_SYS_IBAT1L (PORTX_DEV_BASE | BATL_PP_10 |BATL_CACHEINHIBIT)
  217. #endif
  218. #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
  219. #define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
  220. /* PCI Memory region 1: 0x8XXX_XXXX PCI Mem space: EUMBAR, etc - 16MB */
  221. #define CONFIG_SYS_IBAT2U (PCI_MEM_SPACE1_START|BATU_BL_16M | BATU_VS | BATU_VP)
  222. #define CONFIG_SYS_IBAT2L (PCI_MEM_SPACE1_START|BATL_PP_10 | BATL_GUARDEDSTORAGE|BATL_CACHEINHIBIT)
  223. #define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
  224. #define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
  225. /* PCI Memory region 2: PCI Devices in 0xFD space */
  226. #define CONFIG_SYS_IBAT3U (PCI_MEM_SPACE2_START|BATU_BL_16M | BATU_VS | BATU_VP)
  227. #define CONFIG_SYS_IBAT3L (PCI_MEM_SPACE2_START|BATL_PP_10 | BATL_GUARDEDSTORAGE | BATL_CACHEINHIBIT)
  228. #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
  229. #define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
  230. /*
  231. * For booting Linux, the board info and command line data
  232. * have to be in the first 8 MB of memory, since this is
  233. * the maximum mapped by the Linux kernel during initialization.
  234. */
  235. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  236. /*-----------------------------------------------------------------------
  237. * FLASH organization
  238. */
  239. #define CONFIG_SYS_MAX_FLASH_BANKS 3 /* Max number of flash banks */
  240. #define CONFIG_SYS_MAX_FLASH_SECT 64 /* Max number of sectors in one bank */
  241. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  242. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  243. #if 0
  244. #define CONFIG_ENV_IS_IN_FLASH 1
  245. #define CONFIG_ENV_OFFSET 0x8000 /* Offset of the Environment Sector */
  246. #define CONFIG_ENV_SIZE 0x4000 /* Size of the Environment Sector */
  247. #else
  248. #define CONFIG_ENV_IS_IN_NVRAM 1
  249. #define CONFIG_ENV_ADDR NV_OFF_U_BOOT_ADDR /* PortX NVM Free addr*/
  250. #define CONFIG_ENV_OFFSET CONFIG_ENV_ADDR
  251. #define CONFIG_ENV_SIZE NV_U_BOOT_ENV_SIZE /* 2K */
  252. #endif
  253. /*-----------------------------------------------------------------------
  254. * Cache Configuration
  255. */
  256. #define CONFIG_SYS_CACHELINE_SIZE 16
  257. /*
  258. * Internal Definitions
  259. *
  260. * Boot Flags
  261. */
  262. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  263. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  264. /* Localizations */
  265. #if 0
  266. #define CONFIG_ETHADDR 0:0:0:0:1:d
  267. #define CONFIG_IPADDR 172.16.40.113
  268. #define CONFIG_SERVERIP 172.16.40.111
  269. #else
  270. #define CONFIG_ETHADDR 0:0:0:0:1:d
  271. #define CONFIG_IPADDR 209.128.93.138
  272. #define CONFIG_SERVERIP 209.128.93.133
  273. #endif
  274. /*-----------------------------------------------------------------------
  275. * PCI stuff
  276. *-----------------------------------------------------------------------
  277. */
  278. #define CONFIG_PCI /* include pci support */
  279. #undef CONFIG_PCI_PNP
  280. #define CONFIG_NET_MULTI /* Multi ethernet cards support */
  281. #define CONFIG_TULIP
  282. #endif /* __CONFIG_H */