CPU87.h 21 KB

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  1. /*
  2. * (C) Copyright 2001-2005
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
  33. #define CONFIG_CPU87 1 /* ...on a CPU87 board */
  34. #define CONFIG_PCI
  35. #define CONFIG_CPM2 1 /* Has a CPM2 */
  36. /*
  37. * select serial console configuration
  38. *
  39. * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  40. * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  41. * for SCC).
  42. *
  43. * if CONFIG_CONS_NONE is defined, then the serial console routines must
  44. * defined elsewhere (for example, on the cogent platform, there are serial
  45. * ports on the motherboard which are used for the serial console - see
  46. * cogent/cma101/serial.[ch]).
  47. */
  48. #undef CONFIG_CONS_ON_SMC /* define if console on SMC */
  49. #define CONFIG_CONS_ON_SCC /* define if console on SCC */
  50. #undef CONFIG_CONS_NONE /* define if console on something else*/
  51. #define CONFIG_CONS_INDEX 1 /* which serial channel for console */
  52. #if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
  53. #define CONFIG_BAUDRATE 230400
  54. #else
  55. #define CONFIG_BAUDRATE 9600
  56. #endif
  57. /*
  58. * select ethernet configuration
  59. *
  60. * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  61. * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  62. * for FCC)
  63. *
  64. * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  65. * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  66. */
  67. #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
  68. #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
  69. #undef CONFIG_ETHER_NONE /* define if ether on something else */
  70. #define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
  71. #define CONFIG_HAS_ETH1 1
  72. #define CONFIG_HAS_ETH2 1
  73. #if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1)
  74. /*
  75. * - Rx-CLK is CLK11
  76. * - Tx-CLK is CLK12
  77. * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  78. * - Enable Full Duplex in FSMR
  79. */
  80. # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  81. # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11|CMXFCR_TF1CS_CLK12)
  82. # define CONFIG_SYS_CPMFCR_RAMTYPE 0
  83. # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
  84. #elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
  85. /*
  86. * - Rx-CLK is CLK13
  87. * - Tx-CLK is CLK14
  88. * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  89. * - Enable Full Duplex in FSMR
  90. */
  91. # define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  92. # define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
  93. # define CONFIG_SYS_CPMFCR_RAMTYPE 0
  94. # define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
  95. #endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
  96. /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
  97. #define CONFIG_8260_CLKIN 100000000 /* in Hz */
  98. #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
  99. #define CONFIG_PREBOOT \
  100. "echo; " \
  101. "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; " \
  102. "echo"
  103. #undef CONFIG_BOOTARGS
  104. #define CONFIG_BOOTCOMMAND \
  105. "bootp; " \
  106. "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
  107. "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
  108. "bootm"
  109. /*-----------------------------------------------------------------------
  110. * I2C/EEPROM/RTC configuration
  111. */
  112. #define CONFIG_SOFT_I2C /* Software I2C support enabled */
  113. # define CONFIG_SYS_I2C_SPEED 50000
  114. # define CONFIG_SYS_I2C_SLAVE 0xFE
  115. /*
  116. * Software (bit-bang) I2C driver configuration
  117. */
  118. #define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
  119. #define I2C_ACTIVE (iop->pdir |= 0x00010000)
  120. #define I2C_TRISTATE (iop->pdir &= ~0x00010000)
  121. #define I2C_READ ((iop->pdat & 0x00010000) != 0)
  122. #define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
  123. else iop->pdat &= ~0x00010000
  124. #define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
  125. else iop->pdat &= ~0x00020000
  126. #define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
  127. #define CONFIG_RTC_PCF8563
  128. #define CONFIG_SYS_I2C_RTC_ADDR 0x51
  129. #undef CONFIG_WATCHDOG /* watchdog disabled */
  130. /*-----------------------------------------------------------------------
  131. * Disk-On-Chip configuration
  132. */
  133. #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
  134. #define CONFIG_SYS_DOC_SUPPORT_2000
  135. #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
  136. /*-----------------------------------------------------------------------
  137. * Miscellaneous configuration options
  138. */
  139. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  140. #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
  141. /*
  142. * BOOTP options
  143. */
  144. #define CONFIG_BOOTP_SUBNETMASK
  145. #define CONFIG_BOOTP_GATEWAY
  146. #define CONFIG_BOOTP_HOSTNAME
  147. #define CONFIG_BOOTP_BOOTPATH
  148. #define CONFIG_BOOTP_BOOTFILESIZE
  149. /*
  150. * Command line configuration.
  151. */
  152. #include <config_cmd_default.h>
  153. #define CONFIG_CMD_BEDBUG
  154. #define CONFIG_CMD_DATE
  155. #define CONFIG_CMD_EEPROM
  156. #define CONFIG_CMD_I2C
  157. #ifdef CONFIG_PCI
  158. #define CONFIG_CMD_PCI
  159. #endif
  160. /*
  161. * Miscellaneous configurable options
  162. */
  163. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  164. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  165. #if defined(CONFIG_CMD_KGDB)
  166. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  167. #else
  168. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  169. #endif
  170. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  171. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  172. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  173. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  174. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  175. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  176. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  177. #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
  178. #define CONFIG_SYS_RESET_ADDRESS 0xFFF00100 /* "bad" address */
  179. #define CONFIG_LOOPW
  180. /*
  181. * For booting Linux, the board info and command line data
  182. * have to be in the first 8 MB of memory, since this is
  183. * the maximum mapped by the Linux kernel during initialization.
  184. */
  185. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  186. /*-----------------------------------------------------------------------
  187. * Flash configuration
  188. */
  189. #define CONFIG_SYS_BOOTROM_BASE 0xFF800000
  190. #define CONFIG_SYS_BOOTROM_SIZE 0x00080000
  191. #define CONFIG_SYS_FLASH_BASE 0xFF000000
  192. #define CONFIG_SYS_FLASH_SIZE 0x00800000
  193. /*-----------------------------------------------------------------------
  194. * FLASH organization
  195. */
  196. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max num of memory banks */
  197. #define CONFIG_SYS_MAX_FLASH_SECT 135 /* max num of sects on one chip */
  198. #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
  199. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
  200. /*-----------------------------------------------------------------------
  201. * Other areas to be mapped
  202. */
  203. /* CS3: Dual ported SRAM */
  204. #define CONFIG_SYS_DPSRAM_BASE 0x40000000
  205. #define CONFIG_SYS_DPSRAM_SIZE 0x00100000
  206. /* CS4: DiskOnChip */
  207. #define CONFIG_SYS_DOC_BASE 0xF4000000
  208. #define CONFIG_SYS_DOC_SIZE 0x00100000
  209. /* CS5: FDC37C78 controller */
  210. #define CONFIG_SYS_FDC37C78_BASE 0xF1000000
  211. #define CONFIG_SYS_FDC37C78_SIZE 0x00100000
  212. /* CS6: Board configuration registers */
  213. #define CONFIG_SYS_BCRS_BASE 0xF2000000
  214. #define CONFIG_SYS_BCRS_SIZE 0x00010000
  215. /* CS7: VME Extended Access Range */
  216. #define CONFIG_SYS_VMEEAR_BASE 0x60000000
  217. #define CONFIG_SYS_VMEEAR_SIZE 0x01000000
  218. /* CS8: VME Standard Access Range */
  219. #define CONFIG_SYS_VMESAR_BASE 0xFE000000
  220. #define CONFIG_SYS_VMESAR_SIZE 0x01000000
  221. /* CS9: VME Short I/O Access Range */
  222. #define CONFIG_SYS_VMESIOAR_BASE 0xFD000000
  223. #define CONFIG_SYS_VMESIOAR_SIZE 0x01000000
  224. /*-----------------------------------------------------------------------
  225. * Hard Reset Configuration Words
  226. *
  227. * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
  228. * defines for the various registers affected by the HRCW e.g. changing
  229. * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
  230. */
  231. #if defined(CONFIG_BOOT_ROM)
  232. #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | \
  233. HRCW_BPS01 | HRCW_CS10PC01)
  234. #else
  235. #define CONFIG_SYS_HRCW_MASTER (HRCW_CIP | HRCW_ISB100 | HRCW_BMS | HRCW_CS10PC01)
  236. #endif
  237. /* no slaves so just fill with zeros */
  238. #define CONFIG_SYS_HRCW_SLAVE1 0
  239. #define CONFIG_SYS_HRCW_SLAVE2 0
  240. #define CONFIG_SYS_HRCW_SLAVE3 0
  241. #define CONFIG_SYS_HRCW_SLAVE4 0
  242. #define CONFIG_SYS_HRCW_SLAVE5 0
  243. #define CONFIG_SYS_HRCW_SLAVE6 0
  244. #define CONFIG_SYS_HRCW_SLAVE7 0
  245. /*-----------------------------------------------------------------------
  246. * Internal Memory Mapped Register
  247. */
  248. #define CONFIG_SYS_IMMR 0xF0000000
  249. /*-----------------------------------------------------------------------
  250. * Definitions for initial stack pointer and data area (in DPRAM)
  251. */
  252. #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
  253. #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in DPRAM */
  254. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data*/
  255. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  256. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  257. /*-----------------------------------------------------------------------
  258. * Start addresses for the final memory configuration
  259. * (Set up by the startup code)
  260. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  261. *
  262. * 60x SDRAM is mapped at CONFIG_SYS_SDRAM_BASE.
  263. */
  264. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  265. #define CONFIG_SYS_SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */
  266. #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
  267. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
  268. #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
  269. #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  270. # define CONFIG_SYS_RAMBOOT
  271. #endif
  272. #ifdef CONFIG_PCI
  273. #define CONFIG_PCI_PNP
  274. #define CONFIG_EEPRO100
  275. #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
  276. #endif
  277. #if 0
  278. /* environment is in Flash */
  279. #define CONFIG_ENV_IS_IN_FLASH 1
  280. #ifdef CONFIG_BOOT_ROM
  281. # define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE+0x70000)
  282. # define CONFIG_ENV_SIZE 0x10000
  283. # define CONFIG_ENV_SECT_SIZE 0x10000
  284. #endif
  285. #else
  286. /* environment is in EEPROM */
  287. #define CONFIG_ENV_IS_IN_EEPROM 1
  288. #define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* EEPROM X24C16 */
  289. #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
  290. /* mask of address bits that overflow into the "EEPROM chip address" */
  291. #define CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 0x07
  292. #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
  293. #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
  294. #define CONFIG_ENV_OFFSET 512
  295. #define CONFIG_ENV_SIZE (2048 - 512)
  296. #endif
  297. /*
  298. * Internal Definitions
  299. *
  300. * Boot Flags
  301. */
  302. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH*/
  303. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  304. /*-----------------------------------------------------------------------
  305. * Cache Configuration
  306. */
  307. #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
  308. #if defined(CONFIG_CMD_KGDB)
  309. # define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
  310. #endif
  311. /*-----------------------------------------------------------------------
  312. * HIDx - Hardware Implementation-dependent Registers 2-11
  313. *-----------------------------------------------------------------------
  314. * HID0 also contains cache control - initially enable both caches and
  315. * invalidate contents, then the final state leaves only the instruction
  316. * cache enabled. Note that Power-On and Hard reset invalidate the caches,
  317. * but Soft reset does not.
  318. *
  319. * HID1 has only read-only information - nothing to set.
  320. */
  321. #define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\
  322. HID0_DCI|HID0_IFEM|HID0_ABE)
  323. #define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
  324. #define CONFIG_SYS_HID2 0
  325. /*-----------------------------------------------------------------------
  326. * RMR - Reset Mode Register 5-5
  327. *-----------------------------------------------------------------------
  328. * turn on Checkstop Reset Enable
  329. */
  330. #define CONFIG_SYS_RMR RMR_CSRE
  331. /*-----------------------------------------------------------------------
  332. * BCR - Bus Configuration 4-25
  333. *-----------------------------------------------------------------------
  334. */
  335. #define BCR_APD01 0x10000000
  336. #define CONFIG_SYS_BCR (BCR_APD01|BCR_ETM|BCR_LETM) /* 8260 mode */
  337. /*-----------------------------------------------------------------------
  338. * SIUMCR - SIU Module Configuration 4-31
  339. *-----------------------------------------------------------------------
  340. */
  341. #define CONFIG_SYS_SIUMCR (SIUMCR_BBD|SIUMCR_DPPC00|SIUMCR_APPC10|\
  342. SIUMCR_CS10PC01|SIUMCR_BCTLC10)
  343. /*-----------------------------------------------------------------------
  344. * SYPCR - System Protection Control 4-35
  345. * SYPCR can only be written once after reset!
  346. *-----------------------------------------------------------------------
  347. * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
  348. */
  349. #if defined(CONFIG_WATCHDOG)
  350. #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
  351. SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
  352. #else
  353. #define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
  354. SYPCR_SWRI|SYPCR_SWP)
  355. #endif /* CONFIG_WATCHDOG */
  356. /*-----------------------------------------------------------------------
  357. * TMCNTSC - Time Counter Status and Control 4-40
  358. *-----------------------------------------------------------------------
  359. * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
  360. * and enable Time Counter
  361. */
  362. #define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
  363. /*-----------------------------------------------------------------------
  364. * PISCR - Periodic Interrupt Status and Control 4-42
  365. *-----------------------------------------------------------------------
  366. * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
  367. * Periodic timer
  368. */
  369. #define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
  370. /*-----------------------------------------------------------------------
  371. * SCCR - System Clock Control 9-8
  372. *-----------------------------------------------------------------------
  373. * Ensure DFBRG is Divide by 16
  374. */
  375. #define CONFIG_SYS_SCCR SCCR_DFBRG01
  376. /*-----------------------------------------------------------------------
  377. * RCCR - RISC Controller Configuration 13-7
  378. *-----------------------------------------------------------------------
  379. */
  380. #define CONFIG_SYS_RCCR 0
  381. #define CONFIG_SYS_MIN_AM_MASK 0xC0000000
  382. /*
  383. * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
  384. * refresh rate = 7.68 uS (100 MHz Bus Clock)
  385. */
  386. /*-----------------------------------------------------------------------
  387. * MPTPR - Memory Refresh Timer Prescaler Register 10-18
  388. *-----------------------------------------------------------------------
  389. */
  390. #define CONFIG_SYS_MPTPR 0x2000
  391. /*-----------------------------------------------------------------------
  392. * PSRT - Refresh Timer Register 10-16
  393. *-----------------------------------------------------------------------
  394. */
  395. #define CONFIG_SYS_PSRT 0x16
  396. /*-----------------------------------------------------------------------
  397. * PSRT - SDRAM Mode Register 10-10
  398. *-----------------------------------------------------------------------
  399. */
  400. /* SDRAM initialization values for 8-column chips
  401. */
  402. #define CONFIG_SYS_OR2_8COL (CONFIG_SYS_MIN_AM_MASK |\
  403. ORxS_BPD_4 |\
  404. ORxS_ROWST_PBI0_A9 |\
  405. ORxS_NUMR_12)
  406. #define CONFIG_SYS_PSDMR_8COL (PSDMR_SDAM_A13_IS_A5 |\
  407. PSDMR_BSMA_A14_A16 |\
  408. PSDMR_SDA10_PBI0_A10 |\
  409. PSDMR_RFRC_7_CLK |\
  410. PSDMR_PRETOACT_2W |\
  411. PSDMR_ACTTORW_2W |\
  412. PSDMR_LDOTOPRE_1C |\
  413. PSDMR_WRC_1C |\
  414. PSDMR_CL_2)
  415. /* SDRAM initialization values for 9-column chips
  416. */
  417. #define CONFIG_SYS_OR2_9COL (CONFIG_SYS_MIN_AM_MASK |\
  418. ORxS_BPD_4 |\
  419. ORxS_ROWST_PBI0_A7 |\
  420. ORxS_NUMR_13)
  421. #define CONFIG_SYS_PSDMR_9COL (PSDMR_SDAM_A14_IS_A5 |\
  422. PSDMR_BSMA_A13_A15 |\
  423. PSDMR_SDA10_PBI0_A9 |\
  424. PSDMR_RFRC_7_CLK |\
  425. PSDMR_PRETOACT_2W |\
  426. PSDMR_ACTTORW_2W |\
  427. PSDMR_LDOTOPRE_1C |\
  428. PSDMR_WRC_1C |\
  429. PSDMR_CL_2)
  430. /* SDRAM initialization values for 10-column chips
  431. */
  432. #define CONFIG_SYS_OR2_10COL (CONFIG_SYS_MIN_AM_MASK |\
  433. ORxS_BPD_4 |\
  434. ORxS_ROWST_PBI1_A4 |\
  435. ORxS_NUMR_13)
  436. #define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
  437. PSDMR_SDAM_A17_IS_A5 |\
  438. PSDMR_BSMA_A13_A15 |\
  439. PSDMR_SDA10_PBI1_A6 |\
  440. PSDMR_RFRC_7_CLK |\
  441. PSDMR_PRETOACT_2W |\
  442. PSDMR_ACTTORW_2W |\
  443. PSDMR_LDOTOPRE_1C |\
  444. PSDMR_WRC_1C |\
  445. PSDMR_CL_2)
  446. /*
  447. * Init Memory Controller:
  448. *
  449. * Bank Bus Machine PortSz Device
  450. * ---- --- ------- ------ ------
  451. * 0 60x GPCM 8 bit Boot ROM
  452. * 1 60x GPCM 64 bit FLASH
  453. * 2 60x SDRAM 64 bit SDRAM
  454. *
  455. */
  456. #define CONFIG_SYS_MRS_OFFS 0x00000000
  457. #ifdef CONFIG_BOOT_ROM
  458. /* Bank 0 - Boot ROM
  459. */
  460. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
  461. BRx_PS_8 |\
  462. BRx_MS_GPCM_P |\
  463. BRx_V)
  464. #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
  465. ORxG_CSNT |\
  466. ORxG_ACS_DIV1 |\
  467. ORxG_SCY_5_CLK |\
  468. ORxU_EHTR_8IDLE)
  469. /* Bank 1 - FLASH
  470. */
  471. #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
  472. BRx_PS_64 |\
  473. BRx_MS_GPCM_P |\
  474. BRx_V)
  475. #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
  476. ORxG_CSNT |\
  477. ORxG_ACS_DIV1 |\
  478. ORxG_SCY_5_CLK |\
  479. ORxU_EHTR_8IDLE)
  480. #else /* CONFIG_BOOT_ROM */
  481. /* Bank 0 - FLASH
  482. */
  483. #define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
  484. BRx_PS_64 |\
  485. BRx_MS_GPCM_P |\
  486. BRx_V)
  487. #define CONFIG_SYS_OR0_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
  488. ORxG_CSNT |\
  489. ORxG_ACS_DIV1 |\
  490. ORxG_SCY_5_CLK |\
  491. ORxU_EHTR_8IDLE)
  492. /* Bank 1 - Boot ROM
  493. */
  494. #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_BOOTROM_BASE & BRx_BA_MSK)|\
  495. BRx_PS_8 |\
  496. BRx_MS_GPCM_P |\
  497. BRx_V)
  498. #define CONFIG_SYS_OR1_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BOOTROM_SIZE) |\
  499. ORxG_CSNT |\
  500. ORxG_ACS_DIV1 |\
  501. ORxG_SCY_5_CLK |\
  502. ORxU_EHTR_8IDLE)
  503. #endif /* CONFIG_BOOT_ROM */
  504. /* Bank 2 - 60x bus SDRAM
  505. */
  506. #ifndef CONFIG_SYS_RAMBOOT
  507. #define CONFIG_SYS_BR2_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
  508. BRx_PS_64 |\
  509. BRx_MS_SDRAM_P |\
  510. BRx_V)
  511. #define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_OR2_8COL
  512. #define CONFIG_SYS_PSDMR CONFIG_SYS_PSDMR_8COL
  513. #endif /* CONFIG_SYS_RAMBOOT */
  514. /* Bank 3 - Dual Ported SRAM
  515. */
  516. #define CONFIG_SYS_BR3_PRELIM ((CONFIG_SYS_DPSRAM_BASE & BRx_BA_MSK) |\
  517. BRx_PS_16 |\
  518. BRx_MS_GPCM_P |\
  519. BRx_V)
  520. #define CONFIG_SYS_OR3_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DPSRAM_SIZE) |\
  521. ORxG_CSNT |\
  522. ORxG_ACS_DIV1 |\
  523. ORxG_SCY_7_CLK |\
  524. ORxG_SETA)
  525. /* Bank 4 - DiskOnChip
  526. */
  527. #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_DOC_BASE & BRx_BA_MSK) |\
  528. BRx_PS_8 |\
  529. BRx_MS_GPCM_P |\
  530. BRx_V)
  531. #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_DOC_SIZE) |\
  532. ORxG_CSNT |\
  533. ORxG_ACS_DIV2 |\
  534. ORxG_SCY_9_CLK |\
  535. ORxU_EHTR_8IDLE)
  536. /* Bank 5 - FDC37C78 controller
  537. */
  538. #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_FDC37C78_BASE & BRx_BA_MSK) |\
  539. BRx_PS_8 |\
  540. BRx_MS_GPCM_P |\
  541. BRx_V)
  542. #define CONFIG_SYS_OR5_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FDC37C78_SIZE) |\
  543. ORxG_ACS_DIV2 |\
  544. ORxG_SCY_10_CLK |\
  545. ORxU_EHTR_8IDLE)
  546. /* Bank 6 - Board control registers
  547. */
  548. #define CONFIG_SYS_BR6_PRELIM ((CONFIG_SYS_BCRS_BASE & BRx_BA_MSK) |\
  549. BRx_PS_8 |\
  550. BRx_MS_GPCM_P |\
  551. BRx_V)
  552. #define CONFIG_SYS_OR6_PRELIM (P2SZ_TO_AM(CONFIG_SYS_BCRS_SIZE) |\
  553. ORxG_CSNT |\
  554. ORxG_SCY_7_CLK)
  555. /* Bank 7 - VME Extended Access Range
  556. */
  557. #define CONFIG_SYS_BR7_PRELIM ((CONFIG_SYS_VMEEAR_BASE & BRx_BA_MSK) |\
  558. BRx_PS_32 |\
  559. BRx_MS_GPCM_P |\
  560. BRx_V)
  561. #define CONFIG_SYS_OR7_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMEEAR_SIZE) |\
  562. ORxG_CSNT |\
  563. ORxG_ACS_DIV1 |\
  564. ORxG_SCY_7_CLK |\
  565. ORxG_SETA)
  566. /* Bank 8 - VME Standard Access Range
  567. */
  568. #define CONFIG_SYS_BR8_PRELIM ((CONFIG_SYS_VMESAR_BASE & BRx_BA_MSK) |\
  569. BRx_PS_16 |\
  570. BRx_MS_GPCM_P |\
  571. BRx_V)
  572. #define CONFIG_SYS_OR8_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESAR_SIZE) |\
  573. ORxG_CSNT |\
  574. ORxG_ACS_DIV1 |\
  575. ORxG_SCY_7_CLK |\
  576. ORxG_SETA)
  577. /* Bank 9 - VME Short I/O Access Range
  578. */
  579. #define CONFIG_SYS_BR9_PRELIM ((CONFIG_SYS_VMESIOAR_BASE & BRx_BA_MSK) |\
  580. BRx_PS_16 |\
  581. BRx_MS_GPCM_P |\
  582. BRx_V)
  583. #define CONFIG_SYS_OR9_PRELIM (P2SZ_TO_AM(CONFIG_SYS_VMESIOAR_SIZE) |\
  584. ORxG_CSNT |\
  585. ORxG_ACS_DIV1 |\
  586. ORxG_SCY_7_CLK |\
  587. ORxG_SETA)
  588. #endif /* __CONFIG_H */