AR405.h 10 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274
  1. /*
  2. * (C) Copyright 2001-2004
  3. * Stefan Roese, esd gmbh germany, stefan.roese@esd-electronics.com
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. /*
  24. * board/config.h - configuration options, board specific
  25. */
  26. #ifndef __CONFIG_H
  27. #define __CONFIG_H
  28. /*
  29. * High Level Configuration Options
  30. * (easy to change)
  31. */
  32. #define CONFIG_405GP 1 /* This is a PPC405GP CPU */
  33. #define CONFIG_4xx 1 /* ...member of PPC4xx family */
  34. #define CONFIG_AR405 1 /* ...on a AR405 board */
  35. #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */
  36. #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
  37. #define CONFIG_BOARD_TYPES 1 /* support board types */
  38. #define CONFIG_BAUDRATE 9600
  39. #define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
  40. #if 1
  41. #define CONFIG_BOOTCOMMAND "bootm fff00000" /* autoboot command */
  42. #else
  43. #define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
  44. #endif
  45. #if 0
  46. #define CONFIG_BOOTARGS "root=/dev/nfs " \
  47. "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \
  48. "nfsroot=192.168.2.190:/home/stefan/cpci405/target_ftest4"
  49. #else
  50. #define CONFIG_BOOTARGS "root=/dev/hda1 " \
  51. "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0"
  52. #endif
  53. #define CONFIG_PREBOOT /* enable preboot variable */
  54. #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
  55. #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
  56. #define CONFIG_PPC4xx_EMAC
  57. #define CONFIG_MII 1 /* MII PHY management */
  58. #define CONFIG_PHY_ADDR 0 /* PHY address */
  59. #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */
  60. #define CONFIG_NET_MULTI
  61. /*
  62. * BOOTP options
  63. */
  64. #define CONFIG_BOOTP_BOOTFILESIZE
  65. #define CONFIG_BOOTP_BOOTPATH
  66. #define CONFIG_BOOTP_GATEWAY
  67. #define CONFIG_BOOTP_HOSTNAME
  68. /*
  69. * Command line configuration.
  70. */
  71. #include <config_cmd_default.h>
  72. #define CONFIG_CMD_DHCP
  73. #define CONFIG_CMD_PCI
  74. #define CONFIG_CMD_IRQ
  75. #define CONFIG_CMD_ELF
  76. #define CONFIG_CMD_MII
  77. #undef CONFIG_CMD_NFS
  78. #define CONFIG_CMD_PING
  79. #define CONFIG_CMD_BSP
  80. #undef CONFIG_WATCHDOG /* watchdog disabled */
  81. #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
  82. /*
  83. * Miscellaneous configurable options
  84. */
  85. #define CONFIG_SYS_LONGHELP /* undef to save memory */
  86. #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
  87. #if defined(CONFIG_CMD_KGDB)
  88. #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
  89. #else
  90. #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
  91. #endif
  92. #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
  93. #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
  94. #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
  95. #define CONFIG_SYS_DEVICE_NULLDEV 1 /* include nulldev device */
  96. #define CONFIG_SYS_CONSOLE_INFO_QUIET 1 /* don't print console @ startup*/
  97. #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
  98. #define CONFIG_LOOPW 1 /* enable loopw command */
  99. #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
  100. #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
  101. #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
  102. #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */
  103. /* The following table includes the supported baudrates */
  104. #define CONFIG_SYS_BAUDRATE_TABLE \
  105. { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \
  106. 57600, 115200, 230400, 460800, 921600 }
  107. #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
  108. #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
  109. #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
  110. #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
  111. /*-----------------------------------------------------------------------
  112. * PCI stuff
  113. *-----------------------------------------------------------------------
  114. */
  115. #define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
  116. #define PCI_HOST_FORCE 1 /* configure as pci host */
  117. #define PCI_HOST_AUTO 2 /* detected via arbiter enable */
  118. #define CONFIG_PCI /* include pci support */
  119. #define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
  120. #define CONFIG_PCI_PNP /* do pci plug-and-play */
  121. /* resource configuration */
  122. #define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
  123. #define CONFIG_PCI_CONFIG_HOST_BRIDGE 1 /* don't skip host bridge config*/
  124. #define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/
  125. #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */
  126. #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0403 /* PCI Device ID: ARISTO405 */
  127. #define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
  128. #define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
  129. #define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
  130. #define CONFIG_SYS_PCI_PTM2LA 0xfff00000 /* point to flash */
  131. #define CONFIG_SYS_PCI_PTM2MS 0xfff00001 /* 1MB, enable */
  132. #define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
  133. /*-----------------------------------------------------------------------
  134. * Start addresses for the final memory configuration
  135. * (Set up by the startup code)
  136. * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
  137. */
  138. #define CONFIG_SYS_SDRAM_BASE 0x00000000
  139. #define CONFIG_SYS_FLASH_BASE 0xFFFC0000
  140. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  141. #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
  142. #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
  143. /*
  144. * For booting Linux, the board info and command line data
  145. * have to be in the first 8 MB of memory, since this is
  146. * the maximum mapped by the Linux kernel during initialization.
  147. */
  148. #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
  149. /*-----------------------------------------------------------------------
  150. * FLASH organization
  151. */
  152. #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
  153. #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
  154. #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
  155. #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
  156. #define CONFIG_SYS_FLASH_WORD_SIZE unsigned short /* flash word size (width) */
  157. #define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */
  158. #define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */
  159. /*
  160. * The following defines are added for buggy IOP480 byte interface.
  161. * All other boards should use the standard values (CPCI405 etc.)
  162. */
  163. #define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */
  164. #define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */
  165. #define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */
  166. #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
  167. #define CONFIG_ENV_IS_IN_FLASH 1
  168. #define CONFIG_ENV_ADDR 0xFFFB0000 /* Address of Environment Sector*/
  169. #define CONFIG_ENV_SECT_SIZE 0x10000 /* see README - env sector total size */
  170. #define CONFIG_ENV_SIZE 0x04000 /* Size of Environment */
  171. #define CONFIG_ENV_ADDR_REDUND 0xFFFA0000
  172. #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
  173. /*
  174. * Init Memory Controller:
  175. *
  176. * BR0/1 and OR0/1 (FLASH)
  177. */
  178. #define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */
  179. /*-----------------------------------------------------------------------
  180. * External Bus Controller (EBC) Setup
  181. */
  182. /* Memory Bank 0 (Flash Bank 0) initialization */
  183. #define CONFIG_SYS_EBC_PB0AP 0x92015480
  184. #define CONFIG_SYS_EBC_PB0CR 0xFFC5A000 /* BAS=0xFFC,BS=4MB,BU=R/W,BW=16bit */
  185. /* Memory Bank 1 (CAN0, 1, 2, 3) initialization */
  186. #define CONFIG_SYS_EBC_PB1AP 0x01000380 /* enable Ready, BEM=0 */
  187. #define CONFIG_SYS_EBC_PB1CR 0xF0018000 /* BAS=0xF00,BS=1MB,BU=R/W,BW=8bit */
  188. /* Memory Bank 2 (Expension Bus) initialization */
  189. #define CONFIG_SYS_EBC_PB2AP 0x01000280 /* disable Ready, BEM=0 */
  190. #define CONFIG_SYS_EBC_PB2CR 0xF0118000 /* BAS=0xF01,BS=1MB,BU=R/W,BW=8bit */
  191. /* Memory Bank 3 (16552) initialization */
  192. #define CONFIG_SYS_EBC_PB3AP 0x01000380 /* enable Ready, BEM=0 */
  193. #define CONFIG_SYS_EBC_PB3CR 0xF0218000 /* BAS=0xF02,BS=1MB,BU=R/W,BW=8bit */
  194. /* Memory Bank 4 (FPGA regs) initialization */
  195. #define CONFIG_SYS_EBC_PB4AP 0x01005380 /* enable Ready, BEM=0 */
  196. #define CONFIG_SYS_EBC_PB4CR 0xF031C000 /* BAS=0xF03,BS=1MB,BU=R/W,BW=32bit */
  197. /* Memory Bank 5 (Flash Bank 1/DUMMY) initialization */
  198. #define CONFIG_SYS_EBC_PB5AP 0x92015480
  199. #define CONFIG_SYS_EBC_PB5CR 0xFF85A000 /* BAS=0xFF8,BS=4MB,BU=R/W,BW=16bit */
  200. /*-----------------------------------------------------------------------
  201. * Definitions for initial stack pointer and data area (in data cache)
  202. */
  203. #define CONFIG_SYS_INIT_DCACHE_CS 7 /* use cs # 7 for data cache memory */
  204. #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 /* use data cache */
  205. #define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in RAM */
  206. #define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */
  207. #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
  208. #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
  209. /*
  210. * Internal Definitions
  211. *
  212. * Boot Flags
  213. */
  214. #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
  215. #define BOOTFLAG_WARM 0x02 /* Software reboot */
  216. #endif /* __CONFIG_H */